1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Board-specific initialization File: SWARM_INIT.S 5 * 6 * This module contains the assembly-language part of the init 7 * code for this board support package. The routine 8 * "board_earlyinit" lives here. 9 * 10 * Author: Mitch Lichtenberg 11 * 12 ********************************************************************* 13 * 14 * Copyright 2000,2001,2002,2003 15 * Broadcom Corporation. All rights reserved. 16 * 17 * This software is furnished under license and may be used and 18 * copied only in accordance with the following terms and 19 * conditions. Subject to these conditions, you may download, 20 * copy, install, use, modify and distribute modified or unmodified 21 * copies of this software in source and/or binary form. No title 22 * or ownership is transferred hereby. 23 * 24 * 1) Any source code used, modified or distributed must reproduce 25 * and retain this copyright notice and list of conditions 26 * as they appear in the source file. 27 * 28 * 2) No right is granted to use any trade name, trademark, or 29 * logo of Broadcom Corporation. The "Broadcom Corporation" 30 * name may not be used to endorse or promote products derived 31 * from this software without the prior written permission of 32 * Broadcom Corporation. 33 * 34 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 35 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 36 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 37 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 38 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 39 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 41 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 42 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 43 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 44 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 45 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 46 * THE POSSIBILITY OF SUCH DAMAGE. 47 ********************************************************************* */ 48 49 50#include "sbmips.h" 51#include "sb1250_genbus.h" 52#include "sb1250_regs.h" 53#include "sb1250_scd.h" 54#include "bsp_config.h" 55#include "cpu_config.h" 56#include "swarm.h" 57#include "mipsmacros.h" 58#include "sb1250_draminit.h" 59#include "jedec.h" 60 61 .text 62 63 64/* ********************************************************************* 65 * Macros 66 ********************************************************************* */ 67 68 69/* 70 * Define this to send the LED messages to the serial port instead 71 * of to the LEDs. 72 */ 73 74/*#define _SERIAL_PORT_LEDS_*/ 75 76#include "sb1250_uart.h" /* need this for serial defs */ 77 78 79#if (CFG_UNIPROCESSOR_CPU0 && !CFG_MULTI_CPUS) 80/* ********************************************************************* 81 * sb1250_switch_unicpu0 82 * 83 * Switch the processor into uniprocessor CPU0 mode - this 84 * effectively disables CPU1 and changes the CPU to look 85 * like an 1125 with a big L2 cache (an 1150, if you will). 86 * 87 * This routine will do one of two things: If we are already in 88 * uniprocessor mode, it just returns. If we are not in uni 89 * mode, we muck with the SCD to enable uni mode and do a 90 * soft reset. The processor will reset and eventuall wind 91 * back here, where it will notice that the uni mode is turned 92 * on and execution will continue. 93 * 94 * Input parameters: 95 * nothing 96 * 97 * Return value: 98 * nothing 99 * 100 * Registers used: 101 * t0,t1,t2,t3,t4 102 * register s0 must be preserved, it contains the return address 103 ********************************************************************* */ 104 105LEAF(sb1250_switch_unicpu0) 106 107 /* 108 * If the CPU is a 1250 or hybrid, certain initialization has 109 * to be done so that the chip can be used like an 112x. 110 */ 111 112 /* First, figure out what type of SOC we're on. */ 113 ld t0, PHYS_TO_K1(A_SCD_SYSTEM_REVISION) 114 and t1, t0, M_SYS_PART 115 dsrl t1, t1, S_SYS_PART # part number now in t1 116 and t2, t0, M_SYS_REVISION 117 dsrl t2, t2, S_SYS_REVISION # revision now in t2 118 119 /* 120 * Calculating SOC type: 121 * soc_type = part & 0xf; 122 * if (system_revision <= PASS2 123 * && (soc_type == 2 || soc_type == 5)) 124 * soc_type = 0; # really a 1250. 125 */ 126 127 andi t3, t1, 0xf # soc_type (t3) = part & 0xf; 128 bgt t2, K_SYS_REVISION_PASS2, soc_type_ok 129 beq t3, 2, soc_type_bogus 130 beq t3, 5, soc_type_bogus 131 b soc_type_ok 132 133soc_type_bogus: 134 move t3, zero 135 136soc_type_ok: 137 138 /* 139 * We have a 1250 or hybrid. Initialize registers as appropriate. 140 */ 141 142 /* 143 * XXX TO DO: 144 * if pass2, disable half the cache so we look like an 1125. 145 */ 146 147 /* 148 * If we're not already running as a uniprocessor, get us there. 149 */ 150 and t3, t1, 0xf00 151 dsrl t3, t3, 8 # t3 = numcpus 152 153 ld t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) 154 or t4, t4, M_SYS_SB_SOFTRES 155 xor t4, t4, M_SYS_SB_SOFTRES 156 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* clear soft reset */ 157 158 beq t3, 1, 2f 159 160 or t4, t4, M_SYS_SB_SOFTRES | M_SYS_UNICPU0 161 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* go unicpu */ 162 sync 163 1641: b 1b # loop till reset sinks in 165 1662: j ra 167 168END(sb1250_switch_unicpu0) 169#endif 170 171/* ********************************************************************* 172 * BOARD_EARLYINIT() 173 * 174 * Initialize board registers. This is the earliest 175 * time the BSP gets control. This routine cannot assume that 176 * memory is operational, and therefore all code in this routine 177 * must run from registers only. The $ra register must not 178 * be modified, as it contains the return address. 179 * 180 * This routine will be called from uncached space, before 181 * the caches are initialized. If you want to make 182 * subroutine calls from here, you must use the CALLKSEG1 macro. 183 * 184 * Among other things, this is where the GPIO registers get 185 * programmed to make on-board LEDs function, or other startup 186 * that has to be done before anything will work. 187 * 188 * Input parameters: 189 * nothing 190 * 191 * Return value: 192 * nothing 193 ********************************************************************* */ 194 195LEAF(board_earlyinit) 196 197 198 # 199 # If configured, switch the chip into uniprocessor mode 200 # 201#if (CFG_UNIPROCESSOR_CPU0 && !CFG_MULTI_CPUS) 202 move s0,ra # need this to get out of here 203 bal sb1250_switch_unicpu0 # might not return 204 move ra,s0 # restore saved return address 205#endif 206 207 # 208 # Reprogram the SCD to make sure UART0 is enabled. 209 # Some CSWARM boards have the SER0 enable bit when 210 # they're not supposed to, which switches the UART 211 # into synchronous mode. Kill off the SCD bit. 212 # XXX this should be investigated in hardware, as 213 # XXX it is a strap option on the CPU. 214 # 215 216 li t0,PHYS_TO_K1(A_SCD_SYSTEM_CFG) 217 ld t1,0(t0) 218 dli t2,~M_SYS_SER0_ENABLE 219 and t1,t1,t2 220 sd t1,0(t0) 221 222 # 223 # Configure the GPIOs 224 # 225 226 li t0,PHYS_TO_K1(A_GPIO_DIRECTION) 227 li t1,GPIO_OUTPUT_MASK 228 sd t1,0(t0) 229 230 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE) 231 li t1,GPIO_INTERRUPT_MASK 232 sd t1,0(t0) 233 234 # 235 # Turn on the diagnostic LED and turn off the sturgeon NMI 236 # 237 li t0,PHYS_TO_K1(A_GPIO_PIN_SET) 238 li t1,M_GPIO_DEBUG_LED 239 sd t1,0(t0) 240 241 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR) 242 li t1,M_GPIO_STURGEON_NMI 243 sd t1,0(t0) 244 245 246 # 247 # Configure the LEDs 248 # 249 250 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS)) 251 li t1,LEDS_PHYS >> S_IO_ADDRBASE 252 sd t1,R_IO_EXT_START_ADDR(t0) 253 254 li t1,LEDS_SIZE-1 /* Needs to be 1 smaller, se UM for details */ 255 sd t1,R_IO_EXT_MULT_SIZE(t0) 256 257 li t1,LEDS_TIMING0 258 sd t1,R_IO_EXT_TIME_CFG0(t0) 259 260 li t1,LEDS_TIMING1 261 sd t1,R_IO_EXT_TIME_CFG1(t0) 262 263 li t1,LEDS_CONFIG 264 sd t1,R_IO_EXT_CFG(t0) 265 266 267 268 # 269 # Configure the alternate boot ROM 270 # 271 272 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS)) 273 274 li t1,ALT_BOOTROM_PHYS >> S_IO_ADDRBASE 275 sd t1,R_IO_EXT_START_ADDR(t0) 276 277 li t1,ALT_BOOTROM_SIZE-1 278 sd t1,R_IO_EXT_MULT_SIZE(t0) 279 280 li t1,ALT_BOOTROM_TIMING0 281 sd t1,R_IO_EXT_TIME_CFG0(t0) 282 283 li t1,ALT_BOOTROM_TIMING1 284 sd t1,R_IO_EXT_TIME_CFG1(t0) 285 286 li t1,ALT_BOOTROM_CONFIG 287 sd t1,R_IO_EXT_CFG(t0) 288 289 290 291 # 292 # Configure the IDE interface 293 # 294 295 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(IDE_CS)) 296 297 li t1,IDE_PHYS >> S_IO_ADDRBASE 298 sd t1,R_IO_EXT_START_ADDR(t0) 299 300 li t1,IDE_SIZE-1 301 sd t1,R_IO_EXT_MULT_SIZE(t0) 302 303 li t1,IDE_TIMING0 304 sd t1,R_IO_EXT_TIME_CFG0(t0) 305 306 li t1,IDE_TIMING1 307 sd t1,R_IO_EXT_TIME_CFG1(t0) 308 309 li t1,IDE_CONFIG 310 sd t1,R_IO_EXT_CFG(t0) 311 312 313 # 314 # Configure the PCMCIA 315 # 316 317 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(PCMCIA_CS)) 318 319 li t1,PCMCIA_PHYS >> S_IO_ADDRBASE 320 sd t1,R_IO_EXT_START_ADDR(t0) 321 322 li t1,PCMCIA_SIZE-1 323 sd t1,R_IO_EXT_MULT_SIZE(t0) 324 325 li t1,PCMCIA_TIMING0 326 sd t1,R_IO_EXT_TIME_CFG0(t0) 327 328 li t1,PCMCIA_TIMING1 329 sd t1,R_IO_EXT_TIME_CFG1(t0) 330 331 li t1,PCMCIA_CONFIG 332 sd t1,R_IO_EXT_CFG(t0) 333 334 335 /* 336 * Program UART0 (default console) to correct baud rate 337 * so we can output messages before CFE finishes starting. 338 */ 339 340 # Program the mode register for 8 bits/char, no parity 341 342 li t0,PHYS_TO_K1(A_DUART_MODE_REG_1_A) 343 li t1,V_DUART_BITS_PER_CHAR_8 | V_DUART_PARITY_MODE_NONE 344 sd t1,(t0) 345 346 # Program the mode register for 1 stop bit, ignore CTS 347 348 li t0,PHYS_TO_K1(A_DUART_MODE_REG_2_A) 349 li t1,M_DUART_STOP_BIT_LEN_1 350 sd t1,(t0) 351 352 # Program the baud rate to 115200 353 354 li t0,PHYS_TO_K1(A_DUART_CLK_SEL_A) 355 li t1,V_DUART_BAUD_RATE(CFG_SERIAL_BAUD_RATE) 356 sd t1,(t0) 357 358 # Dont use any interrupts 359 360 li t0,PHYS_TO_K1(A_DUART_IMR) 361 ld t1,(t0) 362 and t1,~M_DUART_IMR_ALL_A 363 sd t1,(t0) 364 365 # Enable sending and receiving 366 367 li t0,PHYS_TO_K1(A_DUART_CMD_A) 368 li t1,M_DUART_RX_EN | M_DUART_TX_EN 369 sd t1,(t0) 370 371 372 j ra 373 374END(board_earlyinit) 375 376 377/* ********************************************************************* 378 * BOARD_DRAMINFO 379 * 380 * Return the address of the DRAM information table 381 * 382 * Input parameters: 383 * nothing 384 * 385 * Return value: 386 * v0 - DRAM info table, return 0 to use default table 387 ********************************************************************* */ 388 389 390LEAF(board_draminfo) 391 392#ifdef _HARDWIRED_MEMORY_TABLE 393 la v0,myinfo 394#else 395 move v0,zero # auto configure 396#endif 397 j ra 398 399 400 401myinfo: 402 DRAM_GLOBALS(CFG_DRAM_INTERLEAVE) 403 404 405 /* 128MB on MC0 (SDRAM) */ 406 DRAM_CHAN_CFG(MC_CHAN0, DRT10(8,0), JEDEC,CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0) 407 DRAM_CS_GEOM(MC_CS0, 12, 8, 2) 408 DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0, 45, DRT4(20,0), DRT4(15,0), DRT4(20,0), 0, 0) 409 DRAM_EOT 410 411 412END(board_draminfo) 413 414 415/* ********************************************************************* 416 * BOARD_CONOUT 417 * 418 * Transmit a single character via UART A 419 * 420 * Input parameters: 421 * a0 - character to transmit (low-order 8 bits) 422 * 423 * Return value: 424 * nothing 425 * 426 * Registers used: 427 * t0,t1 428 ********************************************************************* */ 429 430LEAF(board_conout) 431_board_conout: 432 433 # Wait until there is space in the transmit buffer 434 4351: li t0,PHYS_TO_K1(A_DUART_STATUS_A) 436 ld t1,(t0) # Get status bits 437 and t1,M_DUART_TX_RDY # test for ready 438 beq t1,0,1b # keep going till ready 439 440 # Okay, now send the character. 441 442 li t0,PHYS_TO_K1(A_DUART_TX_HOLD_A) 443 sd a0,(t0) 444 445 # done! 446 447 j ra 448 449END(board_conout) 450 451/* ********************************************************************* 452 * BOARD_CONIN 453 * 454 * Receive a character from UART A 455 * 456 * Input parameters: 457 * nothing 458 * 459 * Return value: 460 * v0 - received character, or -1 if no characters waiting 461 * 462 * Registers used: 463 * t0,t1 464 ********************************************************************* */ 465 466LEAF(board_conin) 467 468 li v0,-1 469 j ra 470END(board_conin) 471 472 473/* ********************************************************************* 474 * BOARD_SETLEDS(x) 475 * 476 * Set LEDs for boot-time progress indication. Not used if 477 * the board does not have progress LEDs. This routine 478 * must not call any other routines, since it may be invoked 479 * either from KSEG0 or KSEG1 and it may be invoked 480 * whether or not the icache is operational. 481 * 482 * Input parameters: 483 * a0 - LED value (8 bits per character, 4 characters) 484 * 485 * Return value: 486 * nothing 487 * 488 * Registers used: 489 * t0,t1,t2,t3 490 ********************************************************************* */ 491 492 493#define LED_CHAR0 (32+8*3) 494#define LED_CHAR1 (32+8*2) 495#define LED_CHAR2 (32+8*1) 496#define LED_CHAR3 (32+8*0) 497 498LEAF(board_setleds) 499 500#ifdef _SERIAL_PORT_LEDS_ 501 502 /* 503 * Sending to serial port 504 */ 505 move t3,ra 506 move t2,a0 507 508 li a0,'[' 509 bal _board_conout 510 511 move a0,t2 512 rol a0,8 513 bal _board_conout 514 rol a0,8 515 bal _board_conout 516 rol a0,8 517 bal _board_conout 518 rol a0,8 519 bal _board_conout 520 521 li a0,']' 522 bal _board_conout 523 524 move ra,t3 525 j ra 526 527#else 528 529 /* 530 * Sending to LEDs 531 */ 532 li t0,PHYS_TO_K1(LEDS_PHYS) 533 534 rol a0,a0,8 535 and t1,a0,0xFF 536 sb t1,LED_CHAR0(t0) 537 538 rol a0,a0,8 539 and t1,a0,0xFF 540 sb t1,LED_CHAR1(t0) 541 542 rol a0,a0,8 543 and t1,a0,0xFF 544 sb t1,LED_CHAR2(t0) 545 546 rol a0,a0,8 547 and t1,a0,0xFF 548 sb t1,LED_CHAR3(t0) 549 550 j ra 551#endif 552 553END(board_setleds) 554 555