1/* ********************************************************************* 2 * BCM1280/BCM1480 Board Support Package 3 * 4 * Board-specific initialization File: BCM91480HT_INIT.S 5 * 6 * This module contains the assembly-language part of the init 7 * code for this board support package. The routine 8 * "board_earlyinit" lives here. 9 * 10 * Author: Mitch Lichtenberg 11 * 12 ********************************************************************* 13 * 14 * Copyright 2000,2001,2002,2003 15 * Broadcom Corporation. All rights reserved. 16 * 17 * This software is furnished under license and may be used and 18 * copied only in accordance with the following terms and 19 * conditions. Subject to these conditions, you may download, 20 * copy, install, use, modify and distribute modified or unmodified 21 * copies of this software in source and/or binary form. No title 22 * or ownership is transferred hereby. 23 * 24 * 1) Any source code used, modified or distributed must reproduce 25 * and retain this copyright notice and list of conditions 26 * as they appear in the source file. 27 * 28 * 2) No right is granted to use any trade name, trademark, or 29 * logo of Broadcom Corporation. The "Broadcom Corporation" 30 * name may not be used to endorse or promote products derived 31 * from this software without the prior written permission of 32 * Broadcom Corporation. 33 * 34 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 35 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 36 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 37 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 38 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 39 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 41 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 42 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 43 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 44 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 45 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 46 * THE POSSIBILITY OF SUCH DAMAGE. 47 ********************************************************************* */ 48 49 50#include "sbmips.h" 51#include "bcm1480_regs.h" 52#include "bcm1480_scd.h" 53#include "bcm1480_l2c.h" 54#include "sb1250_genbus.h" 55#include "bcm1480_draminit.h" 56#include "jedec.h" 57#include "bsp_config.h" 58#include "cpu_config.h" 59#include "mipsmacros.h" 60#include "bcm91480ht.h" 61 62 .text 63 64 65 66/* ********************************************************************* 67 * Macros 68 ********************************************************************* */ 69 70 71#define _SERIAL_PORT_LEDS_ 72 73 74#ifdef _SERIAL_PORT_LEDS_ 75#include "sb1250_uart.h" 76#endif 77 78/* ********************************************************************* 79 * LED macros 80 ********************************************************************* */ 81 82#define SETLEDS1(a,b,c,d) \ 83 li a0,(((a)<<24)|((b)<<16)|((c)<<8)|(d)) ; \ 84 JAL_KSEG1(board_setleds) 85#define SETLEDS(a,b,c,d) \ 86 li a0,(((a)<<24)|((b)<<16)|((c)<<8)|(d)) ; \ 87 JAL_KSEG1(board_setleds) 88 89 90/* ********************************************************************* 91 * BOARD_EARLYINIT() 92 * 93 * Initialize board registers. This is the earliest 94 * time the BSP gets control. This routine cannot assume that 95 * memory is operational, and therefore all code in this routine 96 * must run from registers only. The $ra register must not 97 * be modified, as it contains the return address. 98 * 99 * This routine will be called from uncached space, before 100 * the caches are initialized. If you want to make 101 * subroutine calls from here, you must use the JAL_KSEG1 macro. 102 * 103 * Among other things, this is where the GPIO registers get 104 * programmed to make on-board LEDs function, or other startup 105 * that has to be done before anything will work. 106 * 107 * Input parameters: 108 * nothing 109 * 110 * Return value: 111 * nothing 112 ********************************************************************* */ 113 114LEAF(board_earlyinit) 115 116 move s0, ra 117 118 # 119 # Configure the GPIOs 120 # 121 122 li t0,PHYS_TO_K1(A_GPIO_DIRECTION) 123 li t1,GPIO_OUTPUT_MASK 124 sd t1,0(t0) 125 126 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE) 127 li t1,GPIO_INTERRUPT_MASK 128 sd t1,0(t0) 129 130#if CFG_L2_RAM /* Variant for using L2 as memory via TLB for 32 bits */ 131 # 132 # Set up the L2 cache to be used as SRAM by setting the 133 # way_disable address (the actual flush will be done by 134 # sb1250_l2cache_init). 135 # 136 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_LO(0x00)) 137 sd zero,(t0) 138 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_HI(0x08)) 139 sd zero,(t0) 140 141 # Use the result of a load to stall the pipe here. 142 # Ref sec 5.4.2 (aka page 92, 1250_1125UM100-R). 143 # XXX Probably not necessary for these early, global accesses. 144 ld t0,(t0) 145 addu t0,t0,t0 146#endif 147 148 149 # 150 # Set the PCIX default frequency 151 # 152 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR) 153 li t1,(M_GPIO_PCIX_FREQALL) 154 sd t1,0(t0) 155 156 li t0,PHYS_TO_K1(A_GPIO_PIN_SET) 157 li t1,(M_GPIO_PCIX_FREQ33) 158 sd t1,0(t0) 159 160 161 # 162 # Configure the alternate boot ROM 163 # 164 165 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS)) 166 167 li t1,ALT_BOOTROM_PHYS >> S_IO_ADDRBASE 168 sd t1,R_IO_EXT_START_ADDR(t0) 169 170 li t1,ALT_BOOTROM_SIZE-1 171 sd t1,R_IO_EXT_MULT_SIZE(t0) 172 173 li t1,ALT_BOOTROM_TIMING0 174 sd t1,R_IO_EXT_TIME_CFG0(t0) 175 176 li t1,ALT_BOOTROM_TIMING1 177 sd t1,R_IO_EXT_TIME_CFG1(t0) 178 179 li t1,ALT_BOOTROM_CONFIG 180 sd t1,R_IO_EXT_CFG(t0) 181 182 183 # 184 # Configure the LEDs 185 # 186 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS)) 187 li t1,LEDS_PHYS >> S_IO_ADDRBASE 188 sd t1,R_IO_EXT_START_ADDR(t0) 189 190 li t1,LEDS_SIZE-1 /* Needs to be 1 smaller, se UM for details */ 191 sd t1,R_IO_EXT_MULT_SIZE(t0) 192 193 li t1,LEDS_TIMING0 194 sd t1,R_IO_EXT_TIME_CFG0(t0) 195 196 li t1,LEDS_TIMING1 197 sd t1,R_IO_EXT_TIME_CFG1(t0) 198 199 li t1,LEDS_CONFIG 200 sd t1,R_IO_EXT_CFG(t0) 201 202 # 203 # Configure the BATTERY BACKUP CONTROLLER CPLD 204 # 205 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(BATTERY_CS)) 206 li t1,BATTERY_PHYS >> S_IO_ADDRBASE 207 sd t1,R_IO_EXT_START_ADDR(t0) 208 209 li t1,BATTERY_SIZE-1 /* Needs to be 1 smaller, se UM for details */ 210 sd t1,R_IO_EXT_MULT_SIZE(t0) 211 212 li t1,BATTERY_TIMING0 213 sd t1,R_IO_EXT_TIME_CFG0(t0) 214 215 li t1,BATTERY_TIMING1 216 sd t1,R_IO_EXT_TIME_CFG1(t0) 217 218 li t1,BATTERY_CONFIG 219 sd t1,R_IO_EXT_CFG(t0) 220 221 # 222 # Make sure that the mailbox registers are cleared 223 # 224 225 li t0,PHYS_TO_K1(A_BCM1480_IMR_REGISTER(0,R_BCM1480_IMR_MAILBOX_0_CLR_CPU)) 226 nor t1, zero, zero 227 sd t1,(t0) 228 li t0,PHYS_TO_K1(A_BCM1480_IMR_REGISTER(0,R_BCM1480_IMR_MAILBOX_1_CLR_CPU)) 229 sd t1,(t0) 230 231#ifdef _SERIAL_PORT_LEDS_ 232 233 # Program the mode register for 8 bits/char, no parity 234 235 li t0,PHYS_TO_K1(A_DUART_MODE_REG_1_A) 236 li t1,V_DUART_BITS_PER_CHAR_8 | V_DUART_PARITY_MODE_NONE 237 sd t1,(t0) 238 239 # Program the mode register for 1 stop bit, ignore CTS 240 241 li t0,PHYS_TO_K1(A_DUART_MODE_REG_2_A) 242 li t1,M_DUART_STOP_BIT_LEN_1 243 sd t1,(t0) 244 245 # Program the baud rate to 115200 246 247 li t0,PHYS_TO_K1(A_DUART_CLK_SEL_A) 248 li t1,V_DUART_BAUD_RATE(CFG_SERIAL_BAUD_RATE) 249 sd t1,(t0) 250 251 # Dont use any interrupts 252 253 li t0,PHYS_TO_K1(A_DUART_IMR) 254 ld t1,(t0) 255 and t1,~M_DUART_IMR_ALL_A 256 sd t1,(t0) 257 258 # Enable sending and receiving 259 260 li t0,PHYS_TO_K1(A_DUART_CMD_A) 261 li t1,M_DUART_RX_EN | M_DUART_TX_EN 262 sd t1,(t0) 263 264#endif 265 266 move ra, s0 267 j ra 268 269END(board_earlyinit) 270 271 272/* ********************************************************************* 273 * BOARD_DRAMINFO 274 * 275 * Return the address of the DRAM information table 276 * 277 * Input parameters: 278 * nothing 279 * 280 * Return value: 281 * v0 - DRAM info table, return 0 to use default table 282 ********************************************************************* */ 283 284 285#define VPN2_256K(va) (((va)>>(13+6))<<6) 286#define PFN(pa) ((pa)>>12) 287#define PGMASK_256K (0x3F<<13) 288 289LEAF(board_draminfo) 290 291 292#if CFG_L2_RAM /* Variant for using L2 as memory via TLB for 32 bits */ 293 /* 294 * Map 512K of L2 space to VA 0x300000 using a pair of 256K 295 * page frames. 296 * This is an abuse of the function, but it is called at the 297 * correct point in the initialization sequence, where adding 298 * new function calls is delicate. 299 */ 300 301 .set push 302 .set mips64 303 304 dli v0,(VPN2_256K(0x00300000)<<13) 305 dmtc0 v0,C0_TLBHI 306 li v0,(PFN(0xd0300000)<<6 | (5<<3) | 7) 307 mtc0 v0,C0_TLBLO0 308 li v0,(PFN(0xd0340000)<<6 | (5<<3) | 7) 309 mtc0 v0,C0_TLBLO1 310 li v0,PGMASK_256K 311 mtc0 v0,C0_PGMASK 312 li v0,1 313 mtc0 v0,C0_WIRED 314 li v0,0 315 mtc0 v0,C0_INDEX 316 tlbwi 317 318 HAZARD 319 320 .set pop 321#endif /* CFG_L2_RAM */ 322 323 /* 324 * Return pointer to DRAM table. 325 */ 326 327 la v0,dramtab 328 j ra 329 330 331dramtab: 332 /* 333 * Big Dipper DRAM 334 * Four 32 bit ECC channels 335 * channel 0 and 1 single slot with ODT enable 336 * channel 2 and 3 two slots ODT static on 337 * 338 * DRAM_CHAN_CFG(chan,tMEMCLK,tROUNDTRIP,chantype,dramtype,pagepolicy,csintlv,ecc,flg) 339 * DRAM_CS_SPD(csel,flags,chan,dev) 340 * DRAM_CS_TIMING2(tAL,tRTP,tRAP) 341 * DRAM_CHAN_DLLCFG2(addrfreq,dqicoarse,dqifreq,dqocoarse,dqofreq,dlldefault,dllfreq,dllbypass) 342 * DRAM_CHAN_ODTCFG(odt0,odt2,odt4,odt6,odt_odd_en,odt_mc_value,odt_dram_value) 343 * DRAM_CHAN_ODTCFG2(odt0,odt2,odt4,odt6,odt_odd_en,odt_mc_value,odt_dram_value) 344 * DRAM_CHAN_ADDRCOARSE(addrcoarse_reg,addrcoarse_unbuf) 345 * 346 * tROUNDTRIP is trace delay + edge delay(600ps) of MCLK + DSQ 347 */ 348 349 DRAM_GLOBALS(MC_01CHANINTLV) 350 DRAM_CHAN_CFG(MC_CHAN0, DRT10(3,0), DRT10(3,0), MC_32BIT_CHAN, DRAM_TYPE_SPD, CASCHECK,CSINTLV_2CS ,0 , 0 ) 351 DRAM_CS_SPD(MC_CS0,0,DRAM_SMBUS_CHAN_J4_1,DRAM_SMBUS_DEV_J4_1) 352 DRAM_CHAN_ODTCFG(0x30,0x00,0x00,0x00,CS_ODD_ODT_EN,ODT_150,ODT_75) 353 354 DRAM_CHAN_CFG(MC_CHAN1, DRT10(3,0), DRT10(3,0), MC_32BIT_CHAN, DRAM_TYPE_SPD, CASCHECK,CSINTLV_2CS , 0, 0 ) 355 DRAM_CS_SPD(MC_CS0,0,DRAM_SMBUS_CHAN_J4_1,DRAM_SMBUS_DEV_J4_1) 356 DRAM_CHAN_ODTCFG(0x30,0x00,0x00,0x00,CS_ODD_ODT_EN,ODT_150,ODT_75) 357 358 /* 359 * Channels 2 and 3 360 * 4 rank no ODT 361 */ 362/* 363 * MC_NOCHANINTLV 364 * MC_01CHANINTLV 365 * MC_23CHANINTLV Valid in 32-bit channels only 366 * MC_01_23CHANINTLV Valid in 32-bit channels only 367 * MC_FULLCHANINTLV Valid in 32-bit channels only 368 */ 369 370/* 371 * NOCSINTLV 372 * CSINTLV_2CS 373 * CSINTLV_4CS 374 * CSINTLV_8CS Valid in 64-bit channels only 375 */ 376 377 DRAM_CHAN_CFG(MC_CHAN2, DRT10(3,0), DRT10(3,5), MC_32BIT_CHAN, DRAM_TYPE_SPD, CASCHECK, 0, 0, MCFLG_2T | MCFLG_NO_ODT_CS) 378 DRAM_CS_SPD(MC_CS0,0,DRAM_SMBUS_CHAN_J5_2,DRAM_SMBUS_DEV_J5_2) 379 DRAM_CS_SPD(MC_CS2,0,DRAM_SMBUS_CHAN_J25_2,DRAM_SMBUS_DEV_J25_2) 380 DRAM_CHAN_ODTCFG(0x00,0x00,0x00,0x00,0x00,ODT_150,ODT_75) 381 DRAM_CHAN_ODTCFG2(0x00,0x00,0x00,0x00,0x00,ODT_150,ODT_75) 382 DRAM_CHAN_ADDRCOARSE(0x0,0x0c) 383 384 DRAM_CHAN_CFG(MC_CHAN3, DRT10(3,0), DRT10(3,5), MC_32BIT_CHAN, DRAM_TYPE_SPD, CASCHECK, 0, 0, MCFLG_2T | MCFLG_NO_ODT_CS) 385 DRAM_CS_SPD(MC_CS0,0,DRAM_SMBUS_CHAN_J5_2,DRAM_SMBUS_DEV_J5_2) 386 DRAM_CS_SPD(MC_CS2,0,DRAM_SMBUS_CHAN_J25_2,DRAM_SMBUS_DEV_J25_2) 387 DRAM_CHAN_ODTCFG(0x00,0x00,0x00,0x00,0x00,ODT_150,ODT_75) 388 DRAM_CHAN_ODTCFG2(0x00,0x00,0x00,0x00,0x00,ODT_150,ODT_75) 389 DRAM_CHAN_ADDRCOARSE(0x0,0x0c) 390 391 DRAM_EOT 392 393END(board_draminfo) 394 395 396/* ********************************************************************* 397 * BOARD_PIAI2_TXCHAR 398 * 399 * Transmit a single character via UART A 400 * 401 * Input parameters: 402 * a0 - character to transmit (low-order 8 bits) 403 * 404 * Return value: 405 * nothing 406 * 407 * Registers used: 408 * t0,t1 409 ********************************************************************* */ 410 411#ifdef _PROMICE_PORT_LEDS_ 412 413LEAF(board_piai2_txchar) 414 415 # Wait until there is space in the transmit buffer 416 417 li t0,PHYS_TO_K1(BOARD_PROMICE_BASE) 418 4191: lb t1,BOARD_PROMICE_STATUS(t0) 420 andi t1,TDA 421 bne t1,zero,1b 422 423 # Okay, now send the character. 424 425 sb a0,BOARD_PROMICE_ZERO(t0) 426 427 # done! 428 429 j ra 430 431END(board_piai2_txchar) 432#endif 433 434/* ********************************************************************* 435 * BOARD_UARTA_TXCHAR 436 * 437 * Transmit a single character via UART A 438 * 439 * Input parameters: 440 * a0 - character to transmit (low-order 8 bits) 441 * 442 * Return value: 443 * nothing 444 * 445 * Registers used: 446 * t0,t1 447 ********************************************************************* */ 448 449#ifdef _SERIAL_PORT_LEDS_ 450board_uarta_txchar: 451 452 # Wait until there is space in the transmit buffer 453 4541: li t0,PHYS_TO_K1(A_DUART_STATUS_A) 455 ld t1,(t0) # Get status bits 456 and t1,M_DUART_TX_RDY # test for ready 457 beq t1,0,1b # keep going till ready 458 459 # Okay, now send the character. 460 461 li t0,PHYS_TO_K1(A_DUART_TX_HOLD_A) 462 sd a0,(t0) 463 464 # done! 465 466 j ra 467 468 469#endif 470 471/* ********************************************************************* 472 * BOARD_SETLEDS(x) 473 * 474 * Set LEDs for boot-time progress indication. Not used if 475 * the board does not have progress LEDs. This routine 476 * must not call any other routines, since it may be invoked 477 * either from KSEG0 or KSEG1 and it may be invoked 478 * whether or not the icache is operational. 479 * 480 * Input parameters: 481 * a0 - LED value (8 bits per character, 4 characters) 482 * 483 * Return value: 484 * nothing 485 * 486 * Registers used: 487 * t0,t1,t2,t3 488 ********************************************************************* */ 489 490 491#define LED_CHAR0 (32+8*3) 492#define LED_CHAR1 (32+8*2) 493#define LED_CHAR2 (32+8*1) 494#define LED_CHAR3 (32+8*0) 495 496 497LEAF(board_setleds) 498 499 /* 500 * Sending to LEDs 501 */ 502 503 li t0,PHYS_TO_K1(LEDS_PHYS) 504 505 rol a0,a0,8 506 and t1,a0,0xFF 507 sb t1,LED_CHAR0(t0) 508 509 rol a0,a0,8 510 and t1,a0,0xFF 511 sb t1,LED_CHAR1(t0) 512 513 rol a0,a0,8 514 and t1,a0,0xFF 515 sb t1,LED_CHAR2(t0) 516 517 rol a0,a0,8 518 and t1,a0,0xFF 519 sb t1,LED_CHAR3(t0) 520 521 522 523#ifdef _SERIAL_PORT_LEDS_ 524 move t3,ra 525 move t2,a0 526 527 li a0,'[' 528 bal board_uarta_txchar 529 530 move a0,t2 531 rol a0,8 532 bal board_uarta_txchar 533 rol a0,8 534 bal board_uarta_txchar 535 rol a0,8 536 bal board_uarta_txchar 537 rol a0,8 538 bal board_uarta_txchar 539 540 li a0,']' 541 bal board_uarta_txchar 542 li a0,13 543 bal board_uarta_txchar 544 li a0,10 545 bal board_uarta_txchar 546 547 move a0,t2 548 move ra,t3 549 550#endif 551 552 j ra 553 554END(board_setleds) 555 556LEAF(board_get_config) 557 .set push 558 .set noreorder 559 .set nomacro 560 lui t0, %hi(PHYS_TO_K1(A_SCD_SYSTEM_CFG)) 561 ld t0, %lo(PHYS_TO_K1(A_SCD_SYSTEM_CFG))(t0) 562 dsrl t0, t0, S_BCM1480_SYS_CONFIG 563 li v0, (M_BCM1480_SYS_CONFIG >> S_BCM1480_SYS_CONFIG) 564 and v0, v0, t0 565 566 jr ra 567 nop 568 .set pop 569END(board_get_config) 570 571 572 573