1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Board-specific initialization File: SENTOSA_INIT.S 5 * 6 * This module contains the assembly-language part of the init 7 * code for this board support package. The routine 8 * "board_earlyinit" lives here. 9 * 10 * Author: Mitch Lichtenberg 11 * 12 ********************************************************************* 13 * 14 * Copyright 2000,2001,2002,2003 15 * Broadcom Corporation. All rights reserved. 16 * 17 * This software is furnished under license and may be used and 18 * copied only in accordance with the following terms and 19 * conditions. Subject to these conditions, you may download, 20 * copy, install, use, modify and distribute modified or unmodified 21 * copies of this software in source and/or binary form. No title 22 * or ownership is transferred hereby. 23 * 24 * 1) Any source code used, modified or distributed must reproduce 25 * and retain this copyright notice and list of conditions 26 * as they appear in the source file. 27 * 28 * 2) No right is granted to use any trade name, trademark, or 29 * logo of Broadcom Corporation. The "Broadcom Corporation" 30 * name may not be used to endorse or promote products derived 31 * from this software without the prior written permission of 32 * Broadcom Corporation. 33 * 34 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 35 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 36 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 37 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 38 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 39 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 41 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 42 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 43 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 44 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 45 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 46 * THE POSSIBILITY OF SUCH DAMAGE. 47 ********************************************************************* */ 48 49 50#include "sbmips.h" 51#include "sb1250_genbus.h" 52#include "sb1250_regs.h" 53#include "sb1250_scd.h" 54#include "bsp_config.h" 55#include "cpu_config.h" 56#include "mipsmacros.h" 57#include "sentosa.h" 58#include "sb1250_draminit.h" 59 60 .text 61 62 63 64/* ********************************************************************* 65 * Macros 66 ********************************************************************* */ 67 68/* #define _SERIAL_PORT_LEDS_ */ 69 70#ifdef _SERIAL_PORT_LEDS_ 71#include "sb1250_uart.h" 72#endif 73 74/* ********************************************************************* 75 * BOARD_EARLYINIT() 76 * 77 * Initialize board registers. This is the earliest 78 * time the BSP gets control. This routine cannot assume that 79 * memory is operational, and therefore all code in this routine 80 * must run from registers only. The $ra register must not 81 * be modified, as it contains the return address. 82 * 83 * This routine will be called from uncached space, before 84 * the caches are initialized. If you want to make 85 * subroutine calls from here, you must use the CALLKSEG1 macro. 86 * 87 * Among other things, this is where the GPIO registers get 88 * programmed to make on-board LEDs function, or other startup 89 * that has to be done before anything will work. 90 * 91 * Input parameters: 92 * nothing 93 * 94 * Return value: 95 * nothing 96 ********************************************************************* */ 97 98LEAF(board_earlyinit) 99 100 101 # 102 # Configure the GPIOs 103 # 104 105 li t0,PHYS_TO_K1(A_GPIO_DIRECTION) 106 li t1,GPIO_OUTPUT_MASK 107 sd t1,0(t0) 108 109 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE) 110 li t1,GPIO_INTERRUPT_MASK 111 sd t1,0(t0) 112 113 # 114 # Turn off the diagnostic LED. 115 # 116 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR) 117 li t1,M_GPIO_DEBUG_LED 118 sd t1,0(t0) 119 120 121 # 122 # Configure the alternate boot ROM 123 # 124 125 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS)) 126 127 li t1,ALT_BOOTROM_PHYS >> S_IO_ADDRBASE 128 sd t1,R_IO_EXT_START_ADDR(t0) 129 130 li t1,ALT_BOOTROM_SIZE-1 131 sd t1,R_IO_EXT_MULT_SIZE(t0) 132 133 li t1,ALT_BOOTROM_TIMING0 134 sd t1,R_IO_EXT_TIME_CFG0(t0) 135 136 li t1,ALT_BOOTROM_TIMING1 137 sd t1,R_IO_EXT_TIME_CFG1(t0) 138 139 li t1,ALT_BOOTROM_CONFIG 140 sd t1,R_IO_EXT_CFG(t0) 141 142 # 143 # Make sure that the mailbox register is cleared 144 # 145 146 li t0,PHYS_TO_K1(A_IMR_REGISTER(0,R_IMR_MAILBOX_CLR_CPU)) 147 nor t1, zero, zero 148 sd t1,(t0) 149 150#ifdef _SERIAL_PORT_LEDS_ 151 152 # Program the mode register for 8 bits/char, no parity 153 154 li t0,PHYS_TO_K1(A_DUART_MODE_REG_1_A) 155 li t1,V_DUART_BITS_PER_CHAR_8 | V_DUART_PARITY_MODE_NONE 156 sd t1,(t0) 157 158 # Program the mode register for 1 stop bit, ignore CTS 159 160 li t0,PHYS_TO_K1(A_DUART_MODE_REG_2_A) 161 li t1,M_DUART_STOP_BIT_LEN_1 162 sd t1,(t0) 163 164 # Program the baud rate to 115200 165 166 li t0,PHYS_TO_K1(A_DUART_CLK_SEL_A) 167 li t1,V_DUART_BAUD_RATE(CFG_SERIAL_BAUD_RATE) 168 sd t1,(t0) 169 170 # Dont use any interrupts 171 172 li t0,PHYS_TO_K1(A_DUART_IMR) 173 ld t1,(t0) 174 and t1,~M_DUART_IMR_ALL_A 175 sd t1,(t0) 176 177 # Enable sending and receiving 178 179 li t0,PHYS_TO_K1(A_DUART_CMD_A) 180 li t1,M_DUART_RX_EN | M_DUART_TX_EN 181 sd t1,(t0) 182 183#endif 184 185 186 j ra 187 188END(board_earlyinit) 189 190 191/* ********************************************************************* 192 * BOARD_DRAMINFO 193 * 194 * Return the address of the DRAM information table 195 * 196 * Input parameters: 197 * nothing 198 * 199 * Return value: 200 * v0 - DRAM info table, return 0 to use default table 201 ********************************************************************* */ 202 203 204LEAF(board_draminfo) 205 206 # 207 # This board has soldered-down memory. 208 # 209 210 la v0,dramtab 211 j ra 212 213 214#if !defined(_SENTOSA_F_) 215 216 /* 217 * Regular DRAM for regular Sentosas 218 */ 219 220dramtab: 221 222 /* 223 * DRAM globals: interleave OK 224 */ 225 226 DRAM_GLOBALS(CFG_DRAM_INTERLEAVE) 227 228 229 /* 230 * 128MB on MC 0 (JEDEC SDRAM) 231 * Samsung K4H561638B - 16Mx16 chips 232 * 233 * Minimum tMEMCLK: 7.5ns (133Mhz max freq) 234 * 235 * CS0 Geometry: 13 rows, 9 columns, 2 bankbits 236 * 237 * 128khz refresh, CAS Latency 2.5 238 * Timing (ns): tCK=7.50 tRAS=45 tRP=20.00 tRRD=15.0 tRCD=20.0 tRFC=auto tRC=auto 239 * 240 * Clock Config: Addrskew 0x08, DQOskew 0x08, DQIskew 0x08, addrdrive 0x07, datadrive 0x07, clockdrive 0x0F 241 */ 242 243 DRAM_CHAN_CFG(MC_CHAN0, DRT10(7,5), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, MCFLG_DS_REDUCED) 244 DRAM_CHAN_CLKCFG(0x08,0x08,0x08,0x07,0x07,0x0F) 245 DRAM_CS_GEOM(MC_CS0, 13, 9, 2) 246 DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_128khz, JEDEC_CASLAT_25, 0, 45, DRT4(20,0), DRT4(15,0), DRT4(20,0), 0, 0) 247 248 249 /* 250 * 128MB on MC 1 (JEDEC SDRAM) 251 * Samsung K4H561638B - 16Mx16 chips 252 * 253 * Minimum tMEMCLK: 7.5ns (133Mhz max freq) 254 * 255 * CS0 Geometry: 13 rows, 9 columns, 2 bankbits 256 * 257 * 128khz refresh, CAS Latency 2.5 258 * Timing (ns): tCK=7.50 tRAS=45 tRP=20.00 tRRD=15.0 tRCD=20.0 tRFC=auto tRC=auto 259 * 260 * Clock Config: Addrskew 0x08, DQOskew 0x08, DQIskew 0x08, addrdrive 0x07, datadrive 0x07, clockdrive 0x0F 261 */ 262 263 DRAM_CHAN_CFG(MC_CHAN1, DRT10(7,5), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, MCFLG_DS_REDUCED) 264 DRAM_CHAN_CLKCFG(0x08,0x08,0x08,0x07,0x07,0x0F) 265 DRAM_CS_GEOM(MC_CS0, 13, 9, 2) 266 DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_128khz, JEDEC_CASLAT_25, 0, 45, DRT4(20,0), DRT4(15,0), DRT4(20,0), 0, 0) 267 268 DRAM_EOT 269 270#else 271 /* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */ 272 /* 273 * Special Sentosa stuffed with Toshiba TC59LM814 FCRAM parts. 274 */ 275 276dramtab: 277 278 DRAM_GLOBALS(CFG_DRAM_INTERLEAVE) 279 /* 280 * 128MB on MC 0 (FCRAM) 281 * Toshiba TC59LM814CFT-50 282 * 283 * Minimum tMEMCLK: 5.5ns (180Mhz max freq) 284 * 285 * CS0 Geometry : 15 rows, 7 columns, 2 bankbits 286 * 287 * 128khz refresh, CAS Latency 3.0 288 * Timing (ns): tCK=5.50 tRAS=26 tRP=6.50 tRRD=13.0 tRCD=6.50 tRFC=97 tRC=auto 289 * 290 * Clock Config: Addrskew 0x08, DQOskew 0x08, DQIskew 0x08, addrdrive 0x07, datadrive 0x07, clockdrive 0x07 291 */ 292 293 DRAM_CHAN_CFG2(MC_CHAN0, DRT10(5,0), DRT10(2,5), FCRAM, CLOSED, BLKSIZE32, NOCSINTLV, CFG_DRAM_ECC, 0) 294 DRAM_CHAN_CLKCFG(0x08,0x08,0x08,0x07,0x07,0x07) 295 296 DRAM_CS_GEOM(MC_CS0, 15, 7, 2) 297 DRAM_CS_TIMING(DRT10(5,0), JEDEC_RFSH_128khz, JEDEC_CASLAT_30, 0, 26, DRT4(6,50) ,DRT4(13,0), DRT4(6,50), 97 , 0) 298 299 300 /* 301 * 128MB on MC 1 (FCRAM) 302 * Toshiba TC59LM814CFT-50 303 * 304 * Minimum tMEMCLK: 5.5ns (180Mhz max freq) 305 * 306 * CS0 Geometry : 15 rows, 7 columns, 2 bankbits 307 * 308 * 128khz refresh, CAS Latency 3.0 309 * Timing (ns): tCK=5.50 tRAS=26 tRP=6.50 tRRD=13.0 tRCD=6.50 tRFC=97 tRC=auto 310 * 311 * Clock Config: Addrskew 0x08, DQOskew 0x08, DQIskew 0x08, addrdrive 0x07, datadrive 0x07, clockdrive 0x07 312 */ 313 314 DRAM_CHAN_CFG2(MC_CHAN1, DRT10(5,0), DRT10(2,5), FCRAM, CLOSED, BLKSIZE32, NOCSINTLV, CFG_DRAM_ECC, 0) 315 DRAM_CHAN_CLKCFG(0x08,0x08,0x08,0x07,0x07,0x07) 316 317 DRAM_CS_GEOM(MC_CS0, 15, 7, 2) 318 DRAM_CS_TIMING(DRT10(5,0), JEDEC_RFSH_128khz, JEDEC_CASLAT_30, 0, 26, DRT4(6,50) ,DRT4(13,0), DRT4(6,50), 97 , 0) 319 320 DRAM_EOT 321 322#endif 323 324 325END(board_draminfo) 326 327 328/* ********************************************************************* 329 * BOARD_UARTA_TXCHAR 330 * 331 * Transmit a single character via UART A 332 * 333 * Input parameters: 334 * a0 - character to transmit (low-order 8 bits) 335 * 336 * Return value: 337 * nothing 338 * 339 * Registers used: 340 * t0,t1 341 ********************************************************************* */ 342 343#ifdef _SERIAL_PORT_LEDS_ 344LEAF(board_uarta_txchar) 345 346 # Wait until there is space in the transmit buffer 347 3481: li t0,PHYS_TO_K1(A_DUART_STATUS_A) 349 ld t1,(t0) # Get status bits 350 and t1,M_DUART_TX_RDY # test for ready 351 beq t1,0,1b # keep going till ready 352 353 # Okay, now send the character. 354 355 li t0,PHYS_TO_K1(A_DUART_TX_HOLD_A) 356 sd a0,(t0) 357 358 # done! 359 360 j ra 361 362END(board_uarta_txchar) 363#endif 364 365/* ********************************************************************* 366 * BOARD_SETLEDS(x) 367 * 368 * Set LEDs for boot-time progress indication. Not used if 369 * the board does not have progress LEDs. This routine 370 * must not call any other routines, since it may be invoked 371 * either from KSEG0 or KSEG1 and it may be invoked 372 * whether or not the icache is operational. 373 * 374 * Input parameters: 375 * a0 - LED value (8 bits per character, 4 characters) 376 * 377 * Return value: 378 * nothing 379 * 380 * Registers used: 381 * t0,t1,t2,t3 382 ********************************************************************* */ 383 384 385LEAF(board_setleds) 386 387#ifdef _SERIAL_PORT_LEDS_ 388 move t3,ra 389 move t2,a0 390 391 li a0,'[' 392 bal board_uarta_txchar 393 394 move a0,t2 395 rol a0,8 396 bal board_uarta_txchar 397 rol a0,8 398 bal board_uarta_txchar 399 rol a0,8 400 bal board_uarta_txchar 401 rol a0,8 402 bal board_uarta_txchar 403 404 li a0,']' 405 bal board_uarta_txchar 406 407 move ra,t3 408 409#endif 410 411 j ra 412 413END(board_setleds) 414