| /freebsd-10-stable/sys/netpfil/ipfw/ |
| H A D | ip_fw2.c | 227 #define TT ( (1 << ICMP_ECHO) | (1 << ICMP_ROUTERSOLICIT) | \ macro
237 #undef TT macro
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| /freebsd-10-stable/libexec/getty/ |
| H A D | gettytab.h | 68 #define TT gettystrs[8].value macro
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| /freebsd-10-stable/contrib/llvm/lib/ExecutionEngine/ |
| H A D | TargetSelect.cpp | 29 Triple TT; local
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| /freebsd-10-stable/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.cpp | 64 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, argument
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| H A D | MipsTargetMachine.cpp | 56 MipsTargetMachine(const Target &T, StringRef TT, argument
118 MipsebTargetMachine(const Target &T, StringRef TT, argument
127 MipselTargetMachine(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/ |
| H A D | TargetMachine.cpp | 47 TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64Subtarget.cpp | 31 AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS) argument
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| H A D | AArch64TargetMachine.cpp | 29 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 31 AArch64AsmBackend(const Target &T, const StringRef TT) argument
84 ELFAArch64AsmBackend(const Target &T, const StringRef TT, argument
581 createAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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| H A D | AArch64MCTargetDesc.cpp | 39 MCSubtargetInfo *AArch64_MC::createAArch64MCSubtargetInfo(StringRef TT, argument
72 static MCCodeGenInfo *createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
96 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, argument
60 createAArch64MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) argument
|
| /freebsd-10-stable/contrib/llvm/lib/Target/CppBackend/ |
| H A D | CPPTargetMachine.h | 25 CPPTargetMachine(const Target &T, StringRef TT, argument
|
| /freebsd-10-stable/contrib/llvm/lib/Target/CppBackend/TargetInfo/ |
| H A D | CppBackendTargetInfo.cpp | 17 static unsigned CppBackend_TripleMatchQuality(const std::string &TT) { argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 49 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): argument
|
| H A D | HexagonTargetMachine.cpp | 67 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCAsmInfo.cpp | 21 HexagonMCAsmInfo::HexagonMCAsmInfo(StringRef TT) { argument
|
| H A D | HexagonMCTargetDesc.cpp | 43 static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) { argument
49 static MCSubtargetInfo *createHexagonMCSubtargetInfo(StringRef TT, argument
69 static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
57 createHexagonMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsAsmBackend.cpp | 281 createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
289 createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
297 createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
305 createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
|
| H A D | MipsMCAsmInfo.cpp | 21 MipsMCAsmInfo::MipsMCAsmInfo(StringRef TT) { argument
|
| H A D | MipsMCTargetDesc.cpp | 42 static std::string ParseMipsTriple(StringRef TT, StringRef CPU) { argument
80 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) { argument
86 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, argument
100 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { argument
110 createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
131 createMCStreamer(const Target &T, StringRef TT, MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, bool RelaxAll, bool NoExecStack) argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
| H A D | AMDGPUSubtarget.cpp | 24 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : argument
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| H A D | AMDGPUTargetMachine.cpp | 52 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/R600/MCTargetDesc/ |
| H A D | AMDGPUAsmBackend.cpp | 98 createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
|
| H A D | AMDGPUMCAsmInfo.cpp | 14 AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(StringRef &TT) : MCAsmInfo() { argument
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| H A D | AMDGPUMCTargetDesc.cpp | 44 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) { argument
50 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, argument
57 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
85 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcAsmBackend.cpp | 246 createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
|