1234353Sdim//===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===// 2234353Sdim// 3234353Sdim// The LLVM Compiler Infrastructure 4234353Sdim// 5234353Sdim// This file is distributed under the University of Illinois Open Source 6234353Sdim// License. See LICENSE.TXT for details. 7234353Sdim// 8234353Sdim//===----------------------------------------------------------------------===// 9234353Sdim// 10234353Sdim// This file implements the MipsAsmBackend and MipsELFObjectWriter classes. 11234353Sdim// 12234353Sdim//===----------------------------------------------------------------------===// 13234353Sdim// 14234353Sdim 15234353Sdim#include "MipsFixupKinds.h" 16226584Sdim#include "MCTargetDesc/MipsMCTargetDesc.h" 17234353Sdim#include "llvm/MC/MCAsmBackend.h" 18226584Sdim#include "llvm/MC/MCAssembler.h" 19226584Sdim#include "llvm/MC/MCDirectives.h" 20226584Sdim#include "llvm/MC/MCELFObjectWriter.h" 21234353Sdim#include "llvm/MC/MCFixupKindInfo.h" 22226584Sdim#include "llvm/MC/MCObjectWriter.h" 23226584Sdim#include "llvm/MC/MCSubtargetInfo.h" 24226584Sdim#include "llvm/Support/ErrorHandling.h" 25226584Sdim#include "llvm/Support/raw_ostream.h" 26234353Sdim 27226584Sdimusing namespace llvm; 28226584Sdim 29234353Sdim// Prepare value for the target space for it 30234353Sdimstatic unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 31234353Sdim 32234353Sdim // Add/subtract and shift 33234353Sdim switch (Kind) { 34234353Sdim default: 35234353Sdim return 0; 36234353Sdim case FK_GPRel_4: 37234353Sdim case FK_Data_4: 38239462Sdim case FK_Data_8: 39234353Sdim case Mips::fixup_Mips_LO16: 40249423Sdim case Mips::fixup_Mips_GPREL16: 41239462Sdim case Mips::fixup_Mips_GPOFF_HI: 42239462Sdim case Mips::fixup_Mips_GPOFF_LO: 43239462Sdim case Mips::fixup_Mips_GOT_PAGE: 44239462Sdim case Mips::fixup_Mips_GOT_OFST: 45239462Sdim case Mips::fixup_Mips_GOT_DISP: 46244628Sdim case Mips::fixup_Mips_GOT_LO16: 47244628Sdim case Mips::fixup_Mips_CALL_LO16: 48263508Sdim case Mips::fixup_MICROMIPS_LO16: 49263508Sdim case Mips::fixup_MICROMIPS_GOT_PAGE: 50263508Sdim case Mips::fixup_MICROMIPS_GOT_OFST: 51263508Sdim case Mips::fixup_MICROMIPS_GOT_DISP: 52234353Sdim break; 53234353Sdim case Mips::fixup_Mips_PC16: 54234353Sdim // So far we are only using this type for branches. 55234353Sdim // For branches we start 1 instruction after the branch 56234353Sdim // so the displacement will be one instruction size less. 57234353Sdim Value -= 4; 58234353Sdim // The displacement is then divided by 4 to give us an 18 bit 59234353Sdim // address range. 60234353Sdim Value >>= 2; 61234353Sdim break; 62234353Sdim case Mips::fixup_Mips_26: 63234353Sdim // So far we are only using this type for jumps. 64234353Sdim // The displacement is then divided by 4 to give us an 28 bit 65234353Sdim // address range. 66234353Sdim Value >>= 2; 67234353Sdim break; 68234353Sdim case Mips::fixup_Mips_HI16: 69234353Sdim case Mips::fixup_Mips_GOT_Local: 70244628Sdim case Mips::fixup_Mips_GOT_HI16: 71244628Sdim case Mips::fixup_Mips_CALL_HI16: 72263508Sdim case Mips::fixup_MICROMIPS_HI16: 73239462Sdim // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 74234353Sdim Value = ((Value + 0x8000) >> 16) & 0xffff; 75234353Sdim break; 76239462Sdim case Mips::fixup_Mips_HIGHER: 77239462Sdim // Get the 3rd 16-bits. 78239462Sdim Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 79239462Sdim break; 80239462Sdim case Mips::fixup_Mips_HIGHEST: 81239462Sdim // Get the 4th 16-bits. 82239462Sdim Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 83239462Sdim break; 84263508Sdim case Mips::fixup_MICROMIPS_26_S1: 85263508Sdim Value >>= 1; 86263508Sdim break; 87263508Sdim case Mips::fixup_MICROMIPS_PC16_S1: 88263508Sdim Value -= 4; 89263508Sdim Value >>= 1; 90263508Sdim break; 91234353Sdim } 92234353Sdim 93234353Sdim return Value; 94234353Sdim} 95234353Sdim 96226584Sdimnamespace { 97234353Sdimclass MipsAsmBackend : public MCAsmBackend { 98234353Sdim Triple::OSType OSType; 99234353Sdim bool IsLittle; // Big or little endian 100234353Sdim bool Is64Bit; // 32 or 64 bit words 101226584Sdim 102226584Sdimpublic: 103234353Sdim MipsAsmBackend(const Target &T, Triple::OSType _OSType, 104234353Sdim bool _isLittle, bool _is64Bit) 105234353Sdim :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {} 106226584Sdim 107234353Sdim MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 108239462Sdim return createMipsELFObjectWriter(OS, 109239462Sdim MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 110226584Sdim } 111226584Sdim 112243830Sdim /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 113226584Sdim /// data fragment, at the offset specified by the fixup and following the 114226584Sdim /// fixup kind as appropriate. 115234353Sdim void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 116226584Sdim uint64_t Value) const { 117234353Sdim MCFixupKind Kind = Fixup.getKind(); 118234353Sdim Value = adjustFixupValue((unsigned)Kind, Value); 119234353Sdim 120234982Sdim if (!Value) 121234353Sdim return; // Doesn't change encoding. 122234353Sdim 123234353Sdim // Where do we start in the object 124234353Sdim unsigned Offset = Fixup.getOffset(); 125234353Sdim // Number of bytes we need to fixup 126234353Sdim unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 127234353Sdim // Used to point to big endian bytes 128234353Sdim unsigned FullSize; 129234353Sdim 130234353Sdim switch ((unsigned)Kind) { 131234353Sdim case Mips::fixup_Mips_16: 132234353Sdim FullSize = 2; 133234353Sdim break; 134234353Sdim case Mips::fixup_Mips_64: 135234353Sdim FullSize = 8; 136234353Sdim break; 137234353Sdim default: 138234353Sdim FullSize = 4; 139234353Sdim break; 140234353Sdim } 141234353Sdim 142234353Sdim // Grab current value, if any, from bits. 143234353Sdim uint64_t CurVal = 0; 144234353Sdim 145234353Sdim for (unsigned i = 0; i != NumBytes; ++i) { 146234353Sdim unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 147234353Sdim CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 148234353Sdim } 149234353Sdim 150239462Sdim uint64_t Mask = ((uint64_t)(-1) >> 151239462Sdim (64 - getFixupKindInfo(Kind).TargetSize)); 152234982Sdim CurVal |= Value & Mask; 153234353Sdim 154234353Sdim // Write out the fixed up bytes back to the code/data bits. 155234353Sdim for (unsigned i = 0; i != NumBytes; ++i) { 156234353Sdim unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 157234353Sdim Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 158234353Sdim } 159226584Sdim } 160226584Sdim 161234353Sdim unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; } 162234353Sdim 163234353Sdim const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 164234353Sdim const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { 165234353Sdim // This table *must* be in same the order of fixup_* kinds in 166234353Sdim // MipsFixupKinds.h. 167234353Sdim // 168234353Sdim // name offset bits flags 169234353Sdim { "fixup_Mips_16", 0, 16, 0 }, 170234353Sdim { "fixup_Mips_32", 0, 32, 0 }, 171234353Sdim { "fixup_Mips_REL32", 0, 32, 0 }, 172234353Sdim { "fixup_Mips_26", 0, 26, 0 }, 173234353Sdim { "fixup_Mips_HI16", 0, 16, 0 }, 174234353Sdim { "fixup_Mips_LO16", 0, 16, 0 }, 175234353Sdim { "fixup_Mips_GPREL16", 0, 16, 0 }, 176234353Sdim { "fixup_Mips_LITERAL", 0, 16, 0 }, 177234353Sdim { "fixup_Mips_GOT_Global", 0, 16, 0 }, 178234353Sdim { "fixup_Mips_GOT_Local", 0, 16, 0 }, 179234353Sdim { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 180234353Sdim { "fixup_Mips_CALL16", 0, 16, 0 }, 181234353Sdim { "fixup_Mips_GPREL32", 0, 32, 0 }, 182234353Sdim { "fixup_Mips_SHIFT5", 6, 5, 0 }, 183234353Sdim { "fixup_Mips_SHIFT6", 6, 5, 0 }, 184234353Sdim { "fixup_Mips_64", 0, 64, 0 }, 185234353Sdim { "fixup_Mips_TLSGD", 0, 16, 0 }, 186234353Sdim { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 187234353Sdim { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 188234353Sdim { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 189234353Sdim { "fixup_Mips_TLSLDM", 0, 16, 0 }, 190234353Sdim { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 191234353Sdim { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 192239462Sdim { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 193239462Sdim { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 194239462Sdim { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 195239462Sdim { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 196239462Sdim { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 197239462Sdim { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 198239462Sdim { "fixup_Mips_HIGHER", 0, 16, 0 }, 199244628Sdim { "fixup_Mips_HIGHEST", 0, 16, 0 }, 200244628Sdim { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 201244628Sdim { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 202244628Sdim { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 203263508Sdim { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 204263508Sdim { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 205263508Sdim { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 206263508Sdim { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 207263508Sdim { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 208263508Sdim { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 209263508Sdim { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 210263508Sdim { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 211263508Sdim { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 212263508Sdim { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 213263508Sdim { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 214263508Sdim { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 215263508Sdim { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 216263508Sdim { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 } 217234353Sdim }; 218234353Sdim 219234353Sdim if (Kind < FirstTargetFixupKind) 220234353Sdim return MCAsmBackend::getFixupKindInfo(Kind); 221234353Sdim 222234353Sdim assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 223234353Sdim "Invalid kind!"); 224234353Sdim return Infos[Kind - FirstTargetFixupKind]; 225234353Sdim } 226234353Sdim 227226584Sdim /// @name Target Relaxation Interfaces 228226584Sdim /// @{ 229226584Sdim 230226584Sdim /// MayNeedRelaxation - Check whether the given instruction may need 231226584Sdim /// relaxation. 232226584Sdim /// 233226584Sdim /// \param Inst - The instruction to test. 234234353Sdim bool mayNeedRelaxation(const MCInst &Inst) const { 235226584Sdim return false; 236226584Sdim } 237226584Sdim 238234353Sdim /// fixupNeedsRelaxation - Target specific predicate for whether a given 239234353Sdim /// fixup requires the associated instruction to be relaxed. 240234353Sdim bool fixupNeedsRelaxation(const MCFixup &Fixup, 241234353Sdim uint64_t Value, 242249423Sdim const MCRelaxableFragment *DF, 243234353Sdim const MCAsmLayout &Layout) const { 244234353Sdim // FIXME. 245234353Sdim assert(0 && "RelaxInstruction() unimplemented"); 246234353Sdim return false; 247234353Sdim } 248234353Sdim 249234353Sdim /// RelaxInstruction - Relax the instruction in the given fragment 250234353Sdim /// to the next wider instruction. 251226584Sdim /// 252234353Sdim /// \param Inst - The instruction to relax, which may be the same 253234353Sdim /// as the output. 254243830Sdim /// \param [out] Res On return, the relaxed instruction. 255234353Sdim void relaxInstruction(const MCInst &Inst, MCInst &Res) const { 256226584Sdim } 257234353Sdim 258226584Sdim /// @} 259226584Sdim 260234353Sdim /// WriteNopData - Write an (optimal) nop sequence of Count bytes 261234353Sdim /// to the given output. If the target cannot generate such a sequence, 262234353Sdim /// it should return an error. 263226584Sdim /// 264226584Sdim /// \return - True on success. 265234353Sdim bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { 266239462Sdim // Check for a less than instruction size number of bytes 267239462Sdim // FIXME: 16 bit instructions are not handled yet here. 268239462Sdim // We shouldn't be using a hard coded number for instruction size. 269239462Sdim if (Count % 4) return false; 270239462Sdim 271239462Sdim uint64_t NumNops = Count / 4; 272239462Sdim for (uint64_t i = 0; i != NumNops; ++i) 273239462Sdim OW->Write32(0); 274234353Sdim return true; 275226584Sdim } 276234353Sdim}; // class MipsAsmBackend 277226584Sdim 278234353Sdim} // namespace 279226584Sdim 280234353Sdim// MCAsmBackend 281263508SdimMCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 282263508Sdim const MCRegisterInfo &MRI, 283263508Sdim StringRef TT, 284241430Sdim StringRef CPU) { 285234353Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 286234353Sdim /*IsLittle*/true, /*Is64Bit*/false); 287234353Sdim} 288226584Sdim 289263508SdimMCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 290263508Sdim const MCRegisterInfo &MRI, 291263508Sdim StringRef TT, 292241430Sdim StringRef CPU) { 293234353Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 294234353Sdim /*IsLittle*/false, /*Is64Bit*/false); 295234353Sdim} 296226584Sdim 297263508SdimMCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 298263508Sdim const MCRegisterInfo &MRI, 299263508Sdim StringRef TT, 300241430Sdim StringRef CPU) { 301234353Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 302234353Sdim /*IsLittle*/true, /*Is64Bit*/true); 303234353Sdim} 304226584Sdim 305263508SdimMCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 306263508Sdim const MCRegisterInfo &MRI, 307263508Sdim StringRef TT, 308241430Sdim StringRef CPU) { 309234353Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 310234353Sdim /*IsLittle*/false, /*Is64Bit*/true); 311226584Sdim} 312226584Sdim 313