1249259Sdim//===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief Implements the AMDGPU specific subclass of TargetSubtarget. 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim#include "AMDGPUSubtarget.h" 16249259Sdim 17249259Sdimusing namespace llvm; 18249259Sdim 19249259Sdim#define GET_SUBTARGETINFO_ENUM 20249259Sdim#define GET_SUBTARGETINFO_TARGET_DESC 21249259Sdim#define GET_SUBTARGETINFO_CTOR 22249259Sdim#include "AMDGPUGenSubtargetInfo.inc" 23249259Sdim 24249259SdimAMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : 25249259Sdim AMDGPUGenSubtargetInfo(TT, CPU, FS), DumpCode(false) { 26249259Sdim InstrItins = getInstrItineraryForCPU(CPU); 27249259Sdim 28249259Sdim // Default card 29249259Sdim StringRef GPU = CPU; 30249259Sdim Is64bit = false; 31249259Sdim DefaultSize[0] = 64; 32249259Sdim DefaultSize[1] = 1; 33249259Sdim DefaultSize[2] = 1; 34251662Sdim HasVertexCache = false; 35263508Sdim TexVTXClauseSize = 0; 36263508Sdim Gen = AMDGPUSubtarget::R600; 37263508Sdim FP64 = false; 38263508Sdim CaymanISA = false; 39263508Sdim EnableIRStructurizer = true; 40263508Sdim EnableIfCvt = true; 41249259Sdim ParseSubtargetFeatures(GPU, FS); 42249259Sdim DevName = GPU; 43249259Sdim} 44249259Sdim 45249259Sdimbool 46249259SdimAMDGPUSubtarget::is64bit() const { 47249259Sdim return Is64bit; 48249259Sdim} 49249259Sdimbool 50251662SdimAMDGPUSubtarget::hasVertexCache() const { 51251662Sdim return HasVertexCache; 52251662Sdim} 53263508Sdimshort 54263508SdimAMDGPUSubtarget::getTexVTXClauseSize() const { 55263508Sdim return TexVTXClauseSize; 56263508Sdim} 57263508Sdimenum AMDGPUSubtarget::Generation 58263508SdimAMDGPUSubtarget::getGeneration() const { 59263508Sdim return Gen; 60263508Sdim} 61251662Sdimbool 62263508SdimAMDGPUSubtarget::hasHWFP64() const { 63263508Sdim return FP64; 64263508Sdim} 65263508Sdimbool 66263508SdimAMDGPUSubtarget::hasCaymanISA() const { 67263508Sdim return CaymanISA; 68263508Sdim} 69263508Sdimbool 70263508SdimAMDGPUSubtarget::IsIRStructurizerEnabled() const { 71263508Sdim return EnableIRStructurizer; 72263508Sdim} 73263508Sdimbool 74263508SdimAMDGPUSubtarget::isIfCvtEnabled() const { 75263508Sdim return EnableIfCvt; 76263508Sdim} 77263508Sdimbool 78249259SdimAMDGPUSubtarget::isTargetELF() const { 79249259Sdim return false; 80249259Sdim} 81249259Sdimsize_t 82249259SdimAMDGPUSubtarget::getDefaultSize(uint32_t dim) const { 83249259Sdim if (dim > 3) { 84249259Sdim return 1; 85249259Sdim } else { 86249259Sdim return DefaultSize[dim]; 87249259Sdim } 88249259Sdim} 89249259Sdim 90249259Sdimstd::string 91249259SdimAMDGPUSubtarget::getDataLayout() const { 92263508Sdim std::string DataLayout = std::string( 93263508Sdim "e" 94263508Sdim "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" 95263508Sdim "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 96263508Sdim "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 97263508Sdim "-n32:64" 98263508Sdim ); 99263508Sdim 100263508Sdim if (hasHWFP64()) { 101263508Sdim DataLayout.append("-f64:64:64"); 102263508Sdim } 103263508Sdim 104263508Sdim if (is64bit()) { 105263508Sdim DataLayout.append("-p:64:64:64"); 106263508Sdim } else { 107263508Sdim DataLayout.append("-p:32:32:32"); 108263508Sdim } 109263508Sdim 110263508Sdim if (Gen >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { 111263508Sdim DataLayout.append("-p3:32:32:32"); 112263508Sdim } 113263508Sdim 114263508Sdim return DataLayout; 115249259Sdim} 116249259Sdim 117249259Sdimstd::string 118249259SdimAMDGPUSubtarget::getDeviceName() const { 119249259Sdim return DevName; 120249259Sdim} 121