| /freebsd-10-stable/contrib/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 42 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, argument
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| /freebsd-10-stable/contrib/llvm/lib/Support/ |
| H A D | TargetRegistry.cpp | 67 const Target *TargetRegistry::lookupTarget(const std::string &TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetMachine.cpp | 67 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCTargetDesc.cpp | 40 static MCRegisterInfo *createMSP430MCRegisterInfo(StringRef TT) { argument
46 static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, argument
53 static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.cpp | 64 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, argument
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| H A D | MipsTargetMachine.cpp | 56 MipsTargetMachine(const Target &T, StringRef TT, argument
118 MipsebTargetMachine(const Target &T, StringRef TT, argument
127 MipselTargetMachine(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXMCTargetDesc.cpp | 40 static MCRegisterInfo *createNVPTXMCRegisterInfo(StringRef TT) { argument
48 createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { argument
54 createNVPTXMCCodeGenInfo( StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
| H A D | AMDGPUSubtarget.cpp | 24 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : argument
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| H A D | AMDGPUTargetMachine.cpp | 52 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcTargetMachine.cpp | 28 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, argument
85 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
97 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCAsmBackend.cpp | 121 createSystemZMCAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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| H A D | SystemZMCTargetDesc.cpp | 113 static MCRegisterInfo *createSystemZMCRegisterInfo(StringRef TT) { argument
119 static MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, argument
127 static MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
183 static MCStreamer *createSystemZMCObjectStreamer(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetMachine.cpp | 22 SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/XCore/MCTargetDesc/ |
| H A D | XCoreMCTargetDesc.cpp | 41 static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) { argument
47 static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, argument
65 static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
54 createXCoreMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.cpp | 77 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, argument
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| H A D | ARMTargetMachine.cpp | 45 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, argument
70 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, argument
96 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsAsmBackend.cpp | 281 createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
289 createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
297 createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
305 createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 66 NVPTXTargetMachine( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
80 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
88 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCAsmBackend.cpp | 198 createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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| H A D | PPCMCCodeEmitter.cpp | 38 Triple TT; member in class:__anon2559::PPCMCCodeEmitter
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| /freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.cpp | 33 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, argument
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| H A D | PPCTargetMachine.cpp | 73 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, argument
94 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, argument
104 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/R600/MCTargetDesc/ |
| H A D | AMDGPUAsmBackend.cpp | 98 createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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| H A D | AMDGPUMCTargetDesc.cpp | 44 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) { argument
50 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, argument
57 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
85 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcAsmBackend.cpp | 246 createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
|