| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 740 const uint32_t *Mask = local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1147 SDValue Mask; local
1293 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); local
|
| H A D | AMDGPUISelDAGToDAG.cpp | 1961 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1)); local
1983 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1)); local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 313 SDValue Mask = DAG.getConstant(32/ElemWidth - 1, dl, MVT::i32); local
453 SmallVector<int,128> Mask; local
319 getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1, ArrayRef<int> Mask, SelectionDAG &DAG) const argument
826 SmallVector<int,128> Mask; local
[all...] |
| H A D | HexagonHardwareLoops.cpp | 655 int Mask = 0, ImmValue = 0; local
|
| H A D | HexagonLoopIdiomRecognition.cpp | 1039 Value *Mask = ConstantInt::get(DestTy, (1u << TruncTy->getBitWidth()) - 1); local
|
| H A D | HexagonConstPropagation.cpp | 1593 APInt Mask = APInt::getLowBitsSet(Width, Bits); local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 242 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 1324 Constant *Mask = local
2404 auto *Mask = Operands[2]; local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AtomicExpandPass.cpp | 617 Value *Mask; member in struct:__anon1692::PartwordMaskValues
[all...] |
| H A D | LiveIntervals.cpp | 1529 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); local
|
| H A D | MachineVerifier.cpp | 2103 const uint32_t *Mask = regMasks.pop_back_val(); local
2706 LaneBitmask Mask; local
|
| H A D | RegisterCoalescer.cpp | 948 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntA.reg); local
951 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntB.reg); local
1656 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); local
3376 LaneBitmask Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask() local
3384 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask); local
3394 LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask() local
3400 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 240 SDValue Mask = DAG.getConstant(API, SDLoc(N), NVT); local
327 SDValue Mask = DAG.getNode( local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 1566 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) { argument
1577 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize, argument
516 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
[all...] |
| H A D | SystemZISelDAGToDAG.cpp | 127 uint64_t Mask; member in struct:__anon2408::RxSBGOperands
765 maskMatters(RxSBGOperands &RxSBG, uint64_t Mask) argument
780 uint64_t Mask = allOnes(BitSize); local
795 uint64_t Mask = MaskNode->getZExtValue(); local
818 uint64_t Mask = ~MaskNode->getZExtValue(); local
1007 SDValue Mask = CurDAG->getConstant(RISBG.Mask, DL, VT); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1474 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op.getNode())->getMask(); local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1658 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), local
1680 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), local
1695 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 1941 SmallVector<Constant *, 16> Mask; local
|
| H A D | InstCombineVectorOps.cpp | 445 collectSingleShuffleElements(Value *V, Value *LHS, Value *RHS, SmallVectorImpl<Constant*> &Mask) argument
606 collectShuffleElements(Value *V, SmallVectorImpl<Constant *> &Mask, Value *PermittedRHS, InstCombiner &IC) argument
1082 SmallVector<Constant*, 16> Mask; local
1126 canEvaluateShuffled(Value *V, ArrayRef<int> Mask, unsigned Depth = 5) argument
1289 evaluateInDifferentElementOrder(Value *V, ArrayRef<int> Mask) argument
1399 isShuffleExtractingFromLHS(ShuffleVectorInst &SVI, SmallVector<int, 16> &Mask) argument
1514 Constant *Mask = Shuf.getMask(); local
1608 Constant *Mask = Shuf.getMask(); local
1711 Constant *Mask; local
1748 SmallVector<int, 16> Mask = Shuf.getShuffleMask(); local
1871 SmallVector<int, 16> Mask = Shuf.getShuffleMask(); local
1911 SmallVector<int, 16> Mask = SVI.getShuffleMask(); local
[all...] |
| H A D | InstCombineAddSub.cpp | 1247 APInt Mask = APInt::getHighBitsSet(TySizeBits, ExtendAmt); local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1526 LaneBitmask Mask = Idx.computeLaneMask(); local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 2301 SmallVector<int, 64> Mask; local
2373 SmallVector<int, 16> Mask; local
1758 getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef<int> Mask) argument
2404 SmallVector<int, 16> Mask; local
2421 SmallVector<int, 16> Mask; local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/clang/lib/Frontend/ |
| H A D | CompilerInvocation.cpp | 611 auto Mask = parseXRayInstrValue(B); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2249 isShiftedMask(uint64_t Mask, EVT VT) argument
[all...] |