Configure Tx interrupt mitigation thresholds on athn(4) devices.
ok kevlo@ mpi@

Add athn(4) definitions for the block-ack/block-ack-request control register.

Not used yet but may become useful later.

For AR9271, use correct clock control register and add a macro to access it.

ok stsp@

Complete athn(4) noisefloor calibration code and enable it.
Update default/min/max noisefloor values to those used by Linux ath9k.
Tested by jmc, juanfra, kn, and myself, on 9280 and 9271 devices.

The athn(4) PCI driver forgot about adding the default noisefloor to
measured RSSI values. The same is already done for USB devices.
RSSI values shown in ifconfig make sense now.

ok kevlo@

Make monitor work with athn(4) on my 3T3R AR9380 device.
This card can now receive packets. Transmit is still broken and
Kevin Lo reports that his 2T2R AR9380 device cannot receive yet.

Add cast to mask and shift macros to silence warnings generated by clang.

ok millert@

Allow a variable number of words for the Serializer/Deserializer programming.
Probably not enought to make the AR9380 chips to work, but at least the kernel
shouldn't crash anymore when we see one.

ok stsp@

"athn* at uhub? port ?"
this adds preliminary support for the Atheros AR9271 chipset and
probably the AR9280+AR7010 and AR9287+AR7010 too though those were
not tested.
scanning still takes a very long time (~1 sec per channel) but
otherwise, operation in STA mode seems stable.
will implement fast channel change soon.

committed over the Ubiquiti WifiStation EXT (AR9271) on i386 with WPA.
requires firmware (see man page for details)

ok deraadt@ (who checked the .h files)

unbreak kernel builds; sorry guys.

pointed out by Benoit Lecocq.

commit some bits that will be required by AR9271/AR7010

Make the athn(4) back-end more bus agnostic by moving read and write
operations to callbacks in the PCI and CardBus front-ends.
This will allow support of other buses like USB.
Assume the following memory model:
- writes are ordered but may be buffered and require explicit flush
- a read always flushes all buffered writes

Implement PA linearization on adapters with digital predistorters
(AR9003 family only).

The power amplifier predistortion state machine works as follows:
1) Disable digital predistorters for all Tx chains
2) Repeat steps 3~7 for all Tx chains
3) Force Tx gain to that of training signal
4) Send training signal (asynchronous)
5) Wait for training signal to complete (asynchronous)
6) Read PA measurements (input power, output power, output phase)
7) Compute the predistortion function that linearizes PA output
8) Write predistortion functions to hardware tables for all Tx chains
9) Enable digital predistorters for all Tx chains

from ath9k (though implementation differs a lot)

enable async fifo for >=AR9287 1.3 only.
from ath9k.

initial Host AP bits.

fix athn_updateslot for fast PLL clock and 40MHz CBW

initialization values for AR9380 2.2.
turns out the Rx gain tables are the same as 2.0 (and the Tx gain
registers too), which saves us a few bytes.

athn(4) is going to support a new family of Atheros 802.11n
chips (AR9003), which differs from the currently supported
families (AR5008, AR9001 and AR9002).

The main differences (from a driver point of view) are:

* DMA:
Tx and Rx descriptors have changed.
A single Tx descriptor can now reference up to 4 scatter/gather
DMA segments.
There is now a DMA ring for reporting Tx status with separate
Tx status descriptors (this ring is used to report Tx status for
all the Tx FIFOs).
Rx status descriptors are now put at the beginning of Rx buffers
and do not need to be allocated separately from buffers.
There are two Rx FIFOs (low priority and high priority) instead
of one.

* ROM:
The AR9003 family uses OTP-ROM instead of EEPROM.
Reading the ROM is totally insane since vendors can provide only
the chunks of ROM that differ from a default image (and thus the
default image has to be stored in the driver).
This is referenced as "compressed ROM" in the Linux driver, though
there is no real compression involved, at least for the moment.

* PHY registers:
All PHY registers have changed.
Some registers offsets do not fit on 16 bits anymore, but
since they are 32-bit aligned, we can still make them fit on
16 bits to save .rodata space in initialization tables.

* MAC registers:
Some MAC registers offsets have changed (GPIO, interrupt masks)
which is quite annoying (though ~98% remain the same.)

* Initialization values:
Initialization values are now split in mac/soc/bb/radio blocks
and pre/core/post phases in the Linux driver. I have chosen to
not go that road and merge these blocks in modal and non-modal
initialization values (similar to the other families).
The initialization order remains exactly the same as the Linux
driver though.

To manage these differences, I have split athn.c in two backends:
ar5008.c contains the bits that are specific to the AR5008,
AR9001 and AR9002 families (used by ar5416.c, ar9280.c,
ar9285.c and ar9287.c) and that were previously in athn.c.

ar9003.c contains the bits that are specific to the new
AR9003 family (used by ar9380.c only for now.)

I have introduced a thin hardware abstraction layer (actually
a set of pointers to functions) that is used in athn.c.
My intent is to keep this abstraction layer as thin as possible
and not to create another ugly pile of abstraction layers a la
MadWifi.

I think I've managed to keep things sane, probably at the expense
of duplicating some code in both ar5008.c and ar9003.c, but at
least we do not have to dig through layers and layers of virtual
descriptors to figure out what is mapped to the hardware.

Tested for non-regression on various AR5416 (sparc64+i386), AR9281
and AR9285 (i386 only) adapters.
AR9380 part is not tested (hardware is not available to the general
public yet).

Committed over my AR9285 2.0.

update initvals and TX gains for AR9285 >=1.2
check result of carrier leakage calibration and redo calibration if needed
add support for newer AR9285 chips (AR9285 XE 2.0).

tested for non-regression on a DNXA-95
"Still seems to work here" kettenis@

Disable Reduced Interframe Space search on AR9160 to workaround
baseband issues.
It would be cleaner to modify directly the initvals for AR9160 but
I want to keep the exact same initvals as the Linux ath9k driver.

from ath9k

fix AR_PHY_TX_DESIRED_SCALE_CCK mask (only affect AR9280 2.0
with ROM rev >= 20)
do some cleanup of phy registers definitions while i'm here.

if a radio switch exists, configure the GPIO pin to which it is
connected to raise an interrupt when the pin goes low (or high
depending on the polarity of the radio switch.)
turn the interface down when the interrupt occurs.
this is the same behaviour as in wpi(4) and iwn(4).

cleanup interrupts processing while i'm here.
remove ATHN_INTR_MITIGATION compile option (it is set by default.)

AR9287 uses GPIO pin 8 for LED, not 1.
Turn link LED on while associated.

translate a comment from french to english.
no binary change.

athn(4), a driver for Atheros 802.11a/g/n devices.
written from scratch based on the vendor driver for Linux (ath9k).
AR9285 and AR9287 parts are 100% untested.
only basic functionnalities are enabled for now.

committed over an AR9281.

"commit" deraadt

Add athn(4) definitions for the block-ack/block-ack-request control register.

Not used yet but may become useful later.

For AR9271, use correct clock control register and add a macro to access it.

ok stsp@

Complete athn(4) noisefloor calibration code and enable it.
Update default/min/max noisefloor values to those used by Linux ath9k.
Tested by jmc, juanfra, kn, and myself, on 9280 and 9271 devices.

The athn(4) PCI driver forgot about adding the default noisefloor to
measured RSSI values. The same is already done for USB devices.
RSSI values shown in ifconfig make sense now.

ok kevlo@

Make monitor work with athn(4) on my 3T3R AR9380 device.
This card can now receive packets. Transmit is still broken and
Kevin Lo reports that his 2T2R AR9380 device cannot receive yet.

Add cast to mask and shift macros to silence warnings generated by clang.

ok millert@

Allow a variable number of words for the Serializer/Deserializer programming.
Probably not enought to make the AR9380 chips to work, but at least the kernel
shouldn't crash anymore when we see one.

ok stsp@

"athn* at uhub? port ?"
this adds preliminary support for the Atheros AR9271 chipset and
probably the AR9280+AR7010 and AR9287+AR7010 too though those were
not tested.
scanning still takes a very long time (~1 sec per channel) but
otherwise, operation in STA mode seems stable.
will implement fast channel change soon.

committed over the Ubiquiti WifiStation EXT (AR9271) on i386 with WPA.
requires firmware (see man page for details)

ok deraadt@ (who checked the .h files)

unbreak kernel builds; sorry guys.

pointed out by Benoit Lecocq.

commit some bits that will be required by AR9271/AR7010

Make the athn(4) back-end more bus agnostic by moving read and write
operations to callbacks in the PCI and CardBus front-ends.
This will allow support of other buses like USB.
Assume the following memory model:
- writes are ordered but may be buffered and require explicit flush
- a read always flushes all buffered writes

Implement PA linearization on adapters with digital predistorters
(AR9003 family only).

The power amplifier predistortion state machine works as follows:
1) Disable digital predistorters for all Tx chains
2) Repeat steps 3~7 for all Tx chains
3) Force Tx gain to that of training signal
4) Send training signal (asynchronous)
5) Wait for training signal to complete (asynchronous)
6) Read PA measurements (input power, output power, output phase)
7) Compute the predistortion function that linearizes PA output
8) Write predistortion functions to hardware tables for all Tx chains
9) Enable digital predistorters for all Tx chains

from ath9k (though implementation differs a lot)

enable async fifo for >=AR9287 1.3 only.
from ath9k.

initial Host AP bits.

fix athn_updateslot for fast PLL clock and 40MHz CBW

initialization values for AR9380 2.2.
turns out the Rx gain tables are the same as 2.0 (and the Tx gain
registers too), which saves us a few bytes.

athn(4) is going to support a new family of Atheros 802.11n
chips (AR9003), which differs from the currently supported
families (AR5008, AR9001 and AR9002).

The main differences (from a driver point of view) are:

* DMA:
Tx and Rx descriptors have changed.
A single Tx descriptor can now reference up to 4 scatter/gather
DMA segments.
There is now a DMA ring for reporting Tx status with separate
Tx status descriptors (this ring is used to report Tx status for
all the Tx FIFOs).
Rx status descriptors are now put at the beginning of Rx buffers
and do not need to be allocated separately from buffers.
There are two Rx FIFOs (low priority and high priority) instead
of one.

* ROM:
The AR9003 family uses OTP-ROM instead of EEPROM.
Reading the ROM is totally insane since vendors can provide only
the chunks of ROM that differ from a default image (and thus the
default image has to be stored in the driver).
This is referenced as "compressed ROM" in the Linux driver, though
there is no real compression involved, at least for the moment.

* PHY registers:
All PHY registers have changed.
Some registers offsets do not fit on 16 bits anymore, but
since they are 32-bit aligned, we can still make them fit on
16 bits to save .rodata space in initialization tables.

* MAC registers:
Some MAC registers offsets have changed (GPIO, interrupt masks)
which is quite annoying (though ~98% remain the same.)

* Initialization values:
Initialization values are now split in mac/soc/bb/radio blocks
and pre/core/post phases in the Linux driver. I have chosen to
not go that road and merge these blocks in modal and non-modal
initialization values (similar to the other families).
The initialization order remains exactly the same as the Linux
driver though.

To manage these differences, I have split athn.c in two backends:
ar5008.c contains the bits that are specific to the AR5008,
AR9001 and AR9002 families (used by ar5416.c, ar9280.c,
ar9285.c and ar9287.c) and that were previously in athn.c.

ar9003.c contains the bits that are specific to the new
AR9003 family (used by ar9380.c only for now.)

I have introduced a thin hardware abstraction layer (actually
a set of pointers to functions) that is used in athn.c.
My intent is to keep this abstraction layer as thin as possible
and not to create another ugly pile of abstraction layers a la
MadWifi.

I think I've managed to keep things sane, probably at the expense
of duplicating some code in both ar5008.c and ar9003.c, but at
least we do not have to dig through layers and layers of virtual
descriptors to figure out what is mapped to the hardware.

Tested for non-regression on various AR5416 (sparc64+i386), AR9281
and AR9285 (i386 only) adapters.
AR9380 part is not tested (hardware is not available to the general
public yet).

Committed over my AR9285 2.0.

update initvals and TX gains for AR9285 >=1.2
check result of carrier leakage calibration and redo calibration if needed
add support for newer AR9285 chips (AR9285 XE 2.0).

tested for non-regression on a DNXA-95
"Still seems to work here" kettenis@

Disable Reduced Interframe Space search on AR9160 to workaround
baseband issues.
It would be cleaner to modify directly the initvals for AR9160 but
I want to keep the exact same initvals as the Linux ath9k driver.

from ath9k

fix AR_PHY_TX_DESIRED_SCALE_CCK mask (only affect AR9280 2.0
with ROM rev >= 20)
do some cleanup of phy registers definitions while i'm here.

if a radio switch exists, configure the GPIO pin to which it is
connected to raise an interrupt when the pin goes low (or high
depending on the polarity of the radio switch.)
turn the interface down when the interrupt occurs.
this is the same behaviour as in wpi(4) and iwn(4).

cleanup interrupts processing while i'm here.
remove ATHN_INTR_MITIGATION compile option (it is set by default.)

AR9287 uses GPIO pin 8 for LED, not 1.
Turn link LED on while associated.

translate a comment from french to english.
no binary change.

athn(4), a driver for Atheros 802.11a/g/n devices.
written from scratch based on the vendor driver for Linux (ath9k).
AR9285 and AR9287 parts are 100% untested.
only basic functionnalities are enabled for now.

committed over an AR9281.

"commit" deraadt

For AR9271, use correct clock control register and add a macro to access it.

ok stsp@

Complete athn(4) noisefloor calibration code and enable it.
Update default/min/max noisefloor values to those used by Linux ath9k.
Tested by jmc, juanfra, kn, and myself, on 9280 and 9271 devices.

The athn(4) PCI driver forgot about adding the default noisefloor to
measured RSSI values. The same is already done for USB devices.
RSSI values shown in ifconfig make sense now.

ok kevlo@

Make monitor work with athn(4) on my 3T3R AR9380 device.
This card can now receive packets. Transmit is still broken and
Kevin Lo reports that his 2T2R AR9380 device cannot receive yet.

Add cast to mask and shift macros to silence warnings generated by clang.

ok millert@

Allow a variable number of words for the Serializer/Deserializer programming.
Probably not enought to make the AR9380 chips to work, but at least the kernel
shouldn't crash anymore when we see one.

ok stsp@

"athn* at uhub? port ?"
this adds preliminary support for the Atheros AR9271 chipset and
probably the AR9280+AR7010 and AR9287+AR7010 too though those were
not tested.
scanning still takes a very long time (~1 sec per channel) but
otherwise, operation in STA mode seems stable.
will implement fast channel change soon.

committed over the Ubiquiti WifiStation EXT (AR9271) on i386 with WPA.
requires firmware (see man page for details)

ok deraadt@ (who checked the .h files)

unbreak kernel builds; sorry guys.

pointed out by Benoit Lecocq.

commit some bits that will be required by AR9271/AR7010

Make the athn(4) back-end more bus agnostic by moving read and write
operations to callbacks in the PCI and CardBus front-ends.
This will allow support of other buses like USB.
Assume the following memory model:
- writes are ordered but may be buffered and require explicit flush
- a read always flushes all buffered writes

Implement PA linearization on adapters with digital predistorters
(AR9003 family only).

The power amplifier predistortion state machine works as follows:
1) Disable digital predistorters for all Tx chains
2) Repeat steps 3~7 for all Tx chains
3) Force Tx gain to that of training signal
4) Send training signal (asynchronous)
5) Wait for training signal to complete (asynchronous)
6) Read PA measurements (input power, output power, output phase)
7) Compute the predistortion function that linearizes PA output
8) Write predistortion functions to hardware tables for all Tx chains
9) Enable digital predistorters for all Tx chains

from ath9k (though implementation differs a lot)

enable async fifo for >=AR9287 1.3 only.
from ath9k.

initial Host AP bits.

fix athn_updateslot for fast PLL clock and 40MHz CBW

initialization values for AR9380 2.2.
turns out the Rx gain tables are the same as 2.0 (and the Tx gain
registers too), which saves us a few bytes.

athn(4) is going to support a new family of Atheros 802.11n
chips (AR9003), which differs from the currently supported
families (AR5008, AR9001 and AR9002).

The main differences (from a driver point of view) are:

* DMA:
Tx and Rx descriptors have changed.
A single Tx descriptor can now reference up to 4 scatter/gather
DMA segments.
There is now a DMA ring for reporting Tx status with separate
Tx status descriptors (this ring is used to report Tx status for
all the Tx FIFOs).
Rx status descriptors are now put at the beginning of Rx buffers
and do not need to be allocated separately from buffers.
There are two Rx FIFOs (low priority and high priority) instead
of one.

* ROM:
The AR9003 family uses OTP-ROM instead of EEPROM.
Reading the ROM is totally insane since vendors can provide only
the chunks of ROM that differ from a default image (and thus the
default image has to be stored in the driver).
This is referenced as "compressed ROM" in the Linux driver, though
there is no real compression involved, at least for the moment.

* PHY registers:
All PHY registers have changed.
Some registers offsets do not fit on 16 bits anymore, but
since they are 32-bit aligned, we can still make them fit on
16 bits to save .rodata space in initialization tables.

* MAC registers:
Some MAC registers offsets have changed (GPIO, interrupt masks)
which is quite annoying (though ~98% remain the same.)

* Initialization values:
Initialization values are now split in mac/soc/bb/radio blocks
and pre/core/post phases in the Linux driver. I have chosen to
not go that road and merge these blocks in modal and non-modal
initialization values (similar to the other families).
The initialization order remains exactly the same as the Linux
driver though.

To manage these differences, I have split athn.c in two backends:
ar5008.c contains the bits that are specific to the AR5008,
AR9001 and AR9002 families (used by ar5416.c, ar9280.c,
ar9285.c and ar9287.c) and that were previously in athn.c.

ar9003.c contains the bits that are specific to the new
AR9003 family (used by ar9380.c only for now.)

I have introduced a thin hardware abstraction layer (actually
a set of pointers to functions) that is used in athn.c.
My intent is to keep this abstraction layer as thin as possible
and not to create another ugly pile of abstraction layers a la
MadWifi.

I think I've managed to keep things sane, probably at the expense
of duplicating some code in both ar5008.c and ar9003.c, but at
least we do not have to dig through layers and layers of virtual
descriptors to figure out what is mapped to the hardware.

Tested for non-regression on various AR5416 (sparc64+i386), AR9281
and AR9285 (i386 only) adapters.
AR9380 part is not tested (hardware is not available to the general
public yet).

Committed over my AR9285 2.0.

update initvals and TX gains for AR9285 >=1.2
check result of carrier leakage calibration and redo calibration if needed
add support for newer AR9285 chips (AR9285 XE 2.0).

tested for non-regression on a DNXA-95
"Still seems to work here" kettenis@

Disable Reduced Interframe Space search on AR9160 to workaround
baseband issues.
It would be cleaner to modify directly the initvals for AR9160 but
I want to keep the exact same initvals as the Linux ath9k driver.

from ath9k

fix AR_PHY_TX_DESIRED_SCALE_CCK mask (only affect AR9280 2.0
with ROM rev >= 20)
do some cleanup of phy registers definitions while i'm here.

if a radio switch exists, configure the GPIO pin to which it is
connected to raise an interrupt when the pin goes low (or high
depending on the polarity of the radio switch.)
turn the interface down when the interrupt occurs.
this is the same behaviour as in wpi(4) and iwn(4).

cleanup interrupts processing while i'm here.
remove ATHN_INTR_MITIGATION compile option (it is set by default.)

AR9287 uses GPIO pin 8 for LED, not 1.
Turn link LED on while associated.

translate a comment from french to english.
no binary change.

athn(4), a driver for Atheros 802.11a/g/n devices.
written from scratch based on the vendor driver for Linux (ath9k).
AR9285 and AR9287 parts are 100% untested.
only basic functionnalities are enabled for now.

committed over an AR9281.

"commit" deraadt

Complete athn(4) noisefloor calibration code and enable it.
Update default/min/max noisefloor values to those used by Linux ath9k.
Tested by jmc, juanfra, kn, and myself, on 9280 and 9271 devices.

The athn(4) PCI driver forgot about adding the default noisefloor to
measured RSSI values. The same is already done for USB devices.
RSSI values shown in ifconfig make sense now.

ok kevlo@

Make monitor work with athn(4) on my 3T3R AR9380 device.
This card can now receive packets. Transmit is still broken and
Kevin Lo reports that his 2T2R AR9380 device cannot receive yet.

Add cast to mask and shift macros to silence warnings generated by clang.

ok millert@

Allow a variable number of words for the Serializer/Deserializer programming.
Probably not enought to make the AR9380 chips to work, but at least the kernel
shouldn't crash anymore when we see one.

ok stsp@

"athn* at uhub? port ?"
this adds preliminary support for the Atheros AR9271 chipset and
probably the AR9280+AR7010 and AR9287+AR7010 too though those were
not tested.
scanning still takes a very long time (~1 sec per channel) but
otherwise, operation in STA mode seems stable.
will implement fast channel change soon.

committed over the Ubiquiti WifiStation EXT (AR9271) on i386 with WPA.
requires firmware (see man page for details)

ok deraadt@ (who checked the .h files)

unbreak kernel builds; sorry guys.

pointed out by Benoit Lecocq.

commit some bits that will be required by AR9271/AR7010

Make the athn(4) back-end more bus agnostic by moving read and write
operations to callbacks in the PCI and CardBus front-ends.
This will allow support of other buses like USB.
Assume the following memory model:
- writes are ordered but may be buffered and require explicit flush
- a read always flushes all buffered writes

Implement PA linearization on adapters with digital predistorters
(AR9003 family only).

The power amplifier predistortion state machine works as follows:
1) Disable digital predistorters for all Tx chains
2) Repeat steps 3~7 for all Tx chains
3) Force Tx gain to that of training signal
4) Send training signal (asynchronous)
5) Wait for training signal to complete (asynchronous)
6) Read PA measurements (input power, output power, output phase)
7) Compute the predistortion function that linearizes PA output
8) Write predistortion functions to hardware tables for all Tx chains
9) Enable digital predistorters for all Tx chains

from ath9k (though implementation differs a lot)

enable async fifo for >=AR9287 1.3 only.
from ath9k.

initial Host AP bits.

fix athn_updateslot for fast PLL clock and 40MHz CBW

initialization values for AR9380 2.2.
turns out the Rx gain tables are the same as 2.0 (and the Tx gain
registers too), which saves us a few bytes.

athn(4) is going to support a new family of Atheros 802.11n
chips (AR9003), which differs from the currently supported
families (AR5008, AR9001 and AR9002).

The main differences (from a driver point of view) are:

* DMA:
Tx and Rx descriptors have changed.
A single Tx descriptor can now reference up to 4 scatter/gather
DMA segments.
There is now a DMA ring for reporting Tx status with separate
Tx status descriptors (this ring is used to report Tx status for
all the Tx FIFOs).
Rx status descriptors are now put at the beginning of Rx buffers
and do not need to be allocated separately from buffers.
There are two Rx FIFOs (low priority and high priority) instead
of one.

* ROM:
The AR9003 family uses OTP-ROM instead of EEPROM.
Reading the ROM is totally insane since vendors can provide only
the chunks of ROM that differ from a default image (and thus the
default image has to be stored in the driver).
This is referenced as "compressed ROM" in the Linux driver, though
there is no real compression involved, at least for the moment.

* PHY registers:
All PHY registers have changed.
Some registers offsets do not fit on 16 bits anymore, but
since they are 32-bit aligned, we can still make them fit on
16 bits to save .rodata space in initialization tables.

* MAC registers:
Some MAC registers offsets have changed (GPIO, interrupt masks)
which is quite annoying (though ~98% remain the same.)

* Initialization values:
Initialization values are now split in mac/soc/bb/radio blocks
and pre/core/post phases in the Linux driver. I have chosen to
not go that road and merge these blocks in modal and non-modal
initialization values (similar to the other families).
The initialization order remains exactly the same as the Linux
driver though.

To manage these differences, I have split athn.c in two backends:
ar5008.c contains the bits that are specific to the AR5008,
AR9001 and AR9002 families (used by ar5416.c, ar9280.c,
ar9285.c and ar9287.c) and that were previously in athn.c.

ar9003.c contains the bits that are specific to the new
AR9003 family (used by ar9380.c only for now.)

I have introduced a thin hardware abstraction layer (actually
a set of pointers to functions) that is used in athn.c.
My intent is to keep this abstraction layer as thin as possible
and not to create another ugly pile of abstraction layers a la
MadWifi.

I think I've managed to keep things sane, probably at the expense
of duplicating some code in both ar5008.c and ar9003.c, but at
least we do not have to dig through layers and layers of virtual
descriptors to figure out what is mapped to the hardware.

Tested for non-regression on various AR5416 (sparc64+i386), AR9281
and AR9285 (i386 only) adapters.
AR9380 part is not tested (hardware is not available to the general
public yet).

Committed over my AR9285 2.0.

update initvals and TX gains for AR9285 >=1.2
check result of carrier leakage calibration and redo calibration if needed
add support for newer AR9285 chips (AR9285 XE 2.0).

tested for non-regression on a DNXA-95
"Still seems to work here" kettenis@

Disable Reduced Interframe Space search on AR9160 to workaround
baseband issues.
It would be cleaner to modify directly the initvals for AR9160 but
I want to keep the exact same initvals as the Linux ath9k driver.

from ath9k

fix AR_PHY_TX_DESIRED_SCALE_CCK mask (only affect AR9280 2.0
with ROM rev >= 20)
do some cleanup of phy registers definitions while i'm here.

if a radio switch exists, configure the GPIO pin to which it is
connected to raise an interrupt when the pin goes low (or high
depending on the polarity of the radio switch.)
turn the interface down when the interrupt occurs.
this is the same behaviour as in wpi(4) and iwn(4).

cleanup interrupts processing while i'm here.
remove ATHN_INTR_MITIGATION compile option (it is set by default.)

AR9287 uses GPIO pin 8 for LED, not 1.
Turn link LED on while associated.

translate a comment from french to english.
no binary change.

athn(4), a driver for Atheros 802.11a/g/n devices.
written from scratch based on the vendor driver for Linux (ath9k).
AR9285 and AR9287 parts are 100% untested.
only basic functionnalities are enabled for now.

committed over an AR9281.

"commit" deraadt

The athn(4) PCI driver forgot about adding the default noisefloor to
measured RSSI values. The same is already done for USB devices.
RSSI values shown in ifconfig make sense now.

ok kevlo@

Make monitor work with athn(4) on my 3T3R AR9380 device.
This card can now receive packets. Transmit is still broken and
Kevin Lo reports that his 2T2R AR9380 device cannot receive yet.

Add cast to mask and shift macros to silence warnings generated by clang.

ok millert@

Allow a variable number of words for the Serializer/Deserializer programming.
Probably not enought to make the AR9380 chips to work, but at least the kernel
shouldn't crash anymore when we see one.

ok stsp@

"athn* at uhub? port ?"
this adds preliminary support for the Atheros AR9271 chipset and
probably the AR9280+AR7010 and AR9287+AR7010 too though those were
not tested.
scanning still takes a very long time (~1 sec per channel) but
otherwise, operation in STA mode seems stable.
will implement fast channel change soon.

committed over the Ubiquiti WifiStation EXT (AR9271) on i386 with WPA.
requires firmware (see man page for details)

ok deraadt@ (who checked the .h files)

unbreak kernel builds; sorry guys.

pointed out by Benoit Lecocq.

commit some bits that will be required by AR9271/AR7010

Make the athn(4) back-end more bus agnostic by moving read and write
operations to callbacks in the PCI and CardBus front-ends.
This will allow support of other buses like USB.
Assume the following memory model:
- writes are ordered but may be buffered and require explicit flush
- a read always flushes all buffered writes

Implement PA linearization on adapters with digital predistorters
(AR9003 family only).

The power amplifier predistortion state machine works as follows:
1) Disable digital predistorters for all Tx chains
2) Repeat steps 3~7 for all Tx chains
3) Force Tx gain to that of training signal
4) Send training signal (asynchronous)
5) Wait for training signal to complete (asynchronous)
6) Read PA measurements (input power, output power, output phase)
7) Compute the predistortion function that linearizes PA output
8) Write predistortion functions to hardware tables for all Tx chains
9) Enable digital predistorters for all Tx chains

from ath9k (though implementation differs a lot)

enable async fifo for >=AR9287 1.3 only.
from ath9k.

initial Host AP bits.

fix athn_updateslot for fast PLL clock and 40MHz CBW

initialization values for AR9380 2.2.
turns out the Rx gain tables are the same as 2.0 (and the Tx gain
registers too), which saves us a few bytes.

athn(4) is going to support a new family of Atheros 802.11n
chips (AR9003), which differs from the currently supported
families (AR5008, AR9001 and AR9002).

The main differences (from a driver point of view) are:

* DMA:
Tx and Rx descriptors have changed.
A single Tx descriptor can now reference up to 4 scatter/gather
DMA segments.
There is now a DMA ring for reporting Tx status with separate
Tx status descriptors (this ring is used to report Tx status for
all the Tx FIFOs).
Rx status descriptors are now put at the beginning of Rx buffers
and do not need to be allocated separately from buffers.
There are two Rx FIFOs (low priority and high priority) instead
of one.

* ROM:
The AR9003 family uses OTP-ROM instead of EEPROM.
Reading the ROM is totally insane since vendors can provide only
the chunks of ROM that differ from a default image (and thus the
default image has to be stored in the driver).
This is referenced as "compressed ROM" in the Linux driver, though
there is no real compression involved, at least for the moment.

* PHY registers:
All PHY registers have changed.
Some registers offsets do not fit on 16 bits anymore, but
since they are 32-bit aligned, we can still make them fit on
16 bits to save .rodata space in initialization tables.

* MAC registers:
Some MAC registers offsets have changed (GPIO, interrupt masks)
which is quite annoying (though ~98% remain the same.)

* Initialization values:
Initialization values are now split in mac/soc/bb/radio blocks
and pre/core/post phases in the Linux driver. I have chosen to
not go that road and merge these blocks in modal and non-modal
initialization values (similar to the other families).
The initialization order remains exactly the same as the Linux
driver though.

To manage these differences, I have split athn.c in two backends:
ar5008.c contains the bits that are specific to the AR5008,
AR9001 and AR9002 families (used by ar5416.c, ar9280.c,
ar9285.c and ar9287.c) and that were previously in athn.c.

ar9003.c contains the bits that are specific to the new
AR9003 family (used by ar9380.c only for now.)

I have introduced a thin hardware abstraction layer (actually
a set of pointers to functions) that is used in athn.c.
My intent is to keep this abstraction layer as thin as possible
and not to create another ugly pile of abstraction layers a la
MadWifi.

I think I've managed to keep things sane, probably at the expense
of duplicating some code in both ar5008.c and ar9003.c, but at
least we do not have to dig through layers and layers of virtual
descriptors to figure out what is mapped to the hardware.

Tested for non-regression on various AR5416 (sparc64+i386), AR9281
and AR9285 (i386 only) adapters.
AR9380 part is not tested (hardware is not available to the general
public yet).

Committed over my AR9285 2.0.

update initvals and TX gains for AR9285 >=1.2
check result of carrier leakage calibration and redo calibration if needed
add support for newer AR9285 chips (AR9285 XE 2.0).

tested for non-regression on a DNXA-95
"Still seems to work here" kettenis@

Disable Reduced Interframe Space search on AR9160 to workaround
baseband issues.
It would be cleaner to modify directly the initvals for AR9160 but
I want to keep the exact same initvals as the Linux ath9k driver.

from ath9k

fix AR_PHY_TX_DESIRED_SCALE_CCK mask (only affect AR9280 2.0
with ROM rev >= 20)
do some cleanup of phy registers definitions while i'm here.

if a radio switch exists, configure the GPIO pin to which it is
connected to raise an interrupt when the pin goes low (or high
depending on the polarity of the radio switch.)
turn the interface down when the interrupt occurs.
this is the same behaviour as in wpi(4) and iwn(4).

cleanup interrupts processing while i'm here.
remove ATHN_INTR_MITIGATION compile option (it is set by default.)

AR9287 uses GPIO pin 8 for LED, not 1.
Turn link LED on while associated.

translate a comment from french to english.
no binary change.

athn(4), a driver for Atheros 802.11a/g/n devices.
written from scratch based on the vendor driver for Linux (ath9k).
AR9285 and AR9287 parts are 100% untested.
only basic functionnalities are enabled for now.

committed over an AR9281.

"commit" deraadt