athnreg.h revision 1.11
1/* $OpenBSD: athnreg.h,v 1.11 2010/05/16 09:19:48 damien Exp $ */ 2 3/*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2009 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * MAC registers. 22 */ 23#define AR_CR 0x0008 24#define AR_RXDP 0x000c 25#define AR_CFG 0x0014 26#define AR_RXBP_THRESH 0x0018 27#define AR_MIRT 0x0020 28#define AR_IER 0x0024 29#define AR_TIMT 0x0028 30#define AR_RIMT 0x002c 31#define AR_TXCFG 0x0030 32#define AR_RXCFG 0x0034 33#define AR_MIBC 0x0040 34#define AR_TOPS 0x0044 35#define AR_RXNPTO 0x0048 36#define AR_TXNPTO 0x004c 37#define AR_RPGTO 0x0050 38#define AR_RPCNT 0x0054 39#define AR_MACMISC 0x0058 40#define AR_DATABUF_SIZE 0x0060 41#define AR_GTXTO 0x0064 42#define AR_GTTM 0x0068 43#define AR_CST 0x006c 44#define AR_HP_RXDP 0x0074 45#define AR_LP_RXDP 0x0078 46#define AR_ISR 0x0080 47#define AR_ISR_S0 0x0084 48#define AR_ISR_S1 0x0088 49#define AR_ISR_S2 0x008c 50#define AR_ISR_S3 0x0090 51#define AR_ISR_S4 0x0094 52#define AR_ISR_S5 0x0098 53#define AR_IMR 0x00a0 54#define AR_IMR_S0 0x00a4 55#define AR_IMR_S1 0x00a8 56#define AR_IMR_S2 0x00ac 57#define AR_IMR_S3 0x00b0 58#define AR_IMR_S4 0x00b4 59#define AR_IMR_S5 0x00b8 60#define AR_ISR_RAC 0x00c0 61#define AR_ISR_S0_S 0x00c4 62#define AR_ISR_S1_S 0x00c8 63#define AR_DMADBG(i) (0x00e0 + (i) * 4) 64#define AR_QTXDP(i) (0x0800 + (i) * 4) 65#define AR_Q_STATUS_RING_START 0x0830 66#define AR_Q_STATUS_RING_END 0x0834 67#define AR_Q_TXE 0x0840 68#define AR_Q_TXD 0x0880 69#define AR_QCBRCFG(i) (0x08c0 + (i) * 4) 70#define AR_QRDYTIMECFG(i) (0x0900 + (i) * 4) 71#define AR_Q_ONESHOTARM_SC 0x0940 72#define AR_Q_ONESHOTARM_CC 0x0980 73#define AR_QMISC(i) (0x09c0 + (i) * 4) 74#define AR_QSTS(i) (0x0a00 + (i) * 4) 75#define AR_Q_RDYTIMESHDN 0x0a40 76#define AR_Q_DESC_CRCCHK 0x0a44 77#define AR_DQCUMASK(i) (0x1000 + (i) * 4) 78#define AR_D_GBL_IFS_SIFS 0x1030 79#define AR_D_TXBLK_CMD 0x1038 80#define AR_DLCL_IFS(i) (0x1040 + (i) * 4) 81#define AR_D_GBL_IFS_SLOT 0x1070 82#define AR_DRETRY_LIMIT(i) (0x1080 + (i) * 4) 83#define AR_D_GBL_IFS_EIFS 0x10b0 84#define AR_DCHNTIME(i) (0x10c0 + (i) * 4) 85#define AR_D_GBL_IFS_MISC 0x10f0 86#define AR_DMISC(i) (0x1100 + (i) * 4) 87#define AR_D_SEQNUM 0x1140 88#define AR_D_FPCTL 0x1230 89#define AR_D_TXPSE 0x1270 90#define AR_D_TXSLOTMASK 0x12f0 91#define AR_MAC_SLEEP 0x1f00 92#define AR_CFG_LED 0x1f04 93#define AR_EEPROM_OFFSET(i) (0x2000 + (i) * 4) 94#define AR_RC 0x4000 95#define AR_WA 0x4004 96#define AR_PM_STATE 0x4008 97#define AR_PCIE_PM_CTRL 0x4014 98#define AR_HOST_TIMEOUT 0x4018 99#define AR_EEPROM 0x401c 100#define AR_SREV 0x4020 101#define AR_AHB_MODE 0x4024 102#define AR_INTR_SYNC_CAUSE 0x4028 103#define AR_INTR_SYNC_ENABLE 0x402c 104#define AR_INTR_ASYNC_MASK 0x4030 105#define AR_INTR_SYNC_MASK 0x4034 106#define AR_INTR_ASYNC_CAUSE 0x4038 107#define AR_INTR_ASYNC_ENABLE 0x403c 108#define AR_PCIE_SERDES 0x4040 109#define AR_PCIE_SERDES2 0x4044 110#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4 111#define AR_INTR_PRIO_ASYNC_MASK 0x40c8 112#define AR_INTR_PRIO_SYNC_MASK 0x40cc 113#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4 114#define AR_RTC_RC 0x7000 115#define AR_RTC_XTAL_CONTROL 0x7004 116#define AR_RTC_REG_CONTROL0 0x7008 117#define AR_RTC_REG_CONTROL1 0x700c 118#define AR_RTC_PLL_CONTROL 0x7014 119#define AR_RTC_RESET 0x7040 120#define AR_RTC_STATUS 0x7044 121#define AR_RTC_SLEEP_CLK 0x7048 122#define AR_RTC_FORCE_WAKE 0x704c 123#define AR_RTC_INTR_CAUSE 0x7050 124#define AR_RTC_INTR_ENABLE 0x7054 125#define AR_RTC_INTR_MASK 0x7058 126#define AR_STA_ID0 0x8000 127#define AR_STA_ID1 0x8004 128#define AR_BSS_ID0 0x8008 129#define AR_BSS_ID1 0x800c 130#define AR_BCN_RSSI_AVE 0x8010 131#define AR_TIME_OUT 0x8014 132#define AR_RSSI_THR 0x8018 133#define AR_USEC 0x801c 134#define AR_RESET_TSF 0x8020 135#define AR_MAX_CFP_DUR 0x8038 136#define AR_RX_FILTER 0x803c 137#define AR_MCAST_FIL0 0x8040 138#define AR_MCAST_FIL1 0x8044 139#define AR_DIAG_SW 0x8048 140#define AR_TSF_L32 0x804c 141#define AR_TSF_U32 0x8050 142#define AR_TST_ADDAC 0x8054 143#define AR_DEF_ANTENNA 0x8058 144#define AR_AES_MUTE_MASK0 0x805c 145#define AR_AES_MUTE_MASK1 0x8060 146#define AR_GATED_CLKS 0x8064 147#define AR_OBS_BUS_CTRL 0x8068 148#define AR_OBS_BUS_1 0x806c 149#define AR_LAST_TSTP 0x8080 150#define AR_NAV 0x8084 151#define AR_RTS_OK 0x8088 152#define AR_RTS_FAIL 0x808c 153#define AR_ACK_FAIL 0x8090 154#define AR_FCS_FAIL 0x8094 155#define AR_BEACON_CNT 0x8098 156#define AR_SLEEP1 0x80d4 157#define AR_SLEEP2 0x80d8 158#define AR_BSSMSKL 0x80e0 159#define AR_BSSMSKU 0x80e4 160#define AR_TPC 0x80e8 161#define AR_TFCNT 0x80ec 162#define AR_RFCNT 0x80f0 163#define AR_RCCNT 0x80f4 164#define AR_CCCNT 0x80f8 165#define AR_QUIET1 0x80fc 166#define AR_QUIET2 0x8100 167#define AR_TSF_PARM 0x8104 168#define AR_QOS_NO_ACK 0x8108 169#define AR_PHY_ERR 0x810c 170#define AR_RXFIFO_CFG 0x8114 171#define AR_MIC_QOS_CONTROL 0x8118 172#define AR_MIC_QOS_SELECT 0x811c 173#define AR_PCU_MISC 0x8120 174#define AR_FILT_OFDM 0x8124 175#define AR_FILT_CCK 0x8128 176#define AR_PHY_ERR_1 0x812c 177#define AR_PHY_ERR_MASK_1 0x8130 178#define AR_PHY_ERR_2 0x8134 179#define AR_PHY_ERR_MASK_2 0x8138 180#define AR_TSFOOR_THRESHOLD 0x813c 181#define AR_PHY_ERR_EIFS_MASK 0x8144 182#define AR_PHY_ERR_3 0x8168 183#define AR_PHY_ERR_MASK_3 0x816c 184#define AR_BT_COEX_MODE 0x8170 185#define AR_BT_COEX_WEIGHT 0x8174 186#define AR_BT_COEX_MODE2 0x817c 187#define AR_NEXT_NDP2_TIMER(i) (0x8180 + (i) * 4) 188#define AR_NDP2_PERIOD(i) (0x81a0 + (i) * 4) 189#define AR_NDP2_TIMER_MODE 0x81c0 190#define AR_TXSIFS 0x81d0 191#define AR_TXOP_X 0x81ec 192#define AR_TXOP_0_3 0x81f0 193#define AR_TXOP_4_7 0x81f4 194#define AR_TXOP_8_11 0x81f8 195#define AR_TXOP_12_15 0x81fc 196#define AR_GEN_TIMER(i) (0x8200 + (i) * 4) 197#define AR_NEXT_TBTT_TIMER AR_GEN_TIMER(0) 198#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMER(1) 199#define AR_NEXT_CFP AR_GEN_TIMER(2) 200#define AR_NEXT_HCF AR_GEN_TIMER(3) 201#define AR_NEXT_TIM AR_GEN_TIMER(4) 202#define AR_NEXT_DTIM AR_GEN_TIMER(5) 203#define AR_NEXT_QUIET_TIMER AR_GEN_TIMER(6) 204#define AR_NEXT_NDP_TIMER AR_GEN_TIMER(7) 205#define AR_BEACON_PERIOD AR_GEN_TIMER(8) 206#define AR_DMA_BEACON_PERIOD AR_GEN_TIMER(9) 207#define AR_SWBA_PERIOD AR_GEN_TIMER(10) 208#define AR_HCF_PERIOD AR_GEN_TIMER(11) 209#define AR_TIM_PERIOD AR_GEN_TIMER(12) 210#define AR_DTIM_PERIOD AR_GEN_TIMER(13) 211#define AR_QUIET_PERIOD AR_GEN_TIMER(14) 212#define AR_NDP_PERIOD AR_GEN_TIMER(15) 213#define AR_TIMER_MODE 0x8240 214#define AR_SLP32_MODE 0x8244 215#define AR_SLP32_WAKE 0x8248 216#define AR_SLP32_INC 0x824c 217#define AR_SLP_CNT 0x8250 218#define AR_SLP_CYCLE_CNT 0x8254 219#define AR_SLP_MIB_CTRL 0x8258 220#define AR_WOW_PATTERN_REG 0x825c 221#define AR_WOW_COUNT_REG 0x8260 222#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 223#define AR_WOW_BCN_EN_REG 0x8270 224#define AR_WOW_BCN_TIMO_REG 0x8274 225#define AR_WOW_KEEP_ALIVE_TIMO_REG 0x8278 226#define AR_WOW_KEEP_ALIVE_REG 0x827c 227#define AR_WOW_US_SCALAR_REG 0x8284 228#define AR_WOW_KEEP_ALIVE_DELAY_REG 0x8288 229#define AR_WOW_PATTERN_MATCH_REG 0x828c 230#define AR_WOW_PATTERN_OFF1_REG 0x8290 231#define AR_WOW_PATTERN_OFF2_REG 0x8294 232#define AR_WOW_EXACT_REG 0x829c 233#define AR_2040_MODE 0x8318 234#define AR_EXTRCCNT 0x8328 235#define AR_SELFGEN_MASK 0x832c 236#define AR_PCU_TXBUF_CTRL 0x8340 237#define AR_PCU_MISC_MODE2 0x8344 238#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 239#define AR_WOW_LENGTH1_REG 0x8360 240#define AR_WOW_LENGTH2_REG 0x8364 241#define AR_WOW_PATTERN_MATCH_LT_256B 0x8368 242#define AR_RATE_DURATION(i) (0x8700 + (i) * 4) 243#define AR_KEYTABLE(i) (0x8800 + (i) * 32) 244#define AR_KEYTABLE_KEY0(i) (AR_KEYTABLE(i) + 0) 245#define AR_KEYTABLE_KEY1(i) (AR_KEYTABLE(i) + 4) 246#define AR_KEYTABLE_KEY2(i) (AR_KEYTABLE(i) + 8) 247#define AR_KEYTABLE_KEY3(i) (AR_KEYTABLE(i) + 12) 248#define AR_KEYTABLE_KEY4(i) (AR_KEYTABLE(i) + 16) 249#define AR_KEYTABLE_TYPE(i) (AR_KEYTABLE(i) + 20) 250#define AR_KEYTABLE_MAC0(i) (AR_KEYTABLE(i) + 24) 251#define AR_KEYTABLE_MAC1(i) (AR_KEYTABLE(i) + 28) 252 253 254/* Bits for AR_CR. */ 255#define AR_CR_RXE 0x00000004 256#define AR_CR_RXD 0x00000020 257#define AR_CR_SWI 0x00000040 258 259/* Bits for AR_CFG. */ 260#define AR_CFG_SWTD 0x00000001 261#define AR_CFG_SWTB 0x00000002 262#define AR_CFG_SWRD 0x00000004 263#define AR_CFG_SWRB 0x00000008 264#define AR_CFG_SWRG 0x00000010 265#define AR_CFG_AP_ADHOC_INDICATION 0x00000020 266#define AR_CFG_PHOK 0x00000100 267#define AR_CFG_EEBS 0x00000200 268#define AR_CFG_CLK_GATE_DIS 0x00000400 269#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M 0x00060000 270#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 271 272/* Bits for AR_RXBP_THRESH. */ 273#define AR_RXBP_THRESH_HP_M 0x0000000f 274#define AR_RXBP_THRESH_HP_S 0 275#define AR_RXBP_THRESH_LP_M 0x00003f00 276#define AR_RXBP_THRESH_LP_S 8 277 278/* Bits for AR_IER. */ 279#define AR_IER_ENABLE 0x00000001 280 281/* Bits for AR_TIMT. */ 282#define AR_TIMT_LAST_M 0x0000ffff 283#define AR_TIMT_LAST_S 0 284#define AR_TIMT_FIRST_M 0xffff0000 285#define AR_TIMT_FIRST_S 16 286 287/* Bits for AR_RIMT. */ 288#define AR_RIMT_LAST_M 0x0000ffff 289#define AR_RIMT_LAST_S 0 290#define AR_RIMT_FIRST_M 0xffff0000 291#define AR_RIMT_FIRST_S 16 292 293/* Bits for AR_[TR]XCFG_DMASZ fields. */ 294#define AR_DMASZ_4B 0 295#define AR_DMASZ_8B 1 296#define AR_DMASZ_16B 2 297#define AR_DMASZ_32B 3 298#define AR_DMASZ_64B 4 299#define AR_DMASZ_128B 5 300#define AR_DMASZ_256B 6 301#define AR_DMASZ_512B 7 302 303/* Bits for AR_TXCFG. */ 304#define AR_TXCFG_DMASZ_M 0x00000007 305#define AR_TXCFG_DMASZ_S 0 306#define AR_TXCFG_FTRIG_M 0x000003f0 307#define AR_TXCFG_FTRIG_S 4 308#define AR_TXCFG_FTRIG_IMMED ( 0 / 64) 309#define AR_TXCFG_FTRIG_64B ( 64 / 64) 310#define AR_TXCFG_FTRIG_128B (128 / 64) 311#define AR_TXCFG_FTRIG_192B (192 / 64) 312#define AR_TXCFG_FTRIG_256B (256 / 64) 313#define AR_TXCFG_FTRIG_512B (512 / 64) 314#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 315 316/* Bits for AR_RXCFG. */ 317#define AR_RXCFG_DMASZ_M 0x00000007 318#define AR_RXCFG_DMASZ_S 0 319#define AR_RXCFG_CHIRP 0x00000008 320#define AR_RXCFG_ZLFDMA 0x00000010 321 322/* Bits for AR_MIBC. */ 323#define AR_MIBC_COW 0x00000001 324#define AR_MIBC_FMC 0x00000002 325#define AR_MIBC_CMC 0x00000004 326#define AR_MIBC_MCS 0x00000008 327 328/* Bits for AR_TOPS. */ 329#define AR_TOPS_MASK 0x0000ffff 330 331/* Bits for AR_RXNPTO. */ 332#define AR_RXNPTO_MASK 0x000003ff 333 334/* Bits for AR_TXNPTO. */ 335#define AR_TXNPTO_MASK 0x000003ff 336#define AR_TXNPTO_QCU_MASK 0x000ffc00 337 338/* Bits for AR_RPGTO. */ 339#define AR_RPGTO_MASK 0x000003ff 340 341/* Bits for AR_RPCNT. */ 342#define AR_RPCNT_MASK 0x0000001f 343 344/* Bits for AR_MACMISC. */ 345#define AR_MACMISC_PCI_EXT_FORCE 0x00000010 346#define AR_MACMISC_DMA_OBS_M 0x000001e0 347#define AR_MACMISC_DMA_OBS_S 5 348#define AR_MACMISC_MISC_OBS_M 0x00000e00 349#define AR_MACMISC_MISC_OBS_S 9 350#define AR_MACMISC_MISC_OBS_BUS_LSB_M 0x00007000 351#define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 352#define AR_MACMISC_MISC_OBS_BUS_MSB_M 0x00038000 353#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 354 355/* Bits for AR_GTXTO. */ 356#define AR_GTXTO_TIMEOUT_COUNTER_M 0x0000ffff 357#define AR_GTXTO_TIMEOUT_COUNTER_S 0 358#define AR_GTXTO_TIMEOUT_LIMIT_M 0xffff0000 359#define AR_GTXTO_TIMEOUT_LIMIT_S 16 360 361/* Bits for AR_GTTM. */ 362#define AR_GTTM_USEC 0x00000001 363#define AR_GTTM_IGNORE_IDLE 0x00000002 364#define AR_GTTM_RESET_IDLE 0x00000004 365#define AR_GTTM_CST_USEC 0x00000008 366 367/* Bits for AR_CST. */ 368#define AR_CST_TIMEOUT_COUNTER_M 0x0000ffff 369#define AR_CST_TIMEOUT_COUNTER_S 0 370#define AR_CST_TIMEOUT_LIMIT_M 0xffff0000 371#define AR_CST_TIMEOUT_LIMIT_S 16 372 373/* Bits for AR_ISR. */ 374#define AR_ISR_RXOK 0x00000001 375#define AR_ISR_HP_RXOK 0x00000001 376#define AR_ISR_RXDESC 0x00000002 377#define AR_ISR_LP_RXOK 0x00000002 378#define AR_ISR_RXERR 0x00000004 379#define AR_ISR_RXNOPKT 0x00000008 380#define AR_ISR_RXEOL 0x00000010 381#define AR_ISR_RXORN 0x00000020 382#define AR_ISR_TXOK 0x00000040 383#define AR_ISR_TXDESC 0x00000080 384#define AR_ISR_TXERR 0x00000100 385#define AR_ISR_TXNOPKT 0x00000200 386#define AR_ISR_TXEOL 0x00000400 387#define AR_ISR_TXURN 0x00000800 388#define AR_ISR_MIB 0x00001000 389#define AR_ISR_SWI 0x00002000 390#define AR_ISR_RXPHY 0x00004000 391#define AR_ISR_RXKCM 0x00008000 392#define AR_ISR_SWBA 0x00010000 393#define AR_ISR_BRSSI 0x00020000 394#define AR_ISR_BMISS 0x00040000 395#define AR_ISR_TXMINTR 0x00080000 396#define AR_ISR_BNR 0x00100000 397#define AR_ISR_RXCHIRP 0x00200000 398#define AR_ISR_BCNMISC 0x00800000 399#define AR_ISR_TIM 0x00800000 400#define AR_ISR_RXMINTR 0x01000000 401#define AR_ISR_QCBROVF 0x02000000 402#define AR_ISR_QCBRURN 0x04000000 403#define AR_ISR_QTRIG 0x08000000 404#define AR_ISR_GENTMR 0x10000000 405#define AR_ISR_TXINTM 0x40000000 406#define AR_ISR_RXINTM 0x80000000 407 408/* Bits for AR_ISR_S0. */ 409#define AR_ISR_S0_QCU_TXOK_M 0x000003ff 410#define AR_ISR_S0_QCU_TXOK_S 0 411#define AR_ISR_S0_QCU_TXDESC_M 0x03ff0000 412#define AR_ISR_S0_QCU_TXDESC_S 16 413 414/* Bits for AR_ISR_S1. */ 415#define AR_ISR_S1_QCU_TXERR_M 0x000003ff 416#define AR_ISR_S1_QCU_TXERR_S 0 417#define AR_ISR_S1_QCU_TXEOL_M 0x03ff0000 418#define AR_ISR_S1_QCU_TXEOL_S 16 419 420/* Bits for AR_ISR_S2. */ 421#define AR_ISR_S2_QCU_TXURN_M 0x000003ff 422#define AR_ISR_S2_QCU_TXURN_S 0 423#define AR_ISR_S2_CST 0x00400000 424#define AR_ISR_S2_GTT 0x00800000 425#define AR_ISR_S2_TIM 0x01000000 426#define AR_ISR_S2_CABEND 0x02000000 427#define AR_ISR_S2_DTIMSYNC 0x04000000 428#define AR_ISR_S2_BCNTO 0x08000000 429#define AR_ISR_S2_CABTO 0x10000000 430#define AR_ISR_S2_DTIM 0x20000000 431#define AR_ISR_S2_TSFOOR 0x40000000 432#define AR_ISR_S2_TBTT_TIME 0x80000000 433 434/* Bits for AR_ISR_S3. */ 435#define AR_ISR_S3_QCU_QCBROVF_M 0x000003ff 436#define AR_ISR_S3_QCU_QCBROVF_S 0 437#define AR_ISR_S3_QCU_QCBRURN_M 0x03ff0000 438#define AR_ISR_S3_QCU_QCBRURN_S 0 439 440/* Bits for AR_ISR_S4. */ 441#define AR_ISR_S4_QCU_QTRIG_M 0x000003ff 442#define AR_ISR_S4_QCU_QTRIG_S 0 443 444/* Bits for AR_ISR_S5. */ 445#define AR_ISR_S5_TIMER_TRIG_M 0x000000ff 446#define AR_ISR_S5_TIMER_TRIG_S 0 447#define AR_ISR_S5_TIMER_THRESH_M 0x0007fe00 448#define AR_ISR_S5_TIMER_THRESH_S 9 449#define AR_ISR_S5_TIM_TIMER 0x00000010 450#define AR_ISR_S5_DTIM_TIMER 0x00000020 451#define AR_ISR_S5_GENTIMER_TRIG_M 0x0000ff80 452#define AR_ISR_S5_GENTIMER_TRIG_S 0 453#define AR_ISR_S5_GENTIMER_THRESH_M 0xff800000 454#define AR_ISR_S5_GENTIMER_THRESH_S 16 455 456/* Bits for AR_IMR. */ 457#define AR_IMR_RXOK 0x00000001 458#define AR_IMR_HP_RXOK 0x00000001 459#define AR_IMR_RXDESC 0x00000002 460#define AR_IMR_LP_RXOK 0x00000002 461#define AR_IMR_RXERR 0x00000004 462#define AR_IMR_RXNOPKT 0x00000008 463#define AR_IMR_RXEOL 0x00000010 464#define AR_IMR_RXORN 0x00000020 465#define AR_IMR_TXOK 0x00000040 466#define AR_IMR_TXDESC 0x00000080 467#define AR_IMR_TXERR 0x00000100 468#define AR_IMR_TXNOPKT 0x00000200 469#define AR_IMR_TXEOL 0x00000400 470#define AR_IMR_TXURN 0x00000800 471#define AR_IMR_MIB 0x00001000 472#define AR_IMR_SWI 0x00002000 473#define AR_IMR_RXPHY 0x00004000 474#define AR_IMR_RXKCM 0x00008000 475#define AR_IMR_SWBA 0x00010000 476#define AR_IMR_BRSSI 0x00020000 477#define AR_IMR_BMISS 0x00040000 478#define AR_IMR_TXMINTR 0x00080000 479#define AR_IMR_BNR 0x00100000 480#define AR_IMR_RXCHIRP 0x00200000 481#define AR_IMR_BCNMISC 0x00800000 482#define AR_IMR_TIM 0x00800000 483#define AR_IMR_RXMINTR 0x01000000 484#define AR_IMR_QCBROVF 0x02000000 485#define AR_IMR_QCBRURN 0x04000000 486#define AR_IMR_QTRIG 0x08000000 487#define AR_IMR_GENTMR 0x10000000 488#define AR_IMR_TXINTM 0x40000000 489#define AR_IMR_RXINTM 0x80000000 490 491#define AR_IMR_DEFAULT \ 492 (AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR | \ 493 AR_IMR_RXORN | AR_IMR_BCNMISC | AR_IMR_RXINTM | \ 494 AR_IMR_RXMINTR | AR_IMR_TXOK) 495#define AR_IMR_HOSTAP (AR_IMR_DEFAULT | AR_IMR_MIB) 496 497/* Bits for AR_IMR_S0. */ 498#define AR_IMR_S0_QCU_TXOK(qid) (1 << (qid)) 499#define AR_IMR_S0_QCU_TXDESC(qid) (1 << (16 + (qid))) 500 501/* Bits for AR_IMR_S1. */ 502#define AR_IMR_S1_QCU_TXERR(qid) (1 << (qid)) 503#define AR_IMR_S1_QCU_TXEOL(qid) (1 << (16 + (qid))) 504 505/* Bits for AR_IMR_S2. */ 506#define AR_IMR_S2_QCU_TXURN(qid) (1 << (qid)) 507#define AR_IMR_S2_CST 0x00400000 508#define AR_IMR_S2_GTT 0x00800000 509#define AR_IMR_S2_TIM 0x01000000 510#define AR_IMR_S2_CABEND 0x02000000 511#define AR_IMR_S2_DTIMSYNC 0x04000000 512#define AR_IMR_S2_BCNTO 0x08000000 513#define AR_IMR_S2_CABTO 0x10000000 514#define AR_IMR_S2_DTIM 0x20000000 515#define AR_IMR_S2_TSFOOR 0x40000000 516 517/* Bits for AR_IMR_S3. */ 518#define AR_IMR_S3_QCU_QCBROVF(qid) (1 << (qid)) 519#define AR_IMR_S3_QCU_QCBRURN(qid) (1 << (16 + (qid))) 520 521/* Bits for AR_IMR_S4. */ 522#define AR_IMR_S4_QCU_QTRIG(qid) (1 << (qid)) 523 524/* Bits for AR_IMR_S5. */ 525#define AR_IMR_S5_TIM_TIMER 0x00000010 526#define AR_IMR_S5_DTIM_TIMER 0x00000020 527#define AR_IMR_S5_TIMER_TRIG_M 0x000000ff 528#define AR_IMR_S5_TIMER_TRIG_S 0 529#define AR_IMR_S5_TIMER_THRESH_M 0x0000ff00 530#define AR_IMR_S5_TIMER_THRESH_S 0 531 532#define AR_NUM_QCU 10 533#define AR_QCU(x) (1 << (x)) 534 535/* Bits for AR_Q_TXE. */ 536#define AR_Q_TXE_M 0x000003ff 537#define AR_Q_TXE_S 0 538 539/* Bits for AR_Q_TXD. */ 540#define AR_Q_TXD_M 0x000003ff 541#define AR_Q_TXD_S 0 542 543/* Bits for AR_QCBRCFG_*. */ 544#define AR_Q_CBRCFG_INTERVAL_M 0x00ffffff 545#define AR_Q_CBRCFG_INTERVAL_S 0 546#define AR_Q_CBRCFG_OVF_THRESH_M 0xff000000 547#define AR_Q_CBRCFG_OVF_THRESH_S 24 548 549/* Bits for AR_QRDYTIMECFG_*. */ 550#define AR_Q_RDYTIMECFG_DURATION_M 0x00ffffff 551#define AR_Q_RDYTIMECFG_DURATION_S 0 552#define AR_Q_RDYTIMECFG_EN 0x01000000 553 554/* Bits for AR_QMISC_*. */ 555#define AR_Q_MISC_FSP_M 0x0000000f 556#define AR_Q_MISC_FSP_S 0 557#define AR_Q_MISC_FSP_ASAP 0 558#define AR_Q_MISC_FSP_CBR 1 559#define AR_Q_MISC_FSP_DBA_GATED 2 560#define AR_Q_MISC_FSP_TIM_GATED 3 561#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 562#define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 563#define AR_Q_MISC_ONE_SHOT_EN 0x00000010 564#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 565#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 566#define AR_Q_MISC_BEACON_USE 0x00000080 567#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 568#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 569#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 570#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 571 572/* Bits for AR_QSTS_*. */ 573#define AR_Q_STS_PEND_FR_CNT_M 0x00000003 574#define AR_Q_STS_PEND_FR_CNT_S 0 575#define AR_Q_STS_CBR_EXP_CNT_M 0x0000ff00 576#define AR_Q_STS_CBR_EXP_CNT_S 8 577 578/* Bits for AR_Q_DESC_CRCCHK. */ 579#define AR_Q_DESC_CRCCHK_EN 0x00000001 580 581#define AR_NUM_DCU 10 582#define AR_DCU(x) (1 << (x)) 583 584/* Bits for AR_D_QCUMASK_*. */ 585#define AR_D_QCUMASK_M 0x000003ff 586#define AR_D_QCUMASK_S 0 587 588/* Bits for AR_D_GBL_IFS_SIFS. */ 589#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003ab 590 591/* Bits for AR_D_TXBLK_CMD. */ 592#define AR_D_TXBLK_WRITE_BITMASK_M 0x0000ffff 593#define AR_D_TXBLK_WRITE_BITMASK_S 0 594#define AR_D_TXBLK_WRITE_SLICE_M 0x000f0000 595#define AR_D_TXBLK_WRITE_SLICE_S 16 596#define AR_D_TXBLK_WRITE_DCU_M 0x00f00000 597#define AR_D_TXBLK_WRITE_DCU_S 20 598#define AR_D_TXBLK_WRITE_COMMAND_M 0x0f000000 599#define AR_D_TXBLK_WRITE_COMMAND_S 24 600 601/* Bits for AR_DLCL_IFS. */ 602#define AR_D_LCL_IFS_CWMIN_M 0x000003ff 603#define AR_D_LCL_IFS_CWMIN_S 0 604#define AR_D_LCL_IFS_CWMAX_M 0x000ffc00 605#define AR_D_LCL_IFS_CWMAX_S 10 606#define AR_D_LCL_IFS_AIFS_M 0x0ff00000 607#define AR_D_LCL_IFS_AIFS_S 20 608 609/* Bits for AR_D_GBL_IFS_SLOT. */ 610#define AR_D_GBL_IFS_SLOT_M 0x0000ffff 611#define AR_D_GBL_IFS_SLOT_S 0 612#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 613 614/* Bits for AR_DRETRY_LIMIT_*. */ 615#define AR_D_RETRY_LIMIT_FR_SH_M 0x0000000f 616#define AR_D_RETRY_LIMIT_FR_SH_S 0 617#define AR_D_RETRY_LIMIT_STA_SH_M 0x00003f00 618#define AR_D_RETRY_LIMIT_STA_SH_S 8 619#define AR_D_RETRY_LIMIT_STA_LG_M 0x000fc000 620#define AR_D_RETRY_LIMIT_STA_LG_S 14 621 622/* Bits for AR_D_GBL_IFS_EIFS. */ 623#define AR_D_GBL_IFS_EIFS_M 0x0000ffff 624#define AR_D_GBL_IFS_EIFS_S 0 625#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000a5eb 626 627/* Bits for AR_DCHNTIME_*. */ 628#define AR_D_CHNTIME_DUR_M 0x000fffff 629#define AR_D_CHNTIME_DUR_S 0 630#define AR_D_CHNTIME_EN 0x00100000 631 632/* Bits for AR_D_GBL_IFS_MISC. */ 633#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 634#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 635#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000ffc00 636#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 637#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 638#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 639#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 640#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 641 642/* Bits for AR_DMISC_*. */ 643#define AR_D_MISC_BKOFF_THRESH_M 0x0000003f 644#define AR_D_MISC_BKOFF_THRESH_S 0 645#define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 646#define AR_D_MISC_CW_RESET_EN 0x00000080 647#define AR_D_MISC_FRAG_WAIT_EN 0x00000100 648#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 649#define AR_D_MISC_CW_BKOFF_EN 0x00001000 650#define AR_D_MISC_VIR_COL_HANDLING_M 0x0000c000 651#define AR_D_MISC_VIR_COL_HANDLING_S 14 652#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 653#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 654#define AR_D_MISC_BEACON_USE 0x00010000 655#define AR_D_MISC_ARB_LOCKOUT_CNTRL_M 0x00060000 656#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 657#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 658#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 659#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 660#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 661#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 662#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 663#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 664#define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 665 666/* Bits for AR_D_FPCTL. */ 667#define AR_D_FPCTL_DCU_M 0x0000000f 668#define AR_D_FPCTL_DCU_S 0 669#define AR_D_FPCTL_PREFETCH_EN 0x00000010 670#define AR_D_FPCTL_BURST_PREFETCH_M 0x00007fe0 671#define AR_D_FPCTL_BURST_PREFETCH_S 5 672 673/* Bits for AR_D_TXPSE. */ 674#define AR_D_TXPSE_CTRL_M 0x000003ff 675#define AR_D_TXPSE_CTRL_S 0 676#define AR_D_TXPSE_STATUS 0x00010000 677 678/* Bits for AR_D_TXSLOTMASK. */ 679#define AR_D_TXSLOTMASK_NUM 0x0000000f 680 681/* Bits for AR_MAC_SLEEP. */ 682#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 683 684/* Bits for AR_CFG_LED. */ 685#define AR_CFG_SCLK_RATE_IND_M 0x00000003 686#define AR_CFG_SCLK_RATE_IND_S 0 687#define AR_CFG_SCLK_32MHZ 0 688#define AR_CFG_SCLK_4MHZ 1 689#define AR_CFG_SCLK_1MHZ 2 690#define AR_CFG_SCLK_32KHZ 3 691#define AR_CFG_LED_BLINK_SLOW 0x00000008 692#define AR_CFG_LED_BLINK_THRESH_SEL_M 0x00000070 693#define AR_CFG_LED_BLINK_THRESH_SEL_S 4 694#define AR_CFG_LED_MODE_SEL_M 0x00000380 695#define AR_CFG_LED_MODE_SEL_S 7 696#define AR_CFG_LED_POWER_M 0x00000280 697#define AR_CFG_LED_POWER_S 7 698#define AR_CFG_LED_NETWORK_M 0x00000300 699#define AR_CFG_LED_NETWORK_S 7 700#define AR_CFG_LED_MODE_PROP 0 701#define AR_CFG_LED_MODE_RPROP 1 702#define AR_CFG_LED_MODE_SPLIT 2 703#define AR_CFG_LED_MODE_RAND 3 704#define AR_CFG_LED_MODE_POWER_OFF 4 705#define AR_CFG_LED_MODE_POWER_ON 5 706#define AR_CFG_LED_MODE_NETWORK_OFF 4 707#define AR_CFG_LED_MODE_NETWORK_ON 6 708#define AR_CFG_LED_ASSOC_CTL_M 0x00000c00 709#define AR_CFG_LED_ASSOC_CTL_S 10 710#define AR_CFG_LED_ASSOC_NONE 0 711#define AR_CFG_LED_ASSOC_ACTIVE 1 712#define AR_CFG_LED_ASSOC_PENDING 2 713 714/* Bit for AR_RC. */ 715#define AR_RC_AHB 0x00000001 716#define AR_RC_APB 0x00000002 717#define AR_RC_HOSTIF 0x00000100 718 719/* Bits for AR_WA. */ 720#define AR5416_WA_DEFAULT 0x0000073f 721#define AR9280_WA_DEFAULT 0x0040073b 722#define AR9285_WA_DEFAULT 0x004a050b 723#define AR_WA_UNTIE_RESET_EN 0x00008000 724#define AR_WA_RESET_EN 0x00040000 725#define AR_WA_ANALOG_SHIFT 0x00100000 726#define AR_WA_POR_SHORT 0x00200000 727 728/* Bits for AR_PM_STATE. */ 729#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 730 731/* Bits for AR_PCIE_PM_CTRL. */ 732#define AR_PCIE_PM_CTRL_ENA 0x00080000 733 734/* Bits for AR_HOST_TIMEOUT. */ 735#define AR_HOST_TIMEOUT_APB_CNTR_M 0x0000ffff 736#define AR_HOST_TIMEOUT_APB_CNTR_S 0 737#define AR_HOST_TIMEOUT_LCL_CNTR_M 0xffff0000 738#define AR_HOST_TIMEOUT_LCL_CNTR_S 16 739 740/* Bits for AR_EEPROM. */ 741#define AR_EEPROM_ABSENT 0x00000100 742#define AR_EEPROM_CORRUPT 0x00000200 743#define AR_EEPROM_PROT_MASK_M 0x03fffc00 744#define AR_EEPROM_PROT_MASK_S 10 745 746/* Bits for AR_SREV. */ 747#define AR_SREV_ID_M 0x000000ff 748#define AR_SREV_ID_S 0 749#define AR_SREV_REVISION_M 0x00000007 750#define AR_SREV_REVISION_S 0 751#define AR_SREV_VERSION_M 0x000000f0 752#define AR_SREV_VERSION_S 4 753#define AR_SREV_VERSION2_M 0xfffc0000 754#define AR_SREV_VERSION2_S 12 /* XXX Hack. */ 755#define AR_SREV_TYPE2_M 0x0003f000 756#define AR_SREV_TYPE2_S 12 757#define AR_SREV_TYPE2_CHAIN 0x00001000 758#define AR_SREV_TYPE2_HOST_MODE 0x00002000 759#define AR_SREV_REVISION2_M 0x00000f00 760#define AR_SREV_REVISION2_S 8 761#define AR_SREV_VERSION_5416_PCI 0x00d 762#define AR_SREV_VERSION_5416_PCIE 0x00c 763#define AR_SREV_REVISION_5416_10 0 764#define AR_SREV_REVISION_5416_20 1 765#define AR_SREV_REVISION_5416_22 2 766#define AR_SREV_VERSION_9100 0x014 767#define AR_SREV_VERSION_9160 0x040 768#define AR_SREV_REVISION_9160_10 0 769#define AR_SREV_REVISION_9160_11 1 770#define AR_SREV_VERSION_9280 0x080 771#define AR_SREV_REVISION_9280_10 0 772#define AR_SREV_REVISION_9280_20 1 773#define AR_SREV_REVISION_9280_21 2 774#define AR_SREV_VERSION_9285 0x0c0 775#define AR_SREV_REVISION_9285_10 0 776#define AR_SREV_REVISION_9285_11 1 777#define AR_SREV_REVISION_9285_12 2 778#define AR_SREV_VERSION_9287 0x180 779#define AR_SREV_REVISION_9287_10 0 780#define AR_SREV_REVISION_9287_11 1 781#define AR_SREV_REVISION_9287_12 2 782#define AR_SREV_VERSION_9380 0x1c0 783#define AR_SREV_REVISION_9380_10 0 784#define AR_SREV_REVISION_9380_20 2 785 786/* Bits for AR_AHB_MODE. */ 787#define AR_AHB_EXACT_WR_EN 0x00000000 788#define AR_AHB_BUF_WR_EN 0x00000001 789#define AR_AHB_EXACT_RD_EN 0x00000000 790#define AR_AHB_CACHELINE_RD_EN 0x00000002 791#define AR_AHB_PREFETCH_RD_EN 0x00000004 792#define AR_AHB_PAGE_SIZE_1K 0x00000000 793#define AR_AHB_PAGE_SIZE_2K 0x00000008 794#define AR_AHB_PAGE_SIZE_4K 0x00000010 795#define AR_AHB_CUSTOM_BURST_M 0x000000c0 796#define AR_AHB_CUSTOM_BURST_S 6 797#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 798 799/* Bits for AR_INTR_SYNC_CAUSE. */ 800#define AR_INTR_SYNC_RTC_IRQ 0x00000001 801#define AR_INTR_SYNC_MAC_IRQ 0x00000002 802#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 803#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 804#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 805#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 806#define AR_INTR_SYNC_HOST1_PERR 0x00000040 807#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 808#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 809#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 810#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 811#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 812#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 813#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 814#define AR_INTR_SYNC_PM_ACCESS 0x00004000 815#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 816#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 817#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 818#define AR_INTR_SYNC_ALL 0x0003ffff 819#define AR_INTR_SYNC_GPIO_PIN(i) (1 << (18 + (i))) 820 821#define AR_INTR_SYNC_DEFAULT \ 822 (AR_INTR_SYNC_HOST1_FATAL | \ 823 AR_INTR_SYNC_HOST1_PERR | \ 824 AR_INTR_SYNC_RADM_CPL_EP | \ 825 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 826 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | \ 827 AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 828 AR_INTR_SYNC_RADM_CPL_TIMEOUT | \ 829 AR_INTR_SYNC_LOCAL_TIMEOUT | \ 830 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 831 832/* Bits for AR_INTR_ASYNC_CAUSE. */ 833#define AR_INTR_RTC_IRQ 0x00000001 834#define AR_INTR_MAC_IRQ 0x00000002 835#define AR_INTR_EEP_PROT_ACCESS 0x00000004 836#define AR_INTR_MAC_AWAKE 0x00020000 837#define AR_INTR_MAC_ASLEEP 0x00040000 838#define AR_INTR_GPIO_PIN(i) (1 << (18 + (i))) 839#define AR_INTR_SPURIOUS 0xffffffff 840 841/* Bits for AR_GPIO_OE_OUT. */ 842#define AR_GPIO_OE_OUT_DRV_M 0x00000003 843#define AR_GPIO_OE_OUT_DRV_S 0 844#define AR_GPIO_OE_OUT_DRV_NO 0 845#define AR_GPIO_OE_OUT_DRV_LOW 1 846#define AR_GPIO_OE_OUT_DRV_HI 2 847#define AR_GPIO_OE_OUT_DRV_ALL 3 848 849/* Bits for AR_GPIO_INTR_POL. */ 850#define AR_GPIO_INTR_POL_PIN(i) (1 << (i)) 851 852/* Bits for AR_GPIO_INPUT_EN_VAL. */ 853#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 854#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 855#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 856#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 857#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 858#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 859#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 860#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 861#define AR_GPIO_JTAG_DISABLE 0x00020000 862 863/* Bits for AR_GPIO_INPUT_MUX1. */ 864#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_M 0x00000f00 865#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 866#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_M 0x000f0000 867#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 868 869/* Bits for AR_GPIO_INPUT_MUX2. */ 870#define AR_GPIO_INPUT_MUX2_CLK25_M 0x0000000f 871#define AR_GPIO_INPUT_MUX2_CLK25_S 0 872#define AR_GPIO_INPUT_MUX2_RFSILENT_M 0x000000f0 873#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 874#define AR_GPIO_INPUT_MUX2_RTC_RESET_M 0x00000f00 875#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 876 877/* Bits for AR_GPIO_OUTPUT_MUX[1-3]. */ 878#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 879#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 880#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 881#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 882#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 883#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 884#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 885 886/* Bits for AR_EEPROM_STATUS_DATA. */ 887#define AR_EEPROM_STATUS_DATA_VAL_M 0x0000ffff 888#define AR_EEPROM_STATUS_DATA_VAL_S 0 889#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 890#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 891#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 892#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 893 894/* Bits for AR_PCIE_MSI. */ 895#define AR_PCIE_MSI_ENABLE 0x00000001 896 897/* Bits for AR_RTC_RC. */ 898#define AR_RTC_RC_MAC_WARM 0x00000001 899#define AR_RTC_RC_MAC_COLD 0x00000002 900#define AR_RTC_RC_COLD_RESET 0x00000004 901#define AR_RTC_RC_WARM_RESET 0x00000008 902 903/* Bits for AR_RTC_REG_CONTROL1. */ 904#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 905 906/* Bits for AR_RTC_PLL_CONTROL. */ 907#define AR_RTC_PLL_DIV_M 0x0000001f 908#define AR_RTC_PLL_DIV_S 0 909#define AR_RTC_PLL_DIV2 0x00000020 910#define AR_RTC_PLL_REFDIV_5 0x000000c0 911#define AR_RTC_PLL_CLKSEL_M 0x00000300 912#define AR_RTC_PLL_CLKSEL_S 8 913#define AR_RTC_9160_PLL_DIV_M 0x000003ff 914#define AR_RTC_9160_PLL_DIV_S 0 915#define AR_RTC_9160_PLL_REFDIV_M 0x00003c00 916#define AR_RTC_9160_PLL_REFDIV_S 10 917#define AR_RTC_9160_PLL_CLKSEL_M 0x0000c000 918#define AR_RTC_9160_PLL_CLKSEL_S 14 919 920/* Bits for AR_RTC_RESET. */ 921#define AR_RTC_RESET_EN 0x00000001 922 923/* Bits for AR_RTC_STATUS. */ 924#define AR_RTC_STATUS_M 0x0000000f 925#define AR_RTC_STATUS_S 0 926#define AR_RTC_STATUS_SHUTDOWN 0x00000001 927#define AR_RTC_STATUS_ON 0x00000002 928#define AR_RTC_STATUS_SLEEP 0x00000004 929#define AR_RTC_STATUS_WAKEUP 0x00000008 930 931/* Bits for AR_RTC_SLEEP_CLK. */ 932#define AR_RTC_FORCE_DERIVED_CLK 0x00000002 933#define AR_RTC_FORCE_SWREG_PRD 0x00000004 934 935/* Bits for AR_RTC_FORCE_WAKE. */ 936#define AR_RTC_FORCE_WAKE_EN 0x00000001 937#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 938 939/* Bits for AR_STA_ID1. */ 940#define AR_STA_ID1_SADH_M 0x0000ffff 941#define AR_STA_ID1_SADH_S 0 942#define AR_STA_ID1_STA_AP 0x00010000 943#define AR_STA_ID1_ADHOC 0x00020000 944#define AR_STA_ID1_PWR_SAV 0x00040000 945#define AR_STA_ID1_KSRCHDIS 0x00080000 946#define AR_STA_ID1_PCF 0x00100000 947#define AR_STA_ID1_USE_DEFANT 0x00200000 948#define AR_STA_ID1_DEFANT_UPDATE 0x00400000 949#define AR_STA_ID1_RTS_USE_DEF 0x00800000 950#define AR_STA_ID1_ACKCTS_6MB 0x01000000 951#define AR_STA_ID1_BASE_RATE_11B 0x02000000 952#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 953#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 954#define AR_STA_ID1_KSRCH_MODE 0x10000000 955#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 956#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 957#define AR_STA_ID1_MCAST_KSRCH 0x80000000 958 959/* Bits for AR_BSS_ID1. */ 960#define AR_BSS_ID1_U16_M 0x0000ffff 961#define AR_BSS_ID1_U16_S 0 962#define AR_BSS_ID1_AID_M 0x07ff0000 963#define AR_BSS_ID1_AID_S 16 964 965/* Bits for AR_TIME_OUT. */ 966#define AR_TIME_OUT_ACK_M 0x00003fff 967#define AR_TIME_OUT_ACK_S 0 968#define AR_TIME_OUT_CTS_M 0x3fff0000 969#define AR_TIME_OUT_CTS_S 16 970#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001d56 971 972/* Bits for AR_RSSI_THR. */ 973#define AR_RSSI_THR_M 0x000000ff 974#define AR_RSSI_THR_S 0 975#define AR_RSSI_THR_BM_THR_M 0x0000ff00 976#define AR_RSSI_THR_BM_THR_S 8 977#define AR_RSSI_BCN_WEIGHT_M 0x1f000000 978#define AR_RSSI_BCN_WEIGHT_S 24 979#define AR_RSSI_BCN_RSSI_RST 0x20000000 980 981/* Bits for AR_USEC. */ 982#define AR_USEC_USEC_M 0x0000007f 983#define AR_USEC_USEC_S 0 984#define AR_USEC_TX_LAT_M 0x007fc000 985#define AR_USEC_TX_LAT_S 14 986#define AR_USEC_RX_LAT_M 0x1f800000 987#define AR_USEC_RX_LAT_S 23 988#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 989 990/* Bits for AR_RESET_TSF. */ 991#define AR_RESET_TSF_ONCE 0x01000000 992 993/* Bits for AR_RX_FILTER. */ 994#define AR_RX_FILTER_UCAST 0x00000001 995#define AR_RX_FILTER_MCAST 0x00000002 996#define AR_RX_FILTER_BCAST 0x00000004 997#define AR_RX_FILTER_CONTROL 0x00000008 998#define AR_RX_FILTER_BEACON 0x00000010 999#define AR_RX_FILTER_PROM 0x00000020 1000#define AR_RX_FILTER_PROBEREQ 0x00000080 1001#define AR_RX_FILTER_MYBEACON 0x00000200 1002#define AR_RX_FILTER_COMPR_BAR 0x00000400 1003#define AR_RX_FILTER_PSPOLL 0x00004000 1004 1005/* Bits for AR_DIAG_SW. */ 1006#define AR_DIAG_CACHE_ACK 0x00000001 1007#define AR_DIAG_ACK_DIS 0x00000002 1008#define AR_DIAG_CTS_DIS 0x00000004 1009#define AR_DIAG_ENCRYPT_DIS 0x00000008 1010#define AR_DIAG_DECRYPT_DIS 0x00000010 1011#define AR_DIAG_RX_DIS 0x00000020 1012#define AR_DIAG_LOOP_BACK 0x00000040 1013#define AR_DIAG_CORR_FCS 0x00000080 1014#define AR_DIAG_CHAN_INFO 0x00000100 1015#define AR_DIAG_SCRAM_SEED_M 0x0001fe00 1016#define AR_DIAG_SCRAM_SEED_S 8 /* XXX should be 9? */ 1017#define AR_DIAG_FRAME_NV0 0x00020000 1018#define AR_DIAG_OBS_PT_SEL1_M 0x000c0000 1019#define AR_DIAG_OBS_PT_SEL1_S 18 1020#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 1021#define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1022#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1023#define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1024#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1025#define AR_DIAG_RX_ABORT 0x02000000 1026#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1027#define AR_DIAG_OBS_PT_SEL2 0x08000000 1028#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1029#define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 1030 1031/* Bits for AR_AES_MUTE_MASK0. */ 1032#define AR_AES_MUTE_MASK0_FC_M 0x0000ffff 1033#define AR_AES_MUTE_MASK0_FC_S 0 1034#define AR_AES_MUTE_MASK0_QOS_M 0xffff0000 1035#define AR_AES_MUTE_MASK0_QOS_S 16 1036 1037/* Bits for AR_AES_MUTE_MASK1. */ 1038#define AR_AES_MUTE_MASK1_SEQ_M 0x0000ffff 1039#define AR_AES_MUTE_MASK1_SEQ_S 0 1040#define AR_AES_MUTE_MASK1_FC_MGMT_M 0xffff0000 1041#define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1042#define AR_AES_MUTE_MASK1_FC0_MGMT_M 0x00ff0000 1043#define AR_AES_MUTE_MASK1_FC0_MGMT_S 16 1044#define AR_AES_MUTE_MASK1_FC1_MGMT_M 0xff000000 1045#define AR_AES_MUTE_MASK1_FC1_MGMT_S 24 1046 1047/* Bits for AR_GATED_CLKS. */ 1048#define AR_GATED_CLKS_TX 0x00000002 1049#define AR_GATED_CLKS_RX 0x00000004 1050#define AR_GATED_CLKS_REG 0x00000008 1051 1052/* Bits for AR_OBS_BUS_CTRL. */ 1053#define AR_OBS_BUS_SEL_1 0x00040000 1054#define AR_OBS_BUS_SEL_2 0x00080000 1055#define AR_OBS_BUS_SEL_3 0x000c0000 1056#define AR_OBS_BUS_SEL_4 0x08040000 1057#define AR_OBS_BUS_SEL_5 0x08080000 1058 1059/* Bits for AR_OBS_BUS_1. */ 1060#define AR_OBS_BUS_1_PCU 0x00000001 1061#define AR_OBS_BUS_1_RX_END 0x00000002 1062#define AR_OBS_BUS_1_RX_WEP 0x00000004 1063#define AR_OBS_BUS_1_RX_BEACON 0x00000008 1064#define AR_OBS_BUS_1_RX_FILTER 0x00000010 1065#define AR_OBS_BUS_1_TX_HCF 0x00000020 1066#define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1067#define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1068#define AR_OBS_BUS_1_TX_HOLD 0x00000100 1069#define AR_OBS_BUS_1_TX_FRAME 0x00000200 1070#define AR_OBS_BUS_1_RX_FRAME 0x00000400 1071#define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1072#define AR_OBS_BUS_1_WEP_STATE_M 0x0003f000 1073#define AR_OBS_BUS_1_WEP_STATE_S 12 1074#define AR_OBS_BUS_1_RX_STATE_M 0x01f00000 1075#define AR_OBS_BUS_1_RX_STATE_S 20 1076#define AR_OBS_BUS_1_TX_STATE_M 0x7e000000 1077#define AR_OBS_BUS_1_TX_STATE_S 25 1078 1079/* Bits for AR_SLEEP1. */ 1080#define AR_SLEEP1_ASSUME_DTIM 0x00080000 1081#define AR_SLEEP1_CAB_TIMEOUT_M 0xffe00000 1082#define AR_SLEEP1_CAB_TIMEOUT_S 21 1083/* Default value. */ 1084#define AR_CAB_TIMEOUT_VAL 10 1085 1086/* Bits for AR_SLEEP2. */ 1087#define AR_SLEEP2_BEACON_TIMEOUT_M 0xffe00000 1088#define AR_SLEEP2_BEACON_TIMEOUT_S 21 1089 1090/* Bits for AR_TPC. */ 1091#define AR_TPC_ACK_M 0x0000003f 1092#define AR_TPC_ACK_S 0 1093#define AR_TPC_CTS_M 0x00003f00 1094#define AR_TPC_CTS_S 8 1095#define AR_TPC_CHIRP_M 0x003f0000 1096#define AR_TPC_CHIRP_S 16 1097 1098/* Bits for AR_QUIET1. */ 1099#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1100#define AR_QUIET1_NEXT_QUIET_S 0 1101#define AR_QUIET1_QUIET_ENABLE 0x00010000 1102#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 1103 1104/* Bits for AR_QUIET2. */ 1105#define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1106#define AR_QUIET2_QUIET_PERIOD_S 0 1107#define AR_QUIET2_QUIET_DUR_M 0xffff0000 1108#define AR_QUIET2_QUIET_DUR_S 16 1109 1110/* Bits for AR_TSF_PARM. */ 1111#define AR_TSF_INCREMENT_M 0x000000ff 1112#define AR_TSF_INCREMENT_S 0 1113 1114/* Bits for AR_QOS_NO_ACK. */ 1115#define AR_QOS_NO_ACK_TWO_BIT_M 0x0000000f 1116#define AR_QOS_NO_ACK_TWO_BIT_S 0 1117#define AR_QOS_NO_ACK_BIT_OFF_M 0x0000007f 1118#define AR_QOS_NO_ACK_BIT_OFF_S 4 1119#define AR_QOS_NO_ACK_BYTE_OFF_M 0x00000180 1120#define AR_QOS_NO_ACK_BYTE_OFF_S 7 1121 1122/* Bits for AR_PHY_ERR. */ 1123#define AR_PHY_ERR_DCHIRP 0x00000008 1124#define AR_PHY_ERR_RADAR 0x00000020 1125#define AR_PHY_ERR_OFDM_TIMING 0x00020000 1126#define AR_PHY_ERR_CCK_TIMING 0x02000000 1127 1128/* Bits for AR_PCU_MISC. */ 1129#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 1130#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 1131#define AR_PCU_TX_ADD_TSF 0x00000008 1132#define AR_PCU_CCK_SIFS_MODE 0x00000010 1133#define AR_PCU_RX_ANT_UPDT 0x00000800 1134#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 1135#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 1136#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 1137#define AR_PCU_FORCE_QUIET_COLL 0x00040000 1138#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1139#define AR_PCU_TBTT_PROTECT 0x00200000 1140#define AR_PCU_CLEAR_VMF 0x01000000 1141#define AR_PCU_CLEAR_BA_VALID 0x04000000 1142 1143/* Bits for AR_BT_COEX_MODE. */ 1144#define AR_BT_TIME_EXTEND_M 0x000000ff 1145#define AR_BT_TIME_EXTEND_S 0 1146#define AR_BT_TXSTATE_EXTEND 0x00000100 1147#define AR_BT_TX_FRAME_EXTEND 0x00000200 1148#define AR_BT_MODE_M 0x00000c00 1149#define AR_BT_MODE_S 10 1150#define AR_BT_MODE_LEGACY 0 1151#define AR_BT_MODE_UNSLOTTED 1 1152#define AR_BT_MODE_SLOTTED 2 1153#define AR_BT_MODE_DISABLED 3 1154#define AR_BT_QUIET 0x00001000 1155#define AR_BT_QCU_THRESH_M 0x0001e000 1156#define AR_BT_QCU_THRESH_S 13 1157#define AR_BT_RX_CLEAR_POLARITY 0x00020000 1158#define AR_BT_PRIORITY_TIME_M 0x00fc0000 1159#define AR_BT_PRIORITY_TIME_S 18 1160#define AR_BT_FIRST_SLOT_TIME_M 0xff000000 1161#define AR_BT_FIRST_SLOT_TIME_S 24 1162 1163/* Bits for AR_BT_COEX_WEIGHT. */ 1164#define AR_BTCOEX_BT_WGHT_M 0x0000ffff 1165#define AR_BTCOEX_BT_WGHT_S 0 1166#define AR_STOMP_LOW_BT_WGHT 0xff55 1167#define AR_BTCOEX_WL_WGHT_M 0xffff0000 1168#define AR_BTCOEX_WL_WGHT_S 16 1169#define AR_STOMP_LOW_WL_WGHT 0xaaa8 1170 1171/* Bits for AR_BT_COEX_MODE2. */ 1172#define AR_BT_BCN_MISS_THRESH_M 0x000000ff 1173#define AR_BT_BCN_MISS_THRESH_S 0 1174#define AR_BT_BCN_MISS_CNT_M 0x0000ff00 1175#define AR_BT_BCN_MISS_CNT_S 8 1176#define AR_BT_HOLD_RX_CLEAR 0x00010000 1177#define AR_BT_DISABLE_BT_ANT 0x00100000 1178 1179/* Bits for AR_PCU_TXBUF_CTRL. */ 1180#define AR_PCU_TXBUF_CTRL_SIZE_M 0x000007ff 1181#define AR_PCU_TXBUF_CTRL_SIZE_S 0 1182#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 1792 1183#define AR9285_PCU_TXBUF_CTRL_USABLE_SIZE (1792 / 2) 1184 1185/* Bits for AR_PCU_MISC_MODE2. */ 1186#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 1187#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 1188#define AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX 0x00000008 1189#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 1190#define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 1191#define AR_PCU_MISC_MODE2_MGMT_QOS_M 0x0000ff00 1192#define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 1193#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DUR 0x00010000 1194#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 1195#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 1196#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 1197 1198/* Bits for AR_MAC_PCU_LOGIC_ANALYZER. */ 1199#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1200 1201/* Bits for AR_MAC_PCU_ASYNC_FIFO_REG3. */ 1202#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 1203#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 1204 1205/* Bits for AR_PHY_ERR_[123]. */ 1206#define AR_PHY_ERR_COUNT_M 0x00ffffff 1207#define AR_PHY_ERR_COUNT_S 0 1208 1209/* Bits for AR_TSFOOR_THRESHOLD. */ 1210#define AR_TSFOOR_THRESHOLD_VAL_M 0x0000ffff 1211#define AR_TSFOOR_THRESHOLD_VAL_S 0 1212 1213/* Bit for AR_TXSIFS. */ 1214#define AR_TXSIFS_TIME_M 0x000000ff 1215#define AR_TXSIFS_TIME_S 0 1216#define AR_TXSIFS_TX_LATENCY_M 0x00000f00 1217#define AR_TXSIFS_TX_LATENCY_S 8 1218#define AR_TXSIFS_ACK_SHIFT_M 0x00007000 1219#define AR_TXSIFS_ACK_SHIFT_S 12 1220 1221/* Bits for AR_TXOP_X. */ 1222#define AR_TXOP_X_VAL 0x000000ff 1223 1224/* Bits for AR_TIMER_MODE. */ 1225#define AR_TBTT_TIMER_EN 0x00000001 1226#define AR_DBA_TIMER_EN 0x00000002 1227#define AR_SWBA_TIMER_EN 0x00000004 1228#define AR_HCF_TIMER_EN 0x00000008 1229#define AR_TIM_TIMER_EN 0x00000010 1230#define AR_DTIM_TIMER_EN 0x00000020 1231#define AR_QUIET_TIMER_EN 0x00000040 1232#define AR_NDP_TIMER_EN 0x00000080 1233#define AR_TIMER_OVERFLOW_INDEX_M 0x00000700 1234#define AR_TIMER_OVERFLOW_INDEX_S 8 1235#define AR_TIMER_THRESH_M 0xfffff000 1236#define AR_TIMER_THRESH_S 12 1237 1238/* Bits for AR_SLP32_MODE. */ 1239#define AR_SLP32_HALF_CLK_LATENCY_M 0x000fffff 1240#define AR_SLP32_HALF_CLK_LATENCY_S 0 1241#define AR_SLP32_ENA 0x00100000 1242#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 1243 1244/* Bits for AR_SLP32_WAKE. */ 1245#define AR_SLP32_WAKE_XTL_TIME_M 0x0000ffff 1246#define AR_SLP32_WAKE_XTL_TIME_S 0 1247 1248/* Bits for AR_SLP_MIB_CTRL. */ 1249#define AR_SLP_MIB_CLEAR 0x00000001 1250#define AR_SLP_MIB_PENDING 0x00000002 1251 1252/* Bits for AR_2040_MODE. */ 1253#define AR_2040_JOINED_RX_CLEAR 0x00000001 1254 1255/* Bits for AR_KEYTABLE_TYPE. */ 1256#define AR_KEYTABLE_TYPE_M 0x00000007 1257#define AR_KEYTABLE_TYPE_S 0 1258#define AR_KEYTABLE_TYPE_40 0 1259#define AR_KEYTABLE_TYPE_104 1 1260#define AR_KEYTABLE_TYPE_128 3 1261#define AR_KEYTABLE_TYPE_TKIP 4 1262#define AR_KEYTABLE_TYPE_AES 5 1263#define AR_KEYTABLE_TYPE_CCM 6 1264#define AR_KEYTABLE_TYPE_CLR 7 1265#define AR_KEYTABLE_ANT 0x00000008 1266#define AR_KEYTABLE_VALID 0x00008000 1267 1268 1269#define AR_BASE_PHY_ACTIVE_DELAY 100 1270 1271#define AR_CLOCK_RATE_CCK 22 1272#define AR_CLOCK_RATE_5GHZ_OFDM 40 1273#define AR_CLOCK_RATE_FAST_5GHZ_OFDM 44 1274#define AR_CLOCK_RATE_2GHZ_OFDM 44 1275 1276#define AR_PWR_DECREASE_FOR_2_CHAIN 6 /* 10 * log10(2) * 2 */ 1277#define AR_PWR_DECREASE_FOR_3_CHAIN 9 /* 10 * log10(3) * 2 */ 1278 1279#define AR_SLEEP_SLOP 3 /* TUs */ 1280 1281#define AR_MIN_BEACON_TIMEOUT_VAL 1 1282#define AR_FUDGE 2 1283#define AR_BEACON_DMA_DELAY 2 1284#define AR_SWBA_DELAY 10 1285/* Divides by 1024 (usecs to TU) without doing 64-bit arithmetic. */ 1286#define AR_TSF_TO_TU(hi, lo) ((hi) << 22 | (lo) >> 10) 1287 1288#define AR_KEY_CACHE_SIZE 128 1289#define AR_RSVD_KEYTABLE_ENTRIES 4 1290 1291#define AR_CAL_SAMPLES 64 /* XXX AR9280? */ 1292#define AR_MAX_LOG_CAL 2 /* XXX AR9280? */ 1293 1294/* Maximum number of chains supported by any chipset. */ 1295#define AR_MAX_CHAINS 3 1296 1297/* Default number of key cache entries. */ 1298#define AR_KEYTABLE_SIZE 128 1299 1300/* GPIO pins. */ 1301#define AR_GPIO_WLANACTIVE_PIN 5 1302#define AR_GPIO_BTACTIVE_PIN 6 1303#define AR_GPIO_BTPRIORITY_PIN 7 1304 1305#define AR_SREV_5416(sc) \ 1306 ((sc)->mac_ver == AR_SREV_VERSION_5416_PCI || \ 1307 (sc)->mac_ver == AR_SREV_VERSION_5416_PCIE) 1308#define AR_SREV_5416_20_OR_LATER(sc) \ 1309 ((AR_SREV_5416(sc) && \ 1310 (sc)->mac_rev >= AR_SREV_REVISION_5416_20) || \ 1311 (sc)->mac_ver >= AR_SREV_VERSION_9100) 1312#define AR_SREV_5416_22_OR_LATER(sc) \ 1313 ((AR_SREV_5416(sc) && \ 1314 (sc)->mac_rev >= AR_SREV_REVISION_5416_22) || \ 1315 (sc)->mac_ver >= AR_SREV_VERSION_9100) 1316 1317#define AR_SREV_9160(sc) \ 1318 ((sc)->mac_ver == AR_SREV_VERSION_9160) 1319#define AR_SREV_9160_10_OR_LATER(sc) \ 1320 ((sc)->mac_ver >= AR_SREV_VERSION_9160) 1321#define AR_SREV_9160_11(sc) \ 1322 (AR_SREV_9160(sc) && \ 1323 (sc)->mac_rev == AR_SREV_REVISION_9160_11) 1324 1325#define AR_SREV_9280(sc) \ 1326 ((sc)->mac_ver == AR_SREV_VERSION_9280) 1327#define AR_SREV_9280_10_OR_LATER(sc) \ 1328 ((sc)->mac_ver >= AR_SREV_VERSION_9280) 1329#define AR_SREV_9280_10(sc) \ 1330 (AR_SREV_9280(sc) && \ 1331 (sc)->mac_rev == AR_SREV_REVISION_9280_10) 1332#define AR_SREV_9280_20(sc) \ 1333 (AR_SREV_9280(sc) && \ 1334 (sc)->mac_rev >= AR_SREV_REVISION_9280_20) 1335#define AR_SREV_9280_20_OR_LATER(sc) \ 1336 ((sc)->mac_ver > AR_SREV_VERSION_9280 || \ 1337 (AR_SREV_9280(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9280_20)) 1338 1339#define AR_SREV_9285(sc) \ 1340 ((sc)->mac_ver == AR_SREV_VERSION_9285) 1341#define AR_SREV_9285_10_OR_LATER(sc) \ 1342 ((sc)->mac_ver >= AR_SREV_VERSION_9285) 1343#define AR_SREV_9285_11(sc) \ 1344 (AR_SREV_9285(sc) && \ 1345 (sc)->mac_rev == AR_SREV_REVISION_9285_11) 1346#define AR_SREV_9285_11_OR_LATER(sc) \ 1347 ((sc)->mac_ver > AR_SREV_VERSION_9285 || \ 1348 (AR_SREV_9285(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9285_11)) 1349#define AR_SREV_9285_12(sc) \ 1350 (AR_SREV_9285(sc) && \ 1351 ((sc)->mac_rev == AR_SREV_REVISION_9285_12)) 1352#define AR_SREV_9285_12_OR_LATER(sc) \ 1353 ((sc)->mac_ver > AR_SREV_VERSION_9285 || \ 1354 (AR_SREV_9285(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9285_12)) 1355 1356#define AR_SREV_9287(sc) \ 1357 ((sc)->mac_ver == AR_SREV_VERSION_9287) 1358#define AR_SREV_9287_10_OR_LATER(sc) \ 1359 ((sc)->mac_ver >= AR_SREV_VERSION_9287) 1360#define AR_SREV_9287_10(sc) \ 1361 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 1362 (sc)->mac_rev == AR_SREV_REVISION_9287_10) 1363#define AR_SREV_9287_11(sc) \ 1364 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 1365 (sc)->mac_rev == AR_SREV_REVISION_9287_11) 1366#define AR_SREV_9287_11_OR_LATER(sc) \ 1367 ((sc)->mac_ver > AR_SREV_VERSION_9287 || \ 1368 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_11)) 1369#define AR_SREV_9287_12(sc) \ 1370 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 1371 (sc)->mac_rev == AR_SREV_REVISION_9287_12) 1372#define AR_SREV_9287_12_OR_LATER(sc) \ 1373 ((sc)->mac_ver > AR_SREV_VERSION_9287 || \ 1374 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_12)) 1375 1376#define AR_SREV_9380(sc) \ 1377 ((sc)->mac_ver == AR_SREV_VERSION_9380) 1378#define AR_SREV_9380_10_OR_LATER(sc) \ 1379 ((sc)->mac_ver >= AR_SREV_VERSION_9380) 1380#define AR_SREV_9380_20(sc) \ 1381 (AR_SREV_9380(sc) && \ 1382 (sc)->mac_rev == AR_SREV_REVISION_9380_20) 1383#define AR_SREV_9380_20_OR_LATER(sc) \ 1384 ((sc)->mac_ver > AR_SREV_VERSION_9380 || \ 1385 (AR_SREV_9380(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9380_20)) 1386 1387#define AR_SINGLE_CHIP(sc) AR_SREV_9280_10_OR_LATER(sc) 1388 1389#define AR_RADIO_SREV_MAJOR 0xf0 1390#define AR_RAD5133_SREV_MAJOR 0xc0 1391#define AR_RAD2133_SREV_MAJOR 0xd0 1392#define AR_RAD5122_SREV_MAJOR 0xe0 1393#define AR_RAD2122_SREV_MAJOR 0xf0 1394 1395#define AR_BCHAN_UNUSED 0xff 1396#define AR_PD_GAINS_IN_MASK 4 /* NB: Max for all chips. */ 1397#define AR_MAX_RATE_POWER 63 1398 1399#define AR_HT40_POWER_INC_FOR_PDADC 2 1400#define AR_PWR_TABLE_OFFSET_DB (-5) 1401#define AR9280_TX_GAIN_TABLE_SIZE 22 1402 1403#define AR_BASE_FREQ_2GHZ 2300 1404#define AR_BASE_FREQ_5GHZ 4900 1405 1406#define AR_SD_NO_CTL 0xe0 1407#define AR_NO_CTL 0xff 1408#define AR_CTL_MODE_M 0x07 1409#define AR_CTL_MODE_S 0 1410#define AR_CTL_11A 0 1411#define AR_CTL_11B 1 1412#define AR_CTL_11G 2 1413#define AR_CTL_2GHT20 5 1414#define AR_CTL_5GHT20 6 1415#define AR_CTL_2GHT40 7 1416#define AR_CTL_5GHT40 8 1417 1418/* 1419 * Serializer/Deserializer programming for non-PCIe devices. 1420 */ 1421static const uint32_t ar_nonpcie_serdes[] = { 1422 0x9248fc00, 1423 0x24924924, 1424 0x28000029, 1425 0x57160824, 1426 0x25980579, 1427 0x00000000, 1428 0x1aaabe40, 1429 0xbe105554, 1430 0x000e1007 1431}; 1432 1433/* 1434 * Macros to access registers. 1435 */ 1436#define AR_READ(sc, reg) \ 1437 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1438 1439#define AR_WRITE(sc, reg, val) \ 1440 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1441 1442#define AR_SETBITS(sc, reg, mask) \ 1443 AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask)) 1444 1445#define AR_CLRBITS(sc, reg, mask) \ 1446 AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask)) 1447 1448/* 1449 * Macros to access subfields in registers. 1450 */ 1451/* Mask and Shift (getter). */ 1452#define MS(val, field) \ 1453 (((val) & field##_M) >> field##_S) 1454 1455/* Shift and Mask (setter). */ 1456#define SM(field, val) \ 1457 (((val) << field##_S) & field##_M) 1458 1459/* Rewrite. */ 1460#define RW(var, field, val) \ 1461 (((var) & ~field##_M) | SM(field, val)) 1462