1/* $OpenBSD: athnreg.h,v 1.25 2020/04/28 06:58:09 stsp Exp $ */ 2 3/*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2009 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * MAC registers. 22 */ 23#define AR_CR 0x0008 24#define AR_RXDP 0x000c 25#define AR_CFG 0x0014 26#define AR_RXBP_THRESH 0x0018 27#define AR_MIRT 0x0020 28#define AR_IER 0x0024 29#define AR_TIMT 0x0028 30#define AR_RIMT 0x002c 31#define AR_TXCFG 0x0030 32#define AR_RXCFG 0x0034 33#define AR_MIBC 0x0040 34#define AR_TOPS 0x0044 35#define AR_RXNPTO 0x0048 36#define AR_TXNPTO 0x004c 37#define AR_RPGTO 0x0050 38#define AR_RPCNT 0x0054 39#define AR_MACMISC 0x0058 40#define AR_DATABUF_SIZE 0x0060 41#define AR_GTXTO 0x0064 42#define AR_GTTM 0x0068 43#define AR_CST 0x006c 44#define AR_HP_RXDP 0x0074 45#define AR_LP_RXDP 0x0078 46#define AR_ISR 0x0080 47#define AR_ISR_S0 0x0084 48#define AR_ISR_S1 0x0088 49#define AR_ISR_S2 0x008c 50#define AR_ISR_S3 0x0090 51#define AR_ISR_S4 0x0094 52#define AR_ISR_S5 0x0098 53#define AR_IMR 0x00a0 54#define AR_IMR_S0 0x00a4 55#define AR_IMR_S1 0x00a8 56#define AR_IMR_S2 0x00ac 57#define AR_IMR_S3 0x00b0 58#define AR_IMR_S4 0x00b4 59#define AR_IMR_S5 0x00b8 60#define AR_ISR_RAC 0x00c0 61#define AR_ISR_S0_S 0x00c4 62#define AR_ISR_S1_S 0x00c8 63#define AR_DMADBG(i) (0x00e0 + (i) * 4) 64#define AR_QTXDP(i) (0x0800 + (i) * 4) 65#define AR_Q_STATUS_RING_START 0x0830 66#define AR_Q_STATUS_RING_END 0x0834 67#define AR_Q_TXE 0x0840 68#define AR_Q_TXD 0x0880 69#define AR_QCBRCFG(i) (0x08c0 + (i) * 4) 70#define AR_QRDYTIMECFG(i) (0x0900 + (i) * 4) 71#define AR_Q_ONESHOTARM_SC 0x0940 72#define AR_Q_ONESHOTARM_CC 0x0980 73#define AR_QMISC(i) (0x09c0 + (i) * 4) 74#define AR_QSTS(i) (0x0a00 + (i) * 4) 75#define AR_Q_RDYTIMESHDN 0x0a40 76#define AR_Q_DESC_CRCCHK 0x0a44 77#define AR_DQCUMASK(i) (0x1000 + (i) * 4) 78#define AR_D_GBL_IFS_SIFS 0x1030 79#define AR_D_TXBLK_CMD 0x1038 80#define AR_DLCL_IFS(i) (0x1040 + (i) * 4) 81#define AR_D_GBL_IFS_SLOT 0x1070 82#define AR_DRETRY_LIMIT(i) (0x1080 + (i) * 4) 83#define AR_D_GBL_IFS_EIFS 0x10b0 84#define AR_DCHNTIME(i) (0x10c0 + (i) * 4) 85#define AR_D_GBL_IFS_MISC 0x10f0 86#define AR_DMISC(i) (0x1100 + (i) * 4) 87#define AR_D_SEQNUM 0x1140 88#define AR_D_FPCTL 0x1230 89#define AR_D_TXPSE 0x1270 90#define AR_D_TXSLOTMASK 0x12f0 91#define AR_MAC_SLEEP 0x1f00 92#define AR_CFG_LED 0x1f04 93#define AR_EEPROM_OFFSET(i) (0x2000 + (i) * 4) 94#define AR_RC 0x4000 95#define AR_WA 0x4004 96#define AR_PM_STATE 0x4008 97#define AR_PCIE_PM_CTRL 0x4014 98#define AR_HOST_TIMEOUT 0x4018 99#define AR_EEPROM 0x401c 100#define AR_SREV 0x4020 101#define AR_AHB_MODE 0x4024 102#define AR_INTR_SYNC_CAUSE 0x4028 103#define AR_INTR_SYNC_ENABLE 0x402c 104#define AR_INTR_ASYNC_MASK 0x4030 105#define AR_INTR_SYNC_MASK 0x4034 106#define AR_INTR_ASYNC_CAUSE 0x4038 107#define AR_INTR_ASYNC_ENABLE 0x403c 108#define AR_PCIE_SERDES 0x4040 109#define AR_PCIE_SERDES2 0x4044 110#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4 111#define AR_INTR_PRIO_ASYNC_MASK 0x40c8 112#define AR_INTR_PRIO_SYNC_MASK 0x40cc 113#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4 114#define AR_RTC_RC 0x7000 115#define AR_RTC_XTAL_CONTROL 0x7004 116#define AR_RTC_REG_CONTROL0 0x7008 117#define AR_RTC_REG_CONTROL1 0x700c 118#define AR_RTC_PLL_CONTROL 0x7014 119#define AR_RTC_PLL_CONTROL2 0x703c 120#define AR_RTC_RESET 0x7040 121#define AR_RTC_STATUS 0x7044 122#define AR_RTC_SLEEP_CLK 0x7048 123#define AR_RTC_FORCE_WAKE 0x704c 124#define AR_RTC_INTR_CAUSE 0x7050 125#define AR_RTC_INTR_ENABLE 0x7054 126#define AR_RTC_INTR_MASK 0x7058 127#define AR_STA_ID0 0x8000 128#define AR_STA_ID1 0x8004 129#define AR_BSS_ID0 0x8008 130#define AR_BSS_ID1 0x800c 131#define AR_BCN_RSSI_AVE 0x8010 132#define AR_TIME_OUT 0x8014 133#define AR_RSSI_THR 0x8018 134#define AR_USEC 0x801c 135#define AR_RESET_TSF 0x8020 136#define AR_MAX_CFP_DUR 0x8038 137#define AR_RX_FILTER 0x803c 138#define AR_MCAST_FIL0 0x8040 139#define AR_MCAST_FIL1 0x8044 140#define AR_DIAG_SW 0x8048 141#define AR_TSF_L32 0x804c 142#define AR_TSF_U32 0x8050 143#define AR_TST_ADDAC 0x8054 144#define AR_DEF_ANTENNA 0x8058 145#define AR_AES_MUTE_MASK0 0x805c 146#define AR_AES_MUTE_MASK1 0x8060 147#define AR_GATED_CLKS 0x8064 148#define AR_OBS_BUS_CTRL 0x8068 149#define AR_OBS_BUS_1 0x806c 150#define AR_LAST_TSTP 0x8080 151#define AR_NAV 0x8084 152#define AR_RTS_OK 0x8088 153#define AR_RTS_FAIL 0x808c 154#define AR_ACK_FAIL 0x8090 155#define AR_FCS_FAIL 0x8094 156#define AR_BEACON_CNT 0x8098 157#define AR_SLEEP1 0x80d4 158#define AR_SLEEP2 0x80d8 159#define AR_BSSMSKL 0x80e0 160#define AR_BSSMSKU 0x80e4 161#define AR_TPC 0x80e8 162#define AR_TFCNT 0x80ec 163#define AR_RFCNT 0x80f0 164#define AR_RCCNT 0x80f4 165#define AR_CCCNT 0x80f8 166#define AR_QUIET1 0x80fc 167#define AR_QUIET2 0x8100 168#define AR_TSF_PARM 0x8104 169#define AR_QOS_NO_ACK 0x8108 170#define AR_PHY_ERR 0x810c 171#define AR_RXFIFO_CFG 0x8114 172#define AR_MIC_QOS_CONTROL 0x8118 173#define AR_MIC_QOS_SELECT 0x811c 174#define AR_PCU_MISC 0x8120 175#define AR_FILT_OFDM 0x8124 176#define AR_FILT_CCK 0x8128 177#define AR_PHY_ERR_1 0x812c 178#define AR_PHY_ERR_MASK_1 0x8130 179#define AR_PHY_ERR_2 0x8134 180#define AR_PHY_ERR_MASK_2 0x8138 181#define AR_TSFOOR_THRESHOLD 0x813c 182#define AR_PHY_ERR_EIFS_MASK 0x8144 183#define AR_PHY_ERR_3 0x8168 184#define AR_PHY_ERR_MASK_3 0x816c 185#define AR_BT_COEX_MODE 0x8170 186#define AR_BT_COEX_WEIGHT 0x8174 187#define AR_BT_COEX_MODE2 0x817c 188#define AR_NEXT_NDP2_TIMER(i) (0x8180 + (i) * 4) 189#define AR_NDP2_PERIOD(i) (0x81a0 + (i) * 4) 190#define AR_NDP2_TIMER_MODE 0x81c0 191#define AR_TXSIFS 0x81d0 192#define AR_TXOP_X 0x81ec 193#define AR_TXOP_0_3 0x81f0 194#define AR_TXOP_4_7 0x81f4 195#define AR_TXOP_8_11 0x81f8 196#define AR_TXOP_12_15 0x81fc 197#define AR_GEN_TIMER(i) (0x8200 + (i) * 4) 198#define AR_NEXT_TBTT_TIMER AR_GEN_TIMER(0) 199#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMER(1) 200#define AR_NEXT_CFP AR_GEN_TIMER(2) 201#define AR_NEXT_HCF AR_GEN_TIMER(3) 202#define AR_NEXT_TIM AR_GEN_TIMER(4) 203#define AR_NEXT_DTIM AR_GEN_TIMER(5) 204#define AR_NEXT_QUIET_TIMER AR_GEN_TIMER(6) 205#define AR_NEXT_NDP_TIMER AR_GEN_TIMER(7) 206#define AR_BEACON_PERIOD AR_GEN_TIMER(8) 207#define AR_DMA_BEACON_PERIOD AR_GEN_TIMER(9) 208#define AR_SWBA_PERIOD AR_GEN_TIMER(10) 209#define AR_HCF_PERIOD AR_GEN_TIMER(11) 210#define AR_TIM_PERIOD AR_GEN_TIMER(12) 211#define AR_DTIM_PERIOD AR_GEN_TIMER(13) 212#define AR_QUIET_PERIOD AR_GEN_TIMER(14) 213#define AR_NDP_PERIOD AR_GEN_TIMER(15) 214#define AR_TIMER_MODE 0x8240 215#define AR_SLP32_MODE 0x8244 216#define AR_SLP32_WAKE 0x8248 217#define AR_SLP32_INC 0x824c 218#define AR_SLP_CNT 0x8250 219#define AR_SLP_CYCLE_CNT 0x8254 220#define AR_SLP_MIB_CTRL 0x8258 221#define AR_WOW_PATTERN_REG 0x825c 222#define AR_WOW_COUNT_REG 0x8260 223#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 224#define AR_WOW_BCN_EN_REG 0x8270 225#define AR_WOW_BCN_TIMO_REG 0x8274 226#define AR_WOW_KEEP_ALIVE_TIMO_REG 0x8278 227#define AR_WOW_KEEP_ALIVE_REG 0x827c 228#define AR_WOW_US_SCALAR_REG 0x8284 229#define AR_WOW_KEEP_ALIVE_DELAY_REG 0x8288 230#define AR_WOW_PATTERN_MATCH_REG 0x828c 231#define AR_WOW_PATTERN_OFF1_REG 0x8290 232#define AR_WOW_PATTERN_OFF2_REG 0x8294 233#define AR_WOW_EXACT_REG 0x829c 234#define AR_2040_MODE 0x8318 235#define AR_EXTRCCNT 0x8328 236#define AR_PCU_BA_BAR_CTRL 0x8330 237#define AR_SELFGEN_MASK 0x832c 238#define AR_PCU_TXBUF_CTRL 0x8340 239#define AR_PCU_MISC_MODE2 0x8344 240#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 241#define AR_WOW_LENGTH1_REG 0x8360 242#define AR_WOW_LENGTH2_REG 0x8364 243#define AR_WOW_PATTERN_MATCH_LT_256B 0x8368 244#define AR_RATE_DURATION(i) (0x8700 + (i) * 4) 245#define AR_KEYTABLE(i) (0x8800 + (i) * 32) 246#define AR_KEYTABLE_KEY0(i) (AR_KEYTABLE(i) + 0) 247#define AR_KEYTABLE_KEY1(i) (AR_KEYTABLE(i) + 4) 248#define AR_KEYTABLE_KEY2(i) (AR_KEYTABLE(i) + 8) 249#define AR_KEYTABLE_KEY3(i) (AR_KEYTABLE(i) + 12) 250#define AR_KEYTABLE_KEY4(i) (AR_KEYTABLE(i) + 16) 251#define AR_KEYTABLE_TYPE(i) (AR_KEYTABLE(i) + 20) 252#define AR_KEYTABLE_MAC0(i) (AR_KEYTABLE(i) + 24) 253#define AR_KEYTABLE_MAC1(i) (AR_KEYTABLE(i) + 28) 254 255 256/* Bits for AR_CR. */ 257#define AR_CR_RXE (AR_SREV_9380_20_OR_LATER(sc) ? 0x000c : 0x0004) 258#define AR_CR_RXD 0x00000020 259#define AR_CR_SWI 0x00000040 260 261/* Bits for AR_CFG. */ 262#define AR_CFG_SWTD 0x00000001 263#define AR_CFG_SWTB 0x00000002 264#define AR_CFG_SWRD 0x00000004 265#define AR_CFG_SWRB 0x00000008 266#define AR_CFG_SWRG 0x00000010 267#define AR_CFG_AP_ADHOC_INDICATION 0x00000020 268#define AR_CFG_PHOK 0x00000100 269#define AR_CFG_EEBS 0x00000200 270#define AR_CFG_CLK_GATE_DIS 0x00000400 271#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M 0x00060000 272#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 273 274/* Bits for AR_RXBP_THRESH. */ 275#define AR_RXBP_THRESH_HP_M 0x0000000f 276#define AR_RXBP_THRESH_HP_S 0 277#define AR_RXBP_THRESH_LP_M 0x00003f00 278#define AR_RXBP_THRESH_LP_S 8 279 280/* Bits for AR_IER. */ 281#define AR_IER_ENABLE 0x00000001 282 283/* Bits for AR_MIRT. */ 284#define AR_MIRT_RATE_THRES_M 0x0000ffff 285#define AR_MIRT_RATE_THRES_S 0 286 287/* Bits for AR_TIMT. */ 288#define AR_TIMT_LAST_M 0x0000ffff 289#define AR_TIMT_LAST_S 0 290#define AR_TIMT_FIRST_M 0xffff0000 291#define AR_TIMT_FIRST_S 16 292 293/* Bits for AR_RIMT. */ 294#define AR_RIMT_LAST_M 0x0000ffff 295#define AR_RIMT_LAST_S 0 296#define AR_RIMT_FIRST_M 0xffff0000 297#define AR_RIMT_FIRST_S 16 298 299/* Bits for AR_[TR]XCFG_DMASZ fields. */ 300#define AR_DMASZ_4B 0 301#define AR_DMASZ_8B 1 302#define AR_DMASZ_16B 2 303#define AR_DMASZ_32B 3 304#define AR_DMASZ_64B 4 305#define AR_DMASZ_128B 5 306#define AR_DMASZ_256B 6 307#define AR_DMASZ_512B 7 308 309/* Bits for AR_TXCFG. */ 310#define AR_TXCFG_DMASZ_M 0x00000007 311#define AR_TXCFG_DMASZ_S 0 312#define AR_TXCFG_FTRIG_M 0x000003f0 313#define AR_TXCFG_FTRIG_S 4 314#define AR_TXCFG_FTRIG_IMMED ( 0 / 64) 315#define AR_TXCFG_FTRIG_64B ( 64 / 64) 316#define AR_TXCFG_FTRIG_128B (128 / 64) 317#define AR_TXCFG_FTRIG_192B (192 / 64) 318#define AR_TXCFG_FTRIG_256B (256 / 64) 319#define AR_TXCFG_FTRIG_512B (512 / 64) 320#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 321 322/* Bits for AR_RXCFG. */ 323#define AR_RXCFG_DMASZ_M 0x00000007 324#define AR_RXCFG_DMASZ_S 0 325#define AR_RXCFG_CHIRP 0x00000008 326#define AR_RXCFG_ZLFDMA 0x00000010 327 328/* Bits for AR_MIBC. */ 329#define AR_MIBC_COW 0x00000001 330#define AR_MIBC_FMC 0x00000002 331#define AR_MIBC_CMC 0x00000004 332#define AR_MIBC_MCS 0x00000008 333 334/* Bits for AR_TOPS. */ 335#define AR_TOPS_MASK 0x0000ffff 336 337/* Bits for AR_RXNPTO. */ 338#define AR_RXNPTO_MASK 0x000003ff 339 340/* Bits for AR_TXNPTO. */ 341#define AR_TXNPTO_MASK 0x000003ff 342#define AR_TXNPTO_QCU_MASK 0x000ffc00 343 344/* Bits for AR_RPGTO. */ 345#define AR_RPGTO_MASK 0x000003ff 346 347/* Bits for AR_RPCNT. */ 348#define AR_RPCNT_MASK 0x0000001f 349 350/* Bits for AR_MACMISC. */ 351#define AR_MACMISC_PCI_EXT_FORCE 0x00000010 352#define AR_MACMISC_DMA_OBS_M 0x000001e0 353#define AR_MACMISC_DMA_OBS_S 5 354#define AR_MACMISC_MISC_OBS_M 0x00000e00 355#define AR_MACMISC_MISC_OBS_S 9 356#define AR_MACMISC_MISC_OBS_BUS_LSB_M 0x00007000 357#define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 358#define AR_MACMISC_MISC_OBS_BUS_MSB_M 0x00038000 359#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 360 361/* Bits for AR_GTXTO. */ 362#define AR_GTXTO_TIMEOUT_COUNTER_M 0x0000ffff 363#define AR_GTXTO_TIMEOUT_COUNTER_S 0 364#define AR_GTXTO_TIMEOUT_LIMIT_M 0xffff0000 365#define AR_GTXTO_TIMEOUT_LIMIT_S 16 366 367/* Bits for AR_GTTM. */ 368#define AR_GTTM_USEC 0x00000001 369#define AR_GTTM_IGNORE_IDLE 0x00000002 370#define AR_GTTM_RESET_IDLE 0x00000004 371#define AR_GTTM_CST_USEC 0x00000008 372 373/* Bits for AR_CST. */ 374#define AR_CST_TIMEOUT_COUNTER_M 0x0000ffff 375#define AR_CST_TIMEOUT_COUNTER_S 0 376#define AR_CST_TIMEOUT_LIMIT_M 0xffff0000 377#define AR_CST_TIMEOUT_LIMIT_S 16 378 379/* Bits for AR_ISR. */ 380#define AR_ISR_RXOK 0x00000001 381#define AR_ISR_HP_RXOK 0x00000001 382#define AR_ISR_RXDESC 0x00000002 383#define AR_ISR_LP_RXOK 0x00000002 384#define AR_ISR_RXERR 0x00000004 385#define AR_ISR_RXNOPKT 0x00000008 386#define AR_ISR_RXEOL 0x00000010 387#define AR_ISR_RXORN 0x00000020 388#define AR_ISR_TXOK 0x00000040 389#define AR_ISR_TXDESC 0x00000080 390#define AR_ISR_TXERR 0x00000100 391#define AR_ISR_TXNOPKT 0x00000200 392#define AR_ISR_TXEOL 0x00000400 393#define AR_ISR_TXURN 0x00000800 394#define AR_ISR_MIB 0x00001000 395#define AR_ISR_SWI 0x00002000 396#define AR_ISR_RXPHY 0x00004000 397#define AR_ISR_RXKCM 0x00008000 398#define AR_ISR_SWBA 0x00010000 399#define AR_ISR_BRSSI 0x00020000 400#define AR_ISR_BMISS 0x00040000 401#define AR_ISR_TXMINTR 0x00080000 402#define AR_ISR_BNR 0x00100000 403#define AR_ISR_RXCHIRP 0x00200000 404#define AR_ISR_BCNMISC 0x00800000 405#define AR_ISR_TIM 0x00800000 406#define AR_ISR_RXMINTR 0x01000000 407#define AR_ISR_QCBROVF 0x02000000 408#define AR_ISR_QCBRURN 0x04000000 409#define AR_ISR_QTRIG 0x08000000 410#define AR_ISR_GENTMR 0x10000000 411#define AR_ISR_TXINTM 0x40000000 412#define AR_ISR_RXINTM 0x80000000 413 414/* Bits for AR_ISR_S0. */ 415#define AR_ISR_S0_QCU_TXOK_M 0x000003ff 416#define AR_ISR_S0_QCU_TXOK_S 0 417#define AR_ISR_S0_QCU_TXDESC_M 0x03ff0000 418#define AR_ISR_S0_QCU_TXDESC_S 16 419 420/* Bits for AR_ISR_S1. */ 421#define AR_ISR_S1_QCU_TXERR_M 0x000003ff 422#define AR_ISR_S1_QCU_TXERR_S 0 423#define AR_ISR_S1_QCU_TXEOL_M 0x03ff0000 424#define AR_ISR_S1_QCU_TXEOL_S 16 425 426/* Bits for AR_ISR_S2. */ 427#define AR_ISR_S2_QCU_TXURN_M 0x000003ff 428#define AR_ISR_S2_QCU_TXURN_S 0 429#define AR_ISR_S2_BB_WATCHDOG 0x00010000 430#define AR_ISR_S2_CST 0x00400000 431#define AR_ISR_S2_GTT 0x00800000 432#define AR_ISR_S2_TIM 0x01000000 433#define AR_ISR_S2_CABEND 0x02000000 434#define AR_ISR_S2_DTIMSYNC 0x04000000 435#define AR_ISR_S2_BCNTO 0x08000000 436#define AR_ISR_S2_CABTO 0x10000000 437#define AR_ISR_S2_DTIM 0x20000000 438#define AR_ISR_S2_TSFOOR 0x40000000 439#define AR_ISR_S2_TBTT_TIME 0x80000000 440 441/* Bits for AR_ISR_S3. */ 442#define AR_ISR_S3_QCU_QCBROVF_M 0x000003ff 443#define AR_ISR_S3_QCU_QCBROVF_S 0 444#define AR_ISR_S3_QCU_QCBRURN_M 0x03ff0000 445#define AR_ISR_S3_QCU_QCBRURN_S 0 446 447/* Bits for AR_ISR_S4. */ 448#define AR_ISR_S4_QCU_QTRIG_M 0x000003ff 449#define AR_ISR_S4_QCU_QTRIG_S 0 450 451/* Bits for AR_ISR_S5. */ 452#define AR_ISR_S5_TIMER_TRIG_M 0x000000ff 453#define AR_ISR_S5_TIMER_TRIG_S 0 454#define AR_ISR_S5_TIMER_THRESH_M 0x0007fe00 455#define AR_ISR_S5_TIMER_THRESH_S 9 456#define AR_ISR_S5_TIM_TIMER 0x00000010 457#define AR_ISR_S5_DTIM_TIMER 0x00000020 458#define AR_ISR_S5_GENTIMER_TRIG_M 0x0000ff80 459#define AR_ISR_S5_GENTIMER_TRIG_S 0 460#define AR_ISR_S5_GENTIMER_THRESH_M 0xff800000 461#define AR_ISR_S5_GENTIMER_THRESH_S 16 462 463/* Bits for AR_IMR. */ 464#define AR_IMR_RXOK 0x00000001 465#define AR_IMR_HP_RXOK 0x00000001 466#define AR_IMR_RXDESC 0x00000002 467#define AR_IMR_LP_RXOK 0x00000002 468#define AR_IMR_RXERR 0x00000004 469#define AR_IMR_RXNOPKT 0x00000008 470#define AR_IMR_RXEOL 0x00000010 471#define AR_IMR_RXORN 0x00000020 472#define AR_IMR_TXOK 0x00000040 473#define AR_IMR_TXDESC 0x00000080 474#define AR_IMR_TXERR 0x00000100 475#define AR_IMR_TXNOPKT 0x00000200 476#define AR_IMR_TXEOL 0x00000400 477#define AR_IMR_TXURN 0x00000800 478#define AR_IMR_MIB 0x00001000 479#define AR_IMR_SWI 0x00002000 480#define AR_IMR_RXPHY 0x00004000 481#define AR_IMR_RXKCM 0x00008000 482#define AR_IMR_SWBA 0x00010000 483#define AR_IMR_BRSSI 0x00020000 484#define AR_IMR_BMISS 0x00040000 485#define AR_IMR_TXMINTR 0x00080000 486#define AR_IMR_BNR 0x00100000 487#define AR_IMR_RXCHIRP 0x00200000 488#define AR_IMR_BCNMISC 0x00800000 489#define AR_IMR_TIM 0x00800000 490#define AR_IMR_RXMINTR 0x01000000 491#define AR_IMR_QCBROVF 0x02000000 492#define AR_IMR_QCBRURN 0x04000000 493#define AR_IMR_QTRIG 0x08000000 494#define AR_IMR_GENTMR 0x10000000 495#define AR_IMR_TXINTM 0x40000000 496#define AR_IMR_RXINTM 0x80000000 497 498#define AR_IMR_DEFAULT \ 499 (AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR | \ 500 AR_IMR_RXORN | AR_IMR_BCNMISC | AR_IMR_RXINTM | \ 501 AR_IMR_RXMINTR | AR_IMR_TXOK) 502#define AR_IMR_HOSTAP (AR_IMR_DEFAULT | AR_IMR_MIB) 503 504/* Bits for AR_IMR_S0. */ 505#define AR_IMR_S0_QCU_TXOK(qid) (1 << (qid)) 506#define AR_IMR_S0_QCU_TXDESC(qid) (1 << (16 + (qid))) 507 508/* Bits for AR_IMR_S1. */ 509#define AR_IMR_S1_QCU_TXERR(qid) (1 << (qid)) 510#define AR_IMR_S1_QCU_TXEOL(qid) (1 << (16 + (qid))) 511 512/* Bits for AR_IMR_S2. */ 513#define AR_IMR_S2_QCU_TXURN(qid) (1 << (qid)) 514#define AR_IMR_S2_CST 0x00400000 515#define AR_IMR_S2_GTT 0x00800000 516#define AR_IMR_S2_TIM 0x01000000 517#define AR_IMR_S2_CABEND 0x02000000 518#define AR_IMR_S2_DTIMSYNC 0x04000000 519#define AR_IMR_S2_BCNTO 0x08000000 520#define AR_IMR_S2_CABTO 0x10000000 521#define AR_IMR_S2_DTIM 0x20000000 522#define AR_IMR_S2_TSFOOR 0x40000000 523 524/* Bits for AR_IMR_S3. */ 525#define AR_IMR_S3_QCU_QCBROVF(qid) (1 << (qid)) 526#define AR_IMR_S3_QCU_QCBRURN(qid) (1 << (16 + (qid))) 527 528/* Bits for AR_IMR_S4. */ 529#define AR_IMR_S4_QCU_QTRIG(qid) (1 << (qid)) 530 531/* Bits for AR_IMR_S5. */ 532#define AR_IMR_S5_TIM_TIMER 0x00000010 533#define AR_IMR_S5_DTIM_TIMER 0x00000020 534#define AR_IMR_S5_TIMER_TRIG_M 0x000000ff 535#define AR_IMR_S5_TIMER_TRIG_S 0 536#define AR_IMR_S5_TIMER_THRESH_M 0x0000ff00 537#define AR_IMR_S5_TIMER_THRESH_S 0 538 539#define AR_NUM_QCU 10 540#define AR_QCU(x) (1 << (x)) 541 542/* Bits for AR_Q_TXE. */ 543#define AR_Q_TXE_M 0x000003ff 544#define AR_Q_TXE_S 0 545 546/* Bits for AR_Q_TXD. */ 547#define AR_Q_TXD_M 0x000003ff 548#define AR_Q_TXD_S 0 549 550/* Bits for AR_QCBRCFG_*. */ 551#define AR_Q_CBRCFG_INTERVAL_M 0x00ffffff 552#define AR_Q_CBRCFG_INTERVAL_S 0 553#define AR_Q_CBRCFG_OVF_THRESH_M 0xff000000 554#define AR_Q_CBRCFG_OVF_THRESH_S 24 555 556/* Bits for AR_QRDYTIMECFG_*. */ 557#define AR_Q_RDYTIMECFG_DURATION_M 0x00ffffff 558#define AR_Q_RDYTIMECFG_DURATION_S 0 559#define AR_Q_RDYTIMECFG_EN 0x01000000 560 561/* Bits for AR_QMISC_*. */ 562#define AR_Q_MISC_FSP_M 0x0000000f 563#define AR_Q_MISC_FSP_S 0 564#define AR_Q_MISC_FSP_ASAP 0 565#define AR_Q_MISC_FSP_CBR 1 566#define AR_Q_MISC_FSP_DBA_GATED 2 567#define AR_Q_MISC_FSP_TIM_GATED 3 568#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 569#define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 570#define AR_Q_MISC_ONE_SHOT_EN 0x00000010 571#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 572#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 573#define AR_Q_MISC_BEACON_USE 0x00000080 574#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 575#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 576#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 577#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 578 579/* Bits for AR_QSTS_*. */ 580#define AR_Q_STS_PEND_FR_CNT_M 0x00000003 581#define AR_Q_STS_PEND_FR_CNT_S 0 582#define AR_Q_STS_CBR_EXP_CNT_M 0x0000ff00 583#define AR_Q_STS_CBR_EXP_CNT_S 8 584 585/* Bits for AR_Q_DESC_CRCCHK. */ 586#define AR_Q_DESC_CRCCHK_EN 0x00000001 587 588#define AR_NUM_DCU 10 589#define AR_DCU(x) (1 << (x)) 590 591/* Bits for AR_D_QCUMASK_*. */ 592#define AR_D_QCUMASK_M 0x000003ff 593#define AR_D_QCUMASK_S 0 594 595/* Bits for AR_D_GBL_IFS_SIFS. */ 596#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003ab 597 598/* Bits for AR_D_TXBLK_CMD. */ 599#define AR_D_TXBLK_WRITE_BITMASK_M 0x0000ffff 600#define AR_D_TXBLK_WRITE_BITMASK_S 0 601#define AR_D_TXBLK_WRITE_SLICE_M 0x000f0000 602#define AR_D_TXBLK_WRITE_SLICE_S 16 603#define AR_D_TXBLK_WRITE_DCU_M 0x00f00000 604#define AR_D_TXBLK_WRITE_DCU_S 20 605#define AR_D_TXBLK_WRITE_COMMAND_M 0x0f000000 606#define AR_D_TXBLK_WRITE_COMMAND_S 24 607 608/* Bits for AR_DLCL_IFS. */ 609#define AR_D_LCL_IFS_CWMIN_M 0x000003ff 610#define AR_D_LCL_IFS_CWMIN_S 0 611#define AR_D_LCL_IFS_CWMAX_M 0x000ffc00 612#define AR_D_LCL_IFS_CWMAX_S 10 613#define AR_D_LCL_IFS_AIFS_M 0x0ff00000 614#define AR_D_LCL_IFS_AIFS_S 20 615 616/* Bits for AR_D_GBL_IFS_SLOT. */ 617#define AR_D_GBL_IFS_SLOT_M 0x0000ffff 618#define AR_D_GBL_IFS_SLOT_S 0 619#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 620 621/* Bits for AR_DRETRY_LIMIT_*. */ 622#define AR_D_RETRY_LIMIT_FR_SH_M 0x0000000f 623#define AR_D_RETRY_LIMIT_FR_SH_S 0 624#define AR_D_RETRY_LIMIT_STA_SH_M 0x00003f00 625#define AR_D_RETRY_LIMIT_STA_SH_S 8 626#define AR_D_RETRY_LIMIT_STA_LG_M 0x000fc000 627#define AR_D_RETRY_LIMIT_STA_LG_S 14 628 629/* Bits for AR_D_GBL_IFS_EIFS. */ 630#define AR_D_GBL_IFS_EIFS_M 0x0000ffff 631#define AR_D_GBL_IFS_EIFS_S 0 632#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000a5eb 633 634/* Bits for AR_DCHNTIME_*. */ 635#define AR_D_CHNTIME_DUR_M 0x000fffff 636#define AR_D_CHNTIME_DUR_S 0 637#define AR_D_CHNTIME_EN 0x00100000 638 639/* Bits for AR_D_GBL_IFS_MISC. */ 640#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 641#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 642#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000ffc00 643#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 644#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 645#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 646#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 647#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 648 649/* Bits for AR_DMISC_*. */ 650#define AR_D_MISC_BKOFF_THRESH_M 0x0000003f 651#define AR_D_MISC_BKOFF_THRESH_S 0 652#define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 653#define AR_D_MISC_CW_RESET_EN 0x00000080 654#define AR_D_MISC_FRAG_WAIT_EN 0x00000100 655#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 656#define AR_D_MISC_CW_BKOFF_EN 0x00001000 657#define AR_D_MISC_VIR_COL_HANDLING_M 0x0000c000 658#define AR_D_MISC_VIR_COL_HANDLING_S 14 659#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 660#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 661#define AR_D_MISC_BEACON_USE 0x00010000 662#define AR_D_MISC_ARB_LOCKOUT_CNTRL_M 0x00060000 663#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 664#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 665#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 666#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 667#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 668#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 669#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 670#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 671#define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 672 673/* Bits for AR_D_FPCTL. */ 674#define AR_D_FPCTL_DCU_M 0x0000000f 675#define AR_D_FPCTL_DCU_S 0 676#define AR_D_FPCTL_PREFETCH_EN 0x00000010 677#define AR_D_FPCTL_BURST_PREFETCH_M 0x00007fe0 678#define AR_D_FPCTL_BURST_PREFETCH_S 5 679 680/* Bits for AR_D_TXPSE. */ 681#define AR_D_TXPSE_CTRL_M 0x000003ff 682#define AR_D_TXPSE_CTRL_S 0 683#define AR_D_TXPSE_STATUS 0x00010000 684 685/* Bits for AR_D_TXSLOTMASK. */ 686#define AR_D_TXSLOTMASK_NUM 0x0000000f 687 688/* Bits for AR_MAC_SLEEP. */ 689#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 690 691/* Bits for AR_CFG_LED. */ 692#define AR_CFG_SCLK_RATE_IND_M 0x00000003 693#define AR_CFG_SCLK_RATE_IND_S 0 694#define AR_CFG_SCLK_32MHZ 0 695#define AR_CFG_SCLK_4MHZ 1 696#define AR_CFG_SCLK_1MHZ 2 697#define AR_CFG_SCLK_32KHZ 3 698#define AR_CFG_LED_BLINK_SLOW 0x00000008 699#define AR_CFG_LED_BLINK_THRESH_SEL_M 0x00000070 700#define AR_CFG_LED_BLINK_THRESH_SEL_S 4 701#define AR_CFG_LED_MODE_SEL_M 0x00000380 702#define AR_CFG_LED_MODE_SEL_S 7 703#define AR_CFG_LED_POWER_M 0x00000280 704#define AR_CFG_LED_POWER_S 7 705#define AR_CFG_LED_NETWORK_M 0x00000300 706#define AR_CFG_LED_NETWORK_S 7 707#define AR_CFG_LED_MODE_PROP 0 708#define AR_CFG_LED_MODE_RPROP 1 709#define AR_CFG_LED_MODE_SPLIT 2 710#define AR_CFG_LED_MODE_RAND 3 711#define AR_CFG_LED_MODE_POWER_OFF 4 712#define AR_CFG_LED_MODE_POWER_ON 5 713#define AR_CFG_LED_MODE_NETWORK_OFF 4 714#define AR_CFG_LED_MODE_NETWORK_ON 6 715#define AR_CFG_LED_ASSOC_CTL_M 0x00000c00 716#define AR_CFG_LED_ASSOC_CTL_S 10 717#define AR_CFG_LED_ASSOC_NONE 0 718#define AR_CFG_LED_ASSOC_ACTIVE 1 719#define AR_CFG_LED_ASSOC_PENDING 2 720 721/* Bit for AR_RC. */ 722#define AR_RC_AHB 0x00000001 723#define AR_RC_APB 0x00000002 724#define AR_RC_HOSTIF 0x00000100 725 726/* Bits for AR_WA. */ 727#define AR5416_WA_DEFAULT 0x0000073f 728#define AR9280_WA_DEFAULT 0x0040073b 729#define AR9285_WA_DEFAULT 0x004a050b 730#define AR_WA_UNTIE_RESET_EN 0x00008000 731#define AR_WA_RESET_EN 0x00040000 732#define AR_WA_ANALOG_SHIFT 0x00100000 733#define AR_WA_POR_SHORT 0x00200000 734 735/* Bits for AR_PM_STATE. */ 736#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 737 738/* Bits for AR_PCIE_PM_CTRL. */ 739#define AR_PCIE_PM_CTRL_ENA 0x00080000 740 741/* Bits for AR_HOST_TIMEOUT. */ 742#define AR_HOST_TIMEOUT_APB_CNTR_M 0x0000ffff 743#define AR_HOST_TIMEOUT_APB_CNTR_S 0 744#define AR_HOST_TIMEOUT_LCL_CNTR_M 0xffff0000 745#define AR_HOST_TIMEOUT_LCL_CNTR_S 16 746 747/* Bits for AR_EEPROM. */ 748#define AR_EEPROM_ABSENT 0x00000100 749#define AR_EEPROM_CORRUPT 0x00000200 750#define AR_EEPROM_PROT_MASK_M 0x03fffc00 751#define AR_EEPROM_PROT_MASK_S 10 752 753/* Bits for AR_SREV. */ 754#define AR_SREV_ID_M 0x000000ff 755#define AR_SREV_ID_S 0 756#define AR_SREV_REVISION_M 0x00000007 757#define AR_SREV_REVISION_S 0 758#define AR_SREV_VERSION_M 0x000000f0 759#define AR_SREV_VERSION_S 4 760#define AR_SREV_VERSION2_M 0xfffc0000 761#define AR_SREV_VERSION2_S 12 /* XXX Hack. */ 762#define AR_SREV_TYPE2_M 0x0003f000 763#define AR_SREV_TYPE2_S 12 764#define AR_SREV_TYPE2_CHAIN 0x00001000 765#define AR_SREV_TYPE2_HOST_MODE 0x00002000 766#define AR_SREV_REVISION2_M 0x00000f00 767#define AR_SREV_REVISION2_S 8 768#define AR_SREV_VERSION_5416_PCI 0x00d 769#define AR_SREV_VERSION_5416_PCIE 0x00c 770#define AR_SREV_REVISION_5416_10 0 771#define AR_SREV_REVISION_5416_20 1 772#define AR_SREV_REVISION_5416_22 2 773#define AR_SREV_VERSION_9100 0x014 774#define AR_SREV_VERSION_9160 0x040 775#define AR_SREV_REVISION_9160_10 0 776#define AR_SREV_REVISION_9160_11 1 777#define AR_SREV_VERSION_9280 0x080 778#define AR_SREV_REVISION_9280_10 0 779#define AR_SREV_REVISION_9280_20 1 780#define AR_SREV_REVISION_9280_21 2 781#define AR_SREV_VERSION_9285 0x0c0 782#define AR_SREV_REVISION_9285_10 0 783#define AR_SREV_REVISION_9285_11 1 784#define AR_SREV_REVISION_9285_12 2 785#define AR_SREV_VERSION_9271 0x140 786#define AR_SREV_REVISION_9271_10 0 787#define AR_SREV_REVISION_9271_11 1 788#define AR_SREV_VERSION_9287 0x180 789#define AR_SREV_REVISION_9287_10 0 790#define AR_SREV_REVISION_9287_11 1 791#define AR_SREV_REVISION_9287_12 2 792#define AR_SREV_REVISION_9287_13 3 793#define AR_SREV_VERSION_9380 0x1c0 794#define AR_SREV_REVISION_9380_10 0 795#define AR_SREV_REVISION_9380_20 2 796#define AR_SREV_VERSION_9485 0x240 797#define AR_SREV_REVISION_9485_10 0 798 799/* Bits for AR_AHB_MODE. */ 800#define AR_AHB_EXACT_WR_EN 0x00000000 801#define AR_AHB_BUF_WR_EN 0x00000001 802#define AR_AHB_EXACT_RD_EN 0x00000000 803#define AR_AHB_CACHELINE_RD_EN 0x00000002 804#define AR_AHB_PREFETCH_RD_EN 0x00000004 805#define AR_AHB_PAGE_SIZE_1K 0x00000000 806#define AR_AHB_PAGE_SIZE_2K 0x00000008 807#define AR_AHB_PAGE_SIZE_4K 0x00000010 808#define AR_AHB_CUSTOM_BURST_M 0x000000c0 809#define AR_AHB_CUSTOM_BURST_S 6 810#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 811 812/* Bits for AR_INTR_SYNC_CAUSE. */ 813#define AR_INTR_SYNC_RTC_IRQ 0x00000001 814#define AR_INTR_SYNC_MAC_IRQ 0x00000002 815#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 816#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 817#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 818#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 819#define AR_INTR_SYNC_HOST1_PERR 0x00000040 820#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 821#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 822#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 823#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 824#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 825#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 826#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 827#define AR_INTR_SYNC_PM_ACCESS 0x00004000 828#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 829#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 830#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 831#define AR_INTR_SYNC_ALL 0x0003ffff 832#define AR_INTR_SYNC_GPIO_PIN(i) (1 << (18 + (i))) 833 834#define AR_INTR_SYNC_DEFAULT \ 835 (AR_INTR_SYNC_HOST1_FATAL | \ 836 AR_INTR_SYNC_HOST1_PERR | \ 837 AR_INTR_SYNC_RADM_CPL_EP | \ 838 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 839 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | \ 840 AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 841 AR_INTR_SYNC_RADM_CPL_TIMEOUT | \ 842 AR_INTR_SYNC_LOCAL_TIMEOUT | \ 843 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 844 845/* Bits for AR_INTR_ASYNC_CAUSE. */ 846#define AR_INTR_RTC_IRQ 0x00000001 847#define AR_INTR_MAC_IRQ 0x00000002 848#define AR_INTR_EEP_PROT_ACCESS 0x00000004 849#define AR_INTR_MAC_AWAKE 0x00020000 850#define AR_INTR_MAC_ASLEEP 0x00040000 851#define AR_INTR_GPIO_PIN(i) (1 << (18 + (i))) 852#define AR_INTR_SPURIOUS 0xffffffff 853 854/* Bits for AR_GPIO_OE_OUT. */ 855#define AR_GPIO_OE_OUT_DRV_M 0x00000003 856#define AR_GPIO_OE_OUT_DRV_S 0 857#define AR_GPIO_OE_OUT_DRV_NO 0 858#define AR_GPIO_OE_OUT_DRV_LOW 1 859#define AR_GPIO_OE_OUT_DRV_HI 2 860#define AR_GPIO_OE_OUT_DRV_ALL 3 861 862/* Bits for AR_GPIO_INTR_POL. */ 863#define AR_GPIO_INTR_POL_PIN(i) (1 << (i)) 864 865/* Bits for AR_GPIO_INPUT_EN_VAL. */ 866#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 867#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 868#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 869#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 870#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 871#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 872#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 873#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 874#define AR_GPIO_JTAG_DISABLE 0x00020000 875 876/* Bits for AR_GPIO_INPUT_MUX1. */ 877#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_M 0x00000f00 878#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 879#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_M 0x000f0000 880#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 881 882/* Bits for AR_GPIO_INPUT_MUX2. */ 883#define AR_GPIO_INPUT_MUX2_CLK25_M 0x0000000f 884#define AR_GPIO_INPUT_MUX2_CLK25_S 0 885#define AR_GPIO_INPUT_MUX2_RFSILENT_M 0x000000f0 886#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 887#define AR_GPIO_INPUT_MUX2_RTC_RESET_M 0x00000f00 888#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 889 890/* Bits for AR_GPIO_OUTPUT_MUX[1-3]. */ 891#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 892#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 893#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 894#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 895#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 896#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 897#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 898 899/* Bits for AR_EEPROM_STATUS_DATA. */ 900#define AR_EEPROM_STATUS_DATA_VAL_M 0x0000ffff 901#define AR_EEPROM_STATUS_DATA_VAL_S 0 902#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 903#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 904#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 905#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 906 907/* Bits for AR_PCIE_MSI. */ 908#define AR_PCIE_MSI_ENABLE 0x00000001 909 910/* Bits for AR_RTC_RC. */ 911#define AR_RTC_RC_MAC_WARM 0x00000001 912#define AR_RTC_RC_MAC_COLD 0x00000002 913#define AR_RTC_RC_COLD_RESET 0x00000004 914#define AR_RTC_RC_WARM_RESET 0x00000008 915 916/* Bits for AR_RTC_REG_CONTROL1. */ 917#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 918 919/* Bits for AR_RTC_PLL_CONTROL. */ 920#define AR_RTC_PLL_DIV_M 0x0000001f 921#define AR_RTC_PLL_DIV_S 0 922#define AR_RTC_PLL_DIV2 0x00000020 923#define AR_RTC_PLL_REFDIV_5 0x000000c0 924#define AR_RTC_PLL_CLKSEL_M 0x00000300 925#define AR_RTC_PLL_CLKSEL_S 8 926#define AR_RTC_9160_PLL_DIV_M 0x000003ff 927#define AR_RTC_9160_PLL_DIV_S 0 928#define AR_RTC_9160_PLL_REFDIV_M 0x00003c00 929#define AR_RTC_9160_PLL_REFDIV_S 10 930#define AR_RTC_9160_PLL_CLKSEL_M 0x0000c000 931#define AR_RTC_9160_PLL_CLKSEL_S 14 932 933/* Bits for AR_RTC_RESET. */ 934#define AR_RTC_RESET_EN 0x00000001 935 936/* Bits for AR_RTC_STATUS. */ 937#define AR_RTC_STATUS_M 0x0000000f 938#define AR_RTC_STATUS_S 0 939#define AR_RTC_STATUS_SHUTDOWN 0x00000001 940#define AR_RTC_STATUS_ON 0x00000002 941#define AR_RTC_STATUS_SLEEP 0x00000004 942#define AR_RTC_STATUS_WAKEUP 0x00000008 943 944/* Bits for AR_RTC_SLEEP_CLK. */ 945#define AR_RTC_FORCE_DERIVED_CLK 0x00000002 946#define AR_RTC_FORCE_SWREG_PRD 0x00000004 947 948/* Bits for AR_RTC_FORCE_WAKE. */ 949#define AR_RTC_FORCE_WAKE_EN 0x00000001 950#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 951 952/* Bits for AR_STA_ID1. */ 953#define AR_STA_ID1_SADH_M 0x0000ffff 954#define AR_STA_ID1_SADH_S 0 955#define AR_STA_ID1_STA_AP 0x00010000 956#define AR_STA_ID1_ADHOC 0x00020000 957#define AR_STA_ID1_PWR_SAV 0x00040000 958#define AR_STA_ID1_KSRCHDIS 0x00080000 959#define AR_STA_ID1_PCF 0x00100000 960#define AR_STA_ID1_USE_DEFANT 0x00200000 961#define AR_STA_ID1_DEFANT_UPDATE 0x00400000 962#define AR_STA_ID1_RTS_USE_DEF 0x00800000 963#define AR_STA_ID1_ACKCTS_6MB 0x01000000 964#define AR_STA_ID1_BASE_RATE_11B 0x02000000 965#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 966#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 967#define AR_STA_ID1_KSRCH_MODE 0x10000000 968#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 969#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 970#define AR_STA_ID1_MCAST_KSRCH 0x80000000 971 972/* Bits for AR_BSS_ID1. */ 973#define AR_BSS_ID1_U16_M 0x0000ffff 974#define AR_BSS_ID1_U16_S 0 975#define AR_BSS_ID1_AID_M 0x07ff0000 976#define AR_BSS_ID1_AID_S 16 977 978/* Bits for AR_TIME_OUT. */ 979#define AR_TIME_OUT_ACK_M 0x00003fff 980#define AR_TIME_OUT_ACK_S 0 981#define AR_TIME_OUT_CTS_M 0x3fff0000 982#define AR_TIME_OUT_CTS_S 16 983#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001d56 984 985/* Bits for AR_RSSI_THR. */ 986#define AR_RSSI_THR_M 0x000000ff 987#define AR_RSSI_THR_S 0 988#define AR_RSSI_THR_BM_THR_M 0x0000ff00 989#define AR_RSSI_THR_BM_THR_S 8 990#define AR_RSSI_BCN_WEIGHT_M 0x1f000000 991#define AR_RSSI_BCN_WEIGHT_S 24 992#define AR_RSSI_BCN_RSSI_RST 0x20000000 993 994/* Bits for AR_USEC. */ 995#define AR_USEC_USEC_M 0x0000007f 996#define AR_USEC_USEC_S 0 997#define AR_USEC_TX_LAT_M 0x007fc000 998#define AR_USEC_TX_LAT_S 14 999#define AR_USEC_RX_LAT_M 0x1f800000 1000#define AR_USEC_RX_LAT_S 23 1001#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 1002 1003/* Bits for AR_RESET_TSF. */ 1004#define AR_RESET_TSF_ONCE 0x01000000 1005 1006/* Bits for AR_RX_FILTER. */ 1007#define AR_RX_FILTER_UCAST 0x00000001 1008#define AR_RX_FILTER_MCAST 0x00000002 1009#define AR_RX_FILTER_BCAST 0x00000004 1010#define AR_RX_FILTER_CONTROL 0x00000008 1011#define AR_RX_FILTER_BEACON 0x00000010 1012#define AR_RX_FILTER_PROM 0x00000020 1013#define AR_RX_FILTER_PROBEREQ 0x00000080 1014#define AR_RX_FILTER_MYBEACON 0x00000200 1015#define AR_RX_FILTER_COMPR_BAR 0x00000400 1016#define AR_RX_FILTER_PSPOLL 0x00004000 1017 1018/* Bits for AR_DIAG_SW. */ 1019#define AR_DIAG_CACHE_ACK 0x00000001 1020#define AR_DIAG_ACK_DIS 0x00000002 1021#define AR_DIAG_CTS_DIS 0x00000004 1022#define AR_DIAG_ENCRYPT_DIS 0x00000008 1023#define AR_DIAG_DECRYPT_DIS 0x00000010 1024#define AR_DIAG_RX_DIS 0x00000020 1025#define AR_DIAG_LOOP_BACK 0x00000040 1026#define AR_DIAG_CORR_FCS 0x00000080 1027#define AR_DIAG_CHAN_INFO 0x00000100 1028#define AR_DIAG_SCRAM_SEED_M 0x0001fe00 1029#define AR_DIAG_SCRAM_SEED_S 8 /* XXX should be 9? */ 1030#define AR_DIAG_FRAME_NV0 0x00020000 1031#define AR_DIAG_OBS_PT_SEL1_M 0x000c0000 1032#define AR_DIAG_OBS_PT_SEL1_S 18 1033#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 1034#define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1035#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1036#define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1037#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1038#define AR_DIAG_RX_ABORT 0x02000000 1039#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1040#define AR_DIAG_OBS_PT_SEL2 0x08000000 1041#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1042#define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 1043 1044/* Bits for AR_AES_MUTE_MASK0. */ 1045#define AR_AES_MUTE_MASK0_FC_M 0x0000ffff 1046#define AR_AES_MUTE_MASK0_FC_S 0 1047#define AR_AES_MUTE_MASK0_QOS_M 0xffff0000 1048#define AR_AES_MUTE_MASK0_QOS_S 16 1049 1050/* Bits for AR_AES_MUTE_MASK1. */ 1051#define AR_AES_MUTE_MASK1_SEQ_M 0x0000ffff 1052#define AR_AES_MUTE_MASK1_SEQ_S 0 1053#define AR_AES_MUTE_MASK1_FC_MGMT_M 0xffff0000 1054#define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1055#define AR_AES_MUTE_MASK1_FC0_MGMT_M 0x00ff0000 1056#define AR_AES_MUTE_MASK1_FC0_MGMT_S 16 1057#define AR_AES_MUTE_MASK1_FC1_MGMT_M 0xff000000 1058#define AR_AES_MUTE_MASK1_FC1_MGMT_S 24 1059 1060/* Bits for AR_GATED_CLKS. */ 1061#define AR_GATED_CLKS_TX 0x00000002 1062#define AR_GATED_CLKS_RX 0x00000004 1063#define AR_GATED_CLKS_REG 0x00000008 1064 1065/* Bits for AR_OBS_BUS_CTRL. */ 1066#define AR_OBS_BUS_SEL_1 0x00040000 1067#define AR_OBS_BUS_SEL_2 0x00080000 1068#define AR_OBS_BUS_SEL_3 0x000c0000 1069#define AR_OBS_BUS_SEL_4 0x08040000 1070#define AR_OBS_BUS_SEL_5 0x08080000 1071 1072/* Bits for AR_OBS_BUS_1. */ 1073#define AR_OBS_BUS_1_PCU 0x00000001 1074#define AR_OBS_BUS_1_RX_END 0x00000002 1075#define AR_OBS_BUS_1_RX_WEP 0x00000004 1076#define AR_OBS_BUS_1_RX_BEACON 0x00000008 1077#define AR_OBS_BUS_1_RX_FILTER 0x00000010 1078#define AR_OBS_BUS_1_TX_HCF 0x00000020 1079#define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1080#define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1081#define AR_OBS_BUS_1_TX_HOLD 0x00000100 1082#define AR_OBS_BUS_1_TX_FRAME 0x00000200 1083#define AR_OBS_BUS_1_RX_FRAME 0x00000400 1084#define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1085#define AR_OBS_BUS_1_WEP_STATE_M 0x0003f000 1086#define AR_OBS_BUS_1_WEP_STATE_S 12 1087#define AR_OBS_BUS_1_RX_STATE_M 0x01f00000 1088#define AR_OBS_BUS_1_RX_STATE_S 20 1089#define AR_OBS_BUS_1_TX_STATE_M 0x7e000000 1090#define AR_OBS_BUS_1_TX_STATE_S 25 1091 1092/* Bits for AR_SLEEP1. */ 1093#define AR_SLEEP1_ASSUME_DTIM 0x00080000 1094#define AR_SLEEP1_CAB_TIMEOUT_M 0xffe00000 1095#define AR_SLEEP1_CAB_TIMEOUT_S 21 1096/* Default value. */ 1097#define AR_CAB_TIMEOUT_VAL 10 1098 1099/* Bits for AR_SLEEP2. */ 1100#define AR_SLEEP2_BEACON_TIMEOUT_M 0xffe00000 1101#define AR_SLEEP2_BEACON_TIMEOUT_S 21 1102 1103/* Bits for AR_TPC. */ 1104#define AR_TPC_ACK_M 0x0000003f 1105#define AR_TPC_ACK_S 0 1106#define AR_TPC_CTS_M 0x00003f00 1107#define AR_TPC_CTS_S 8 1108#define AR_TPC_CHIRP_M 0x003f0000 1109#define AR_TPC_CHIRP_S 16 1110 1111/* Bits for AR_QUIET1. */ 1112#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1113#define AR_QUIET1_NEXT_QUIET_S 0 1114#define AR_QUIET1_QUIET_ENABLE 0x00010000 1115#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 1116 1117/* Bits for AR_QUIET2. */ 1118#define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1119#define AR_QUIET2_QUIET_PERIOD_S 0 1120#define AR_QUIET2_QUIET_DUR_M 0xffff0000 1121#define AR_QUIET2_QUIET_DUR_S 16 1122 1123/* Bits for AR_TSF_PARM. */ 1124#define AR_TSF_INCREMENT_M 0x000000ff 1125#define AR_TSF_INCREMENT_S 0 1126 1127/* Bits for AR_QOS_NO_ACK. */ 1128#define AR_QOS_NO_ACK_TWO_BIT_M 0x0000000f 1129#define AR_QOS_NO_ACK_TWO_BIT_S 0 1130#define AR_QOS_NO_ACK_BIT_OFF_M 0x0000007f 1131#define AR_QOS_NO_ACK_BIT_OFF_S 4 1132#define AR_QOS_NO_ACK_BYTE_OFF_M 0x00000180 1133#define AR_QOS_NO_ACK_BYTE_OFF_S 7 1134 1135/* Bits for AR_PHY_ERR. */ 1136#define AR_PHY_ERR_DCHIRP 0x00000008 1137#define AR_PHY_ERR_RADAR 0x00000020 1138#define AR_PHY_ERR_OFDM_TIMING 0x00020000 1139#define AR_PHY_ERR_CCK_TIMING 0x02000000 1140 1141/* Bits for AR_PCU_MISC. */ 1142#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 1143#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 1144#define AR_PCU_TX_ADD_TSF 0x00000008 1145#define AR_PCU_CCK_SIFS_MODE 0x00000010 1146#define AR_PCU_RX_ANT_UPDT 0x00000800 1147#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 1148#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 1149#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 1150#define AR_PCU_FORCE_QUIET_COLL 0x00040000 1151#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1152#define AR_PCU_TBTT_PROTECT 0x00200000 1153#define AR_PCU_CLEAR_VMF 0x01000000 1154#define AR_PCU_CLEAR_BA_VALID 0x04000000 1155 1156/* Bits for AR_BT_COEX_MODE. */ 1157#define AR_BT_TIME_EXTEND_M 0x000000ff 1158#define AR_BT_TIME_EXTEND_S 0 1159#define AR_BT_TXSTATE_EXTEND 0x00000100 1160#define AR_BT_TX_FRAME_EXTEND 0x00000200 1161#define AR_BT_MODE_M 0x00000c00 1162#define AR_BT_MODE_S 10 1163#define AR_BT_MODE_LEGACY 0 1164#define AR_BT_MODE_UNSLOTTED 1 1165#define AR_BT_MODE_SLOTTED 2 1166#define AR_BT_MODE_DISABLED 3 1167#define AR_BT_QUIET 0x00001000 1168#define AR_BT_QCU_THRESH_M 0x0001e000 1169#define AR_BT_QCU_THRESH_S 13 1170#define AR_BT_RX_CLEAR_POLARITY 0x00020000 1171#define AR_BT_PRIORITY_TIME_M 0x00fc0000 1172#define AR_BT_PRIORITY_TIME_S 18 1173#define AR_BT_FIRST_SLOT_TIME_M 0xff000000 1174#define AR_BT_FIRST_SLOT_TIME_S 24 1175 1176/* Bits for AR_BT_COEX_WEIGHT. */ 1177#define AR_BTCOEX_BT_WGHT_M 0x0000ffff 1178#define AR_BTCOEX_BT_WGHT_S 0 1179#define AR_STOMP_LOW_BT_WGHT 0xff55 1180#define AR_BTCOEX_WL_WGHT_M 0xffff0000 1181#define AR_BTCOEX_WL_WGHT_S 16 1182#define AR_STOMP_LOW_WL_WGHT 0xaaa8 1183 1184/* Bits for AR_BT_COEX_MODE2. */ 1185#define AR_BT_BCN_MISS_THRESH_M 0x000000ff 1186#define AR_BT_BCN_MISS_THRESH_S 0 1187#define AR_BT_BCN_MISS_CNT_M 0x0000ff00 1188#define AR_BT_BCN_MISS_CNT_S 8 1189#define AR_BT_HOLD_RX_CLEAR 0x00010000 1190#define AR_BT_DISABLE_BT_ANT 0x00100000 1191 1192/* Bits for AR_PCU_BA_BAR_CTRL. */ 1193#define AR_PCU_BA_BAR_COMRESSED 0x00000100 1194#define AR_PCU_BA_BAR_ACK_POLICY 0x00000200 1195#define AR_PCU_BA_BAR_ACK_POLICY_OFFSET_M 0x000000f0 1196#define AR_PCU_BA_BAR_ACK_POLICY_OFFSET_S 4 1197#define AR_PCU_BA_BAR_COMPRESSED_OFFSET_M 0x0000000f 1198#define AR_PCU_BA_BAR_COMPRESSED_OFFSET_S 0 1199 1200/* Bits for AR_PCU_TXBUF_CTRL. */ 1201#define AR_PCU_TXBUF_CTRL_SIZE_M 0x000007ff 1202#define AR_PCU_TXBUF_CTRL_SIZE_S 0 1203#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 1792 1204#define AR9285_PCU_TXBUF_CTRL_USABLE_SIZE (1792 / 2) 1205 1206/* Bits for AR_PCU_MISC_MODE2. */ 1207#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 1208#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 1209#define AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX 0x00000008 1210#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 1211#define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 1212#define AR_PCU_MISC_MODE2_MGMT_QOS_M 0x0000ff00 1213#define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 1214#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DUR 0x00010000 1215#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 1216#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 1217#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 1218 1219/* Bits for AR_MAC_PCU_LOGIC_ANALYZER. */ 1220#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1221 1222/* Bits for AR_MAC_PCU_ASYNC_FIFO_REG3. */ 1223#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 1224#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 1225 1226/* Bits for AR_PHY_ERR_[123]. */ 1227#define AR_PHY_ERR_COUNT_M 0x00ffffff 1228#define AR_PHY_ERR_COUNT_S 0 1229 1230/* Bits for AR_TSFOOR_THRESHOLD. */ 1231#define AR_TSFOOR_THRESHOLD_VAL_M 0x0000ffff 1232#define AR_TSFOOR_THRESHOLD_VAL_S 0 1233 1234/* Bit for AR_TXSIFS. */ 1235#define AR_TXSIFS_TIME_M 0x000000ff 1236#define AR_TXSIFS_TIME_S 0 1237#define AR_TXSIFS_TX_LATENCY_M 0x00000f00 1238#define AR_TXSIFS_TX_LATENCY_S 8 1239#define AR_TXSIFS_ACK_SHIFT_M 0x00007000 1240#define AR_TXSIFS_ACK_SHIFT_S 12 1241 1242/* Bits for AR_TXOP_X. */ 1243#define AR_TXOP_X_VAL 0x000000ff 1244 1245/* Bits for AR_TIMER_MODE. */ 1246#define AR_TBTT_TIMER_EN 0x00000001 1247#define AR_DBA_TIMER_EN 0x00000002 1248#define AR_SWBA_TIMER_EN 0x00000004 1249#define AR_HCF_TIMER_EN 0x00000008 1250#define AR_TIM_TIMER_EN 0x00000010 1251#define AR_DTIM_TIMER_EN 0x00000020 1252#define AR_QUIET_TIMER_EN 0x00000040 1253#define AR_NDP_TIMER_EN 0x00000080 1254#define AR_TIMER_OVERFLOW_INDEX_M 0x00000700 1255#define AR_TIMER_OVERFLOW_INDEX_S 8 1256#define AR_TIMER_THRESH_M 0xfffff000 1257#define AR_TIMER_THRESH_S 12 1258 1259/* Bits for AR_SLP32_MODE. */ 1260#define AR_SLP32_HALF_CLK_LATENCY_M 0x000fffff 1261#define AR_SLP32_HALF_CLK_LATENCY_S 0 1262#define AR_SLP32_ENA 0x00100000 1263#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 1264 1265/* Bits for AR_SLP32_WAKE. */ 1266#define AR_SLP32_WAKE_XTL_TIME_M 0x0000ffff 1267#define AR_SLP32_WAKE_XTL_TIME_S 0 1268 1269/* Bits for AR_SLP_MIB_CTRL. */ 1270#define AR_SLP_MIB_CLEAR 0x00000001 1271#define AR_SLP_MIB_PENDING 0x00000002 1272 1273/* Bits for AR_2040_MODE. */ 1274#define AR_2040_JOINED_RX_CLEAR 0x00000001 1275 1276/* Bits for AR_KEYTABLE_TYPE. */ 1277#define AR_KEYTABLE_TYPE_M 0x00000007 1278#define AR_KEYTABLE_TYPE_S 0 1279#define AR_KEYTABLE_TYPE_40 0 1280#define AR_KEYTABLE_TYPE_104 1 1281#define AR_KEYTABLE_TYPE_128 3 1282#define AR_KEYTABLE_TYPE_TKIP 4 1283#define AR_KEYTABLE_TYPE_AES 5 1284#define AR_KEYTABLE_TYPE_CCM 6 1285#define AR_KEYTABLE_TYPE_CLR 7 1286#define AR_KEYTABLE_ANT 0x00000008 1287#define AR_KEYTABLE_VALID 0x00008000 1288 1289/* 1290 * AR9271 specific registers. 1291 */ 1292#define AR9271_CLOCK_CONTROL 0x050040 1293#define AR9271_RESET_POWER_DOWN_CONTROL 0x050044 1294#define AR9271_FIRMWARE 0x501000 1295#define AR9271_FIRMWARE_TEXT 0x903000 1296#define AR7010_FIRMWARE_TEXT 0x906000 1297 1298/* Bits for AR9271_RESET_POWER_DOWN_CONTROL. */ 1299#define AR9271_RADIO_RF_RST 0x00000020 1300#define AR9271_GATE_MAC_CTL 0x00004000 1301 1302 1303#define AR_BASE_PHY_ACTIVE_DELAY 100 1304 1305#define AR_CLOCK_RATE_CCK 22 1306#define AR_CLOCK_RATE_5GHZ_OFDM 40 1307#define AR_CLOCK_RATE_FAST_5GHZ_OFDM 44 1308#define AR_CLOCK_RATE_2GHZ_OFDM 44 1309 1310#define AR_PWR_DECREASE_FOR_2_CHAIN 6 /* 10 * log10(2) * 2 */ 1311#define AR_PWR_DECREASE_FOR_3_CHAIN 9 /* 10 * log10(3) * 2 */ 1312 1313#define AR_SLEEP_SLOP 3 /* TUs */ 1314 1315#define AR_MIN_BEACON_TIMEOUT_VAL 1 1316#define AR_FUDGE 2 1317#define AR_BEACON_DMA_DELAY 2 1318#define AR_SWBA_DELAY 10 1319/* Divides by 1024 (usecs to TU) without doing 64-bit arithmetic. */ 1320#define AR_TSF_TO_TU(hi, lo) ((hi) << 22 | (lo) >> 10) 1321 1322#define AR_KEY_CACHE_SIZE 128 1323#define AR_RSVD_KEYTABLE_ENTRIES 4 1324 1325#define AR_CAL_SAMPLES 64 /* XXX AR9280? */ 1326#define AR_MAX_LOG_CAL 2 /* XXX AR9280? */ 1327 1328/* Maximum number of chains supported by any chipset. */ 1329#define AR_MAX_CHAINS 3 1330 1331/* Default number of key cache entries. */ 1332#define AR_KEYTABLE_SIZE 128 1333 1334/* GPIO pins. */ 1335#define AR_GPIO_WLANACTIVE_PIN 5 1336#define AR_GPIO_BTACTIVE_PIN 6 1337#define AR_GPIO_BTPRIORITY_PIN 7 1338 1339#define AR_SREV_5416(sc) \ 1340 ((sc)->mac_ver == AR_SREV_VERSION_5416_PCI || \ 1341 (sc)->mac_ver == AR_SREV_VERSION_5416_PCIE) 1342#define AR_SREV_5416_20_OR_LATER(sc) \ 1343 ((AR_SREV_5416(sc) && \ 1344 (sc)->mac_rev >= AR_SREV_REVISION_5416_20) || \ 1345 (sc)->mac_ver >= AR_SREV_VERSION_9100) 1346#define AR_SREV_5416_22_OR_LATER(sc) \ 1347 ((AR_SREV_5416(sc) && \ 1348 (sc)->mac_rev >= AR_SREV_REVISION_5416_22) || \ 1349 (sc)->mac_ver >= AR_SREV_VERSION_9100) 1350 1351#define AR_SREV_9160(sc) \ 1352 ((sc)->mac_ver == AR_SREV_VERSION_9160) 1353#define AR_SREV_9160_10_OR_LATER(sc) \ 1354 ((sc)->mac_ver >= AR_SREV_VERSION_9160) 1355#define AR_SREV_9160_11(sc) \ 1356 (AR_SREV_9160(sc) && \ 1357 (sc)->mac_rev == AR_SREV_REVISION_9160_11) 1358 1359#define AR_SREV_9280(sc) \ 1360 ((sc)->mac_ver == AR_SREV_VERSION_9280) 1361#define AR_SREV_9280_10_OR_LATER(sc) \ 1362 ((sc)->mac_ver >= AR_SREV_VERSION_9280) 1363#define AR_SREV_9280_10(sc) \ 1364 (AR_SREV_9280(sc) && \ 1365 (sc)->mac_rev == AR_SREV_REVISION_9280_10) 1366#define AR_SREV_9280_20(sc) \ 1367 (AR_SREV_9280(sc) && \ 1368 (sc)->mac_rev >= AR_SREV_REVISION_9280_20) 1369#define AR_SREV_9280_20_OR_LATER(sc) \ 1370 ((sc)->mac_ver > AR_SREV_VERSION_9280 || \ 1371 (AR_SREV_9280(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9280_20)) 1372 1373#define AR_SREV_9285(sc) \ 1374 ((sc)->mac_ver == AR_SREV_VERSION_9285) 1375#define AR_SREV_9285_10_OR_LATER(sc) \ 1376 ((sc)->mac_ver >= AR_SREV_VERSION_9285) 1377#define AR_SREV_9285_11(sc) \ 1378 (AR_SREV_9285(sc) && \ 1379 (sc)->mac_rev == AR_SREV_REVISION_9285_11) 1380#define AR_SREV_9285_11_OR_LATER(sc) \ 1381 ((sc)->mac_ver > AR_SREV_VERSION_9285 || \ 1382 (AR_SREV_9285(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9285_11)) 1383#define AR_SREV_9285_12(sc) \ 1384 (AR_SREV_9285(sc) && \ 1385 ((sc)->mac_rev == AR_SREV_REVISION_9285_12)) 1386#define AR_SREV_9285_12_OR_LATER(sc) \ 1387 ((sc)->mac_ver > AR_SREV_VERSION_9285 || \ 1388 (AR_SREV_9285(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9285_12)) 1389 1390#define AR_SREV_9271(sc) \ 1391 ((sc)->mac_ver == AR_SREV_VERSION_9271) 1392#define AR_SREV_9271_10(sc) \ 1393 (AR_SREV_9271(sc) && \ 1394 (sc)->mac_rev == AR_SREV_REVISION_9271_10) 1395 1396#define AR_SREV_9287(sc) \ 1397 ((sc)->mac_ver == AR_SREV_VERSION_9287) 1398#define AR_SREV_9287_10_OR_LATER(sc) \ 1399 ((sc)->mac_ver >= AR_SREV_VERSION_9287) 1400#define AR_SREV_9287_10(sc) \ 1401 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 1402 (sc)->mac_rev == AR_SREV_REVISION_9287_10) 1403#define AR_SREV_9287_11(sc) \ 1404 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 1405 (sc)->mac_rev == AR_SREV_REVISION_9287_11) 1406#define AR_SREV_9287_11_OR_LATER(sc) \ 1407 ((sc)->mac_ver > AR_SREV_VERSION_9287 || \ 1408 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_11)) 1409#define AR_SREV_9287_12(sc) \ 1410 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 1411 (sc)->mac_rev == AR_SREV_REVISION_9287_12) 1412#define AR_SREV_9287_12_OR_LATER(sc) \ 1413 ((sc)->mac_ver > AR_SREV_VERSION_9287 || \ 1414 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_12)) 1415#define AR_SREV_9287_13_OR_LATER(sc) \ 1416 ((sc)->mac_ver > AR_SREV_VERSION_9287 || \ 1417 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_13)) 1418 1419#define AR_SREV_9380(sc) \ 1420 ((sc)->mac_ver == AR_SREV_VERSION_9380) 1421#define AR_SREV_9380_10_OR_LATER(sc) \ 1422 ((sc)->mac_ver >= AR_SREV_VERSION_9380) 1423#define AR_SREV_9380_20(sc) \ 1424 (AR_SREV_9380(sc) && \ 1425 (sc)->mac_rev == AR_SREV_REVISION_9380_20) 1426#define AR_SREV_9380_20_OR_LATER(sc) \ 1427 ((sc)->mac_ver > AR_SREV_VERSION_9380 || \ 1428 (AR_SREV_9380(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9380_20)) 1429 1430#define AR_SREV_9485(sc) \ 1431 ((sc)->mac_ver == AR_SREV_VERSION_9485) 1432 1433#define AR_SINGLE_CHIP(sc) AR_SREV_9280_10_OR_LATER(sc) 1434 1435#define AR_RADIO_SREV_MAJOR 0xf0 1436#define AR_RAD5133_SREV_MAJOR 0xc0 1437#define AR_RAD2133_SREV_MAJOR 0xd0 1438#define AR_RAD5122_SREV_MAJOR 0xe0 1439#define AR_RAD2122_SREV_MAJOR 0xf0 1440 1441#define AR_BCHAN_UNUSED 0xff 1442#define AR_PD_GAINS_IN_MASK 4 /* NB: Max for all chips. */ 1443#define AR_MAX_RATE_POWER 63 1444 1445#define AR_HT40_POWER_INC_FOR_PDADC 2 1446#define AR_PWR_TABLE_OFFSET_DB (-5) 1447#define AR9280_TX_GAIN_TABLE_SIZE 22 1448#define AR9003_TX_GAIN_TABLE_SIZE 32 1449#define AR9003_PAPRD_MEM_TAB_SIZE 24 1450 1451#define AR_BASE_FREQ_2GHZ 2300 1452#define AR_BASE_FREQ_5GHZ 4900 1453 1454#define AR_SD_NO_CTL 0xe0 1455#define AR_NO_CTL 0xff 1456#define AR_CTL_MODE_M 0x07 1457#define AR_CTL_MODE_S 0 1458#define AR_CTL_11A 0 1459#define AR_CTL_11B 1 1460#define AR_CTL_11G 2 1461#define AR_CTL_2GHT20 5 1462#define AR_CTL_5GHT20 6 1463#define AR_CTL_2GHT40 7 1464#define AR_CTL_5GHT40 8 1465 1466#define AR_DEFAULT_NOISE_FLOOR (-100) 1467 1468/* 1469 * Macros to access registers. 1470 */ 1471#define AR_READ(sc, reg) \ 1472 (sc)->ops.read((sc), (reg)) 1473 1474#define AR_WRITE(sc, reg, val) \ 1475 (sc)->ops.write((sc), (reg), (val)) 1476 1477#define AR_WRITE_BARRIER(sc) \ 1478 (sc)->ops.write_barrier((sc)) 1479 1480#define AR_SETBITS(sc, reg, mask) \ 1481 AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask)) 1482 1483#define AR_CLRBITS(sc, reg, mask) \ 1484 AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask)) 1485 1486/* 1487 * Macros to access subfields in registers. 1488 */ 1489/* Mask and Shift (getter). */ 1490#define MS(val, field) \ 1491 (((uint32_t)(val) & field##_M) >> field##_S) 1492 1493/* Shift and Mask (setter). */ 1494#define SM(field, val) \ 1495 (((uint32_t)(val) << field##_S) & field##_M) 1496 1497/* Rewrite. */ 1498#define RW(var, field, val) \ 1499 (((var) & ~field##_M) | SM(field, val)) 1500