athnreg.h revision 1.6
1/* $OpenBSD: athnreg.h,v 1.6 2010/02/24 19:39:43 damien Exp $ */ 2 3/*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2009 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#define AR_CR 0x0008 21#define AR_RXDP 0x000c 22#define AR_CFG 0x0014 23#define AR_MIRT 0x0020 24#define AR_IER 0x0024 25#define AR_TIMT 0x0028 26#define AR_RIMT 0x002c 27#define AR_TXCFG 0x0030 28#define AR_RXCFG 0x0034 29#define AR_MIBC 0x0040 30#define AR_TOPS 0x0044 31#define AR_RXNPTO 0x0048 32#define AR_TXNPTO 0x004c 33#define AR_RPGTO 0x0050 34#define AR_RPCNT 0x0054 35#define AR_MACMISC 0x0058 36#define AR_GTXTO 0x0064 37#define AR_GTTM 0x0068 38#define AR_CST 0x006c 39#define AR_ISR 0x0080 40#define AR_ISR_S0 0x0084 41#define AR_ISR_S1 0x0088 42#define AR_ISR_S2 0x008c 43#define AR_ISR_S3 0x0090 44#define AR_ISR_S4 0x0094 45#define AR_ISR_S5 0x0098 46#define AR_IMR 0x00a0 47#define AR_IMR_S0 0x00a4 48#define AR_IMR_S1 0x00a8 49#define AR_IMR_S2 0x00ac 50#define AR_IMR_S3 0x00b0 51#define AR_IMR_S4 0x00b4 52#define AR_IMR_S5 0x00b8 53#define AR_ISR_RAC 0x00c0 54#define AR_ISR_S0_S 0x00c4 55#define AR_ISR_S1_S 0x00c8 56#define AR_ISR_S2_S 0x00cc 57#define AR_ISR_S3_S 0x00d0 58#define AR_ISR_S4_S 0x00d4 59#define AR_ISR_S5_S 0x00d8 60#define AR_DMADBG(i) (0x00e0 + (i) * 4) 61#define AR_QTXDP(i) (0x0800 + (i) * 4) 62#define AR_Q_TXE 0x0840 63#define AR_Q_TXD 0x0880 64#define AR_QCBRCFG(i) (0x08c0 + (i) * 4) 65#define AR_QRDYTIMECFG(i) (0x0900 + (i) * 4) 66#define AR_Q_ONESHOTARM_SC 0x0940 67#define AR_Q_ONESHOTARM_CC 0x0980 68#define AR_QMISC(i) (0x09c0 + (i) * 4) 69#define AR_QSTS(i) (0x0a00 + (i) * 4) 70#define AR_Q_RDYTIMESHDN 0x0a40 71#define AR_DQCUMASK(i) (0x1000 + (i) * 4) 72#define AR_D_GBL_IFS_SIFS 0x1030 73#define AR_D_TXBLK_CMD 0x1038 74#define AR_DLCL_IFS(i) (0x1040 + (i) * 4) 75#define AR_D_GBL_IFS_SLOT 0x1070 76#define AR_DRETRY_LIMIT(i) (0x1080 + (i) * 4) 77#define AR_D_GBL_IFS_EIFS 0x10b0 78#define AR_DCHNTIME(i) (0x10c0 + (i) * 4) 79#define AR_D_GBL_IFS_MISC 0x10f0 80#define AR_DMISC(i) (0x1100 + (i) * 4) 81#define AR_D_SEQNUM 0x1140 82#define AR_D_FPCTL 0x1230 83#define AR_D_TXPSE 0x1270 84#define AR_D_TXSLOTMASK 0x12f0 85#define AR_MAC_SLEEP 0x1f00 86#define AR_CFG_LED 0x1f04 87#define AR_EEPROM_OFFSET(i) (0x2000 + (i) * 4) 88#define AR_RC 0x4000 89#define AR_WA 0x4004 90#define AR_PM_STATE 0x4008 91#define AR_PCIE_PM_CTRL 0x4014 92#define AR_HOST_TIMEOUT 0x4018 93#define AR_EEPROM 0x401c 94#define AR_SREV 0x4020 95#define AR_AHB_MODE 0x4024 96#define AR_INTR_SYNC_CAUSE 0x4028 97#define AR_INTR_SYNC_ENABLE 0x402c 98#define AR_INTR_ASYNC_MASK 0x4030 99#define AR_INTR_SYNC_MASK 0x4034 100#define AR_INTR_ASYNC_CAUSE 0x4038 101#define AR_INTR_ASYNC_ENABLE 0x403c 102#define AR_PCIE_SERDES 0x4040 103#define AR_PCIE_SERDES2 0x4044 104#define AR_GPIO_IN_OUT 0x4048 105#define AR_GPIO_OE_OUT 0x404c 106#define AR_GPIO_INTR_POL 0x4050 107#define AR_GPIO_INPUT_EN_VAL 0x4054 108#define AR_GPIO_INPUT_MUX1 0x4058 109#define AR_GPIO_INPUT_MUX2 0x405c 110#define AR_GPIO_OUTPUT_MUX(i) (0x4060 + (i) * 4) 111#define AR_INPUT_STATE 0x406c 112#define AR_EEPROM_STATUS_DATA 0x407c 113#define AR_OBS 0x4080 114#define AR_GPIO_PDPU 0x4088 115#define AR_PCIE_MSI 0x4094 116#define AR_RTC_RC 0x7000 117#define AR_RTC_PLL_CONTROL 0x7014 118#define AR_RTC_RESET 0x7040 119#define AR_RTC_STATUS 0x7044 120#define AR_RTC_SLEEP_CLK 0x7048 121#define AR_RTC_FORCE_WAKE 0x704c 122#define AR_RTC_INTR_CAUSE 0x7050 123#define AR_RTC_INTR_ENABLE 0x7054 124#define AR_RTC_INTR_MASK 0x7058 125#define AR_IS_ANALOG_REG(reg) ((reg) >= 0x7800 && (reg) <= 0x78b4) 126#define AR_AN_RF2G1_CH0 0x7810 127#define AR_AN_RF5G1_CH0 0x7818 128#define AR_AN_RF2G1_CH1 0x7834 129#define AR_AN_RF5G1_CH1 0x783c 130#define AR_AN_SYNTH9 0x7868 131#define AR_AN_TOP1 0x7890 132#define AR_AN_TOP2 0x7894 133#define AR_STA_ID0 0x8000 134#define AR_STA_ID1 0x8004 135#define AR_BSS_ID0 0x8008 136#define AR_BSS_ID1 0x800c 137#define AR_BCN_RSSI_AVE 0x8010 138#define AR_TIME_OUT 0x8014 139#define AR_RSSI_THR 0x8018 140#define AR_USEC 0x801c 141#define AR_RESET_TSF 0x8020 142#define AR_MAX_CFP_DUR 0x8038 143#define AR_RX_FILTER 0x803c 144#define AR_MCAST_FIL0 0x8040 145#define AR_MCAST_FIL1 0x8044 146#define AR_DIAG_SW 0x8048 147#define AR_TSF_L32 0x804c 148#define AR_TSF_U32 0x8050 149#define AR_TST_ADDAC 0x8054 150#define AR_DEF_ANTENNA 0x8058 151#define AR_AES_MUTE_MASK0 0x805c 152#define AR_AES_MUTE_MASK1 0x8060 153#define AR_GATED_CLKS 0x8064 154#define AR_OBS_BUS_CTRL 0x8068 155#define AR_OBS_BUS_1 0x806c 156#define AR_LAST_TSTP 0x8080 157#define AR_NAV 0x8084 158#define AR_RTS_OK 0x8088 159#define AR_RTS_FAIL 0x808c 160#define AR_ACK_FAIL 0x8090 161#define AR_FCS_FAIL 0x8094 162#define AR_BEACON_CNT 0x8098 163#define AR_SLEEP1 0x80d4 164#define AR_SLEEP2 0x80d8 165#define AR_BSSMSKL 0x80e0 166#define AR_BSSMSKU 0x80e4 167#define AR_TPC 0x80e8 168#define AR_TFCNT 0x80ec 169#define AR_RFCNT 0x80f0 170#define AR_RCCNT 0x80f4 171#define AR_CCCNT 0x80f8 172#define AR_QUIET1 0x80fc 173#define AR_QUIET2 0x8100 174#define AR_TSF_PARM 0x8104 175#define AR_QOS_NO_ACK 0x8108 176#define AR_PHY_ERR 0x810c 177#define AR_RXFIFO_CFG 0x8114 178#define AR_MIC_QOS_CONTROL 0x8118 179#define AR_MIC_QOS_SELECT 0x811c 180#define AR_PCU_MISC 0x8120 181#define AR_FILT_OFDM 0x8124 182#define AR_FILT_CCK 0x8128 183#define AR_PHY_ERR_1 0x812c 184#define AR_PHY_ERR_MASK_1 0x8130 185#define AR_PHY_ERR_2 0x8134 186#define AR_PHY_ERR_MASK_2 0x8138 187#define AR_TSFOOR_THRESHOLD 0x813c 188#define AR_PHY_ERR_3 0x8168 189#define AR_PHY_ERR_MASK_3 0x816c 190#define AR_BT_COEX_MODE 0x8170 191#define AR_BT_COEX_WEIGHT 0x8174 192#define AR_BT_COEX_MODE2 0x817c 193#define AR_NEXT_NDP2_TIMER(i) (0x8180 + (i) * 4) 194#define AR_NDP2_PERIOD(i) (0x81a0 + (i) * 4) 195#define AR_NDP2_TIMER_MODE 0x81c0 196#define AR_TXSIFS 0x81d0 197#define AR_TXOP_X 0x81ec 198#define AR_TXOP_0_3 0x81f0 199#define AR_TXOP_4_7 0x81f4 200#define AR_TXOP_8_11 0x81f8 201#define AR_TXOP_12_15 0x81fc 202#define AR_NEXT_TBTT_TIMER 0x8200 203#define AR_NEXT_DMA_BEACON_ALERT 0x8204 204#define AR_NEXT_CFP 0x8208 205#define AR_NEXT_HCF 0x820c 206#define AR_NEXT_TIM 0x8210 207#define AR_NEXT_DTIM 0x8214 208#define AR_NEXT_QUIET_TIMER 0x8218 209#define AR_NEXT_NDP_TIMER 0x821c 210#define AR_BEACON_PERIOD 0x8220 211#define AR_DMA_BEACON_PERIOD 0x8224 212#define AR_SWBA_PERIOD 0x8228 213#define AR_HCF_PERIOD 0x822c 214#define AR_TIM_PERIOD 0x8230 215#define AR_DTIM_PERIOD 0x8234 216#define AR_QUIET_PERIOD 0x8238 217#define AR_NDP_PERIOD 0x823c 218#define AR_TIMER_MODE 0x8240 219#define AR_SLP32_MODE 0x8244 220#define AR_SLP32_WAKE 0x8248 221#define AR_SLP32_INC 0x824c 222#define AR_SLP_CNT 0x8250 223#define AR_SLP_CYCLE_CNT 0x8254 224#define AR_SLP_MIB_CTRL 0x8258 225#define AR_WOW_PATTERN_REG 0x825c 226#define AR_WOW_COUNT_REG 0x8260 227#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 228#define AR_WOW_BCN_EN_REG 0x8270 229#define AR_WOW_BCN_TIMO_REG 0x8274 230#define AR_WOW_KEEP_ALIVE_TIMO_REG 0x8278 231#define AR_WOW_KEEP_ALIVE_REG 0x827c 232#define AR_WOW_US_SCALAR_REG 0x8284 233#define AR_WOW_KEEP_ALIVE_DELAY_REG 0x8288 234#define AR_WOW_PATTERN_MATCH_REG 0x828c 235#define AR_WOW_PATTERN_OFF1_REG 0x8290 236#define AR_WOW_PATTERN_OFF2_REG 0x8294 237#define AR_WOW_EXACT_REG 0x829c 238#define AR_2040_MODE 0x8318 239#define AR_EXTRCCNT 0x8328 240#define AR_SELFGEN_MASK 0x832c 241#define AR_PCU_TXBUF_CTRL 0x8340 242#define AR_PCU_MISC_MODE2 0x8344 243#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 244#define AR_WOW_LENGTH1_REG 0x8360 245#define AR_WOW_LENGTH2_REG 0x8364 246#define AR_WOW_PATTERN_MATCH_LT_256B 0x8368 247#define AR_RATE_DURATION(i) (0x8700 + (i) * 4) 248#define AR_KEYTABLE(i) (0x8800 + (i) * 32) 249#define AR_KEYTABLE_KEY0(i) (AR_KEYTABLE(i) + 0) 250#define AR_KEYTABLE_KEY1(i) (AR_KEYTABLE(i) + 4) 251#define AR_KEYTABLE_KEY2(i) (AR_KEYTABLE(i) + 8) 252#define AR_KEYTABLE_KEY3(i) (AR_KEYTABLE(i) + 12) 253#define AR_KEYTABLE_KEY4(i) (AR_KEYTABLE(i) + 16) 254#define AR_KEYTABLE_TYPE(i) (AR_KEYTABLE(i) + 20) 255#define AR_KEYTABLE_MAC0(i) (AR_KEYTABLE(i) + 24) 256#define AR_KEYTABLE_MAC1(i) (AR_KEYTABLE(i) + 28) 257 258/* 259 * PHY registers. 260 */ 261#define AR_PHY_BASE 0x9800 262#define AR_PHY(i) (AR_PHY_BASE + (i) * 4) 263#define AR_PHY_TEST 0x9800 264#define AR_PHY_TURBO 0x9804 265#define AR_PHY_TEST2 0x9808 266#define AR_PHY_TIMING2 0x9810 267#define AR_PHY_TIMING3 0x9814 268#define AR_PHY_CHIP_ID 0x9818 269#define AR_PHY_ACTIVE 0x981c 270#define AR_PHY_RF_CTL2 0x9824 271#define AR_PHY_RF_CTL3 0x9828 272#define AR_PHY_ADC_CTL 0x982c 273#define AR_PHY_ADC_SERIAL_CTL 0x9830 274#define AR_PHY_RF_CTL4 0x9834 275#define AR_PHY_TSTDAC_CONST 0x983c 276#define AR_PHY_SETTLING 0x9844 277#define AR_PHY_RXGAIN 0x9848 278#define AR_PHY_DESIRED_SZ 0x9850 279#define AR_PHY_FIND_SIG 0x9858 280#define AR_PHY_AGC_CTL1 0x985c 281#define AR_PHY_AGC_CONTROL 0x9860 282#define AR_PHY_CCA(i) (0x9864 + (i) * 0x1000) 283#define AR_PHY_SFCORR 0x9868 284#define AR_PHY_SFCORR_LOW 0x986c 285#define AR_PHY_SLEEP_CTR_CONTROL 0x9870 286#define AR_PHY_SLEEP_CTR_LIMIT 0x9874 287#define AR_PHY_SLEEP_SCAL 0x9878 288#define AR_PHY_PLL_CTL 0x987c 289#define AR_PHY_BIN_MASK_1 0x9900 290#define AR_PHY_BIN_MASK_2 0x9904 291#define AR_PHY_BIN_MASK_3 0x9908 292#define AR_PHY_MASK_CTL 0x990c 293#define AR_PHY_RX_DELAY 0x9914 294#define AR_PHY_SEARCH_START_DELAY 0x9918 295#define AR_PHY_TIMING_CTRL4_0 0x9920 296#define AR_PHY_TIMING_CTRL4(i) (0x9920 + (i) * 0x1000) 297#define AR_PHY_TIMING5 0x9924 298#define AR_PHY_POWER_TX_RATE1 0x9934 299#define AR_PHY_POWER_TX_RATE2 0x9938 300#define AR_PHY_POWER_TX_RATE_MAX 0x993c 301#define AR_PHY_RADAR_EXT 0x9940 302#define AR_PHY_FRAME_CTL 0x9944 303#define AR_PHY_SPUR_REG 0x994c 304#define AR_PHY_RADAR_0 0x9954 305#define AR_PHY_RADAR_1 0x9958 306#define AR_PHY_SWITCH_CHAIN_0 0x9960 307#define AR_PHY_SWITCH_COM 0x9964 308#define AR_PHY_SIGMA_DELTA 0x996c 309#define AR_PHY_RESTART 0x9970 310#define AR_PHY_RFBUS_REQ 0x997c 311#define AR_PHY_TIMING7 0x9980 312#define AR_PHY_TIMING8 0x9984 313#define AR_PHY_BIN_MASK2_1 0x9988 314#define AR_PHY_BIN_MASK2_2 0x998c 315#define AR_PHY_BIN_MASK2_3 0x9990 316#define AR_PHY_BIN_MASK2_4 0x9994 317#define AR_PHY_TIMING9 0x9998 318#define AR_PHY_TIMING10 0x999c 319#define AR_PHY_TIMING11 0x99a0 320#define AR_PHY_RX_CHAINMASK 0x99a4 321#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 322#define AR_PHY_NEW_ADC_DC_GAIN_CORR(i) (0x99b4 + (i) * 0x1000) 323#define AR_PHY_EXT_CCA0 0x99b8 324#define AR_PHY_EXT_CCA(i) (0x99bc + (i) * 0x1000) 325#define AR_PHY_SFCORR_EXT 0x99c0 326#define AR_PHY_HALFGI 0x99d0 327#define AR_PHY_CHANNEL_MASK_01_30 0x99d4 328#define AR_PHY_CHANNEL_MASK_31_60 0x99d8 329#define AR_PHY_CHAN_INFO_MEMORY 0x99dc 330#define AR_PHY_HEAVY_CLIP_ENABLE 0x99e0 331#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec 332#define AR_PHY_CALMODE 0x99f0 333#define AR_PHY_REFCLKDLY 0x99f4 334#define AR_PHY_REFCLKPD 0x99f8 335#define AR_PHY_BB_RFGAIN(i) (0x9a00 + (i) * 4) 336#define AR_PHY_CAL_MEAS_0(i) (0x9c10 + (i) * 0x1000) 337#define AR_PHY_CAL_MEAS_1(i) (0x9c14 + (i) * 0x1000) 338#define AR_PHY_CAL_MEAS_2(i) (0x9c18 + (i) * 0x1000) 339#define AR_PHY_CAL_MEAS_3(i) (0x9c1c + (i) * 0x1000) 340#define AR_PHY_CURRENT_RSSI 0x9c1c 341#define AR_PHY_RFBUS_GRANT 0x9c20 342#define AR9280_PHY_CURRENT_RSSI 0x9c3c 343#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9cf4 344#define AR_PHY_CHAN_INFO_GAIN 0x9cfc 345#define AR_PHY_MODE 0xa200 346#define AR_PHY_CCK_TX_CTRL 0xa204 347#define AR_PHY_CCK_DETECT 0xa208 348#define AR_PHY_GAIN_2GHZ 0xa20c 349#define AR_PHY_CCK_RXCTRL4 0xa21c 350#define AR_PHY_DAG_CTRLCCK 0xa228 351#define AR_PHY_FORCE_CLKEN_CCK 0xa22c 352#define AR_PHY_POWER_TX_RATE3 0xa234 353#define AR_PHY_POWER_TX_RATE4 0xa238 354#define AR_PHY_SCRM_SEQ_XR 0xa23c 355#define AR_PHY_HEADER_DETECT_XR 0xa240 356#define AR_PHY_CHIRP_DETECTED_XR 0xa244 357#define AR_PHY_BLUETOOTH 0xa254 358#define AR_PHY_TPCRG1 0xa258 359#define AR_PHY_TX_PWRCTRL4 0xa264 360#define AR_PHY_ANALOG_SWAP 0xa268 361#define AR_PHY_TPCRG5 0xa26c 362#define AR_PHY_TX_PWRCTRL6_0 0xa270 363#define AR_PHY_TX_PWRCTRL7 0xa274 364#define AR_PHY_TX_PWRCTRL9 0xa27c 365#define AR_PHY_PDADC_TBL_BASE 0xa280 366#define AR_PHY_TX_GAIN_TBL(i) (0xa300 + (i) * 4) 367#define AR_PHY_CL_CAL_CTL 0xa358 368#define AR_PHY_POWER_TX_RATE5 0xa38c 369#define AR_PHY_POWER_TX_RATE6 0xa390 370#define AR_PHY_CH0_TX_PWRCTRL11 0xa398 371#define AR_PHY_CAL_CHAINMASK 0xa39c 372#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 373#define AR_PHY_VIT_MASK2_M_31_45 0xa3a4 374#define AR_PHY_VIT_MASK2_M_16_30 0xa3a8 375#define AR_PHY_VIT_MASK2_M_00_15 0xa3ac 376#define AR_PHY_PILOT_MASK_01_30 0xa3b0 377#define AR_PHY_PILOT_MASK_31_60 0xa3b4 378#define AR_PHY_VIT_MASK2_P_15_01 0xa3b8 379#define AR_PHY_VIT_MASK2_P_30_16 0xa3bc 380#define AR_PHY_VIT_MASK2_P_45_31 0xa3c0 381#define AR_PHY_VIT_MASK2_P_61_46 0xa3c4 382#define AR_PHY_POWER_TX_SUB 0xa3c8 383#define AR_PHY_POWER_TX_RATE7 0xa3cc 384#define AR_PHY_POWER_TX_RATE8 0xa3d0 385#define AR_PHY_POWER_TX_RATE9 0xa3d4 386#define AR_PHY_XPA_CFG 0xa3d8 387#define AR_PHY_TX_PWRCTRL6_1 0xb270 388#define AR_PHY_CH1_TX_PWRCTRL11 0xb398 389 390/* Bits for AR_CR. */ 391#define AR_CR_RXE 0x00000004 392#define AR_CR_RXD 0x00000020 393#define AR_CR_SWI 0x00000040 394 395/* Bits for AR_CFG. */ 396#define AR_CFG_SWTD 0x00000001 397#define AR_CFG_SWTB 0x00000002 398#define AR_CFG_SWRD 0x00000004 399#define AR_CFG_SWRB 0x00000008 400#define AR_CFG_SWRG 0x00000010 401#define AR_CFG_AP_ADHOC_INDICATION 0x00000020 402#define AR_CFG_PHOK 0x00000100 403#define AR_CFG_EEBS 0x00000200 404#define AR_CFG_CLK_GATE_DIS 0x00000400 405#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M 0x00060000 406#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 407 408/* Bits for AR_IER. */ 409#define AR_IER_ENABLE 0x00000001 410 411/* Bits for AR_TIMT. */ 412#define AR_TIMT_LAST_M 0x0000ffff 413#define AR_TIMT_LAST_S 0 414#define AR_TIMT_FIRST_M 0xffff0000 415#define AR_TIMT_FIRST_S 16 416 417/* Bits for AR_RIMT. */ 418#define AR_RIMT_LAST_M 0x0000ffff 419#define AR_RIMT_LAST_S 0 420#define AR_RIMT_FIRST_M 0xffff0000 421#define AR_RIMT_FIRST_S 16 422 423/* Bits for AR_[TR]XCFG_DMASZ fields. */ 424#define AR_DMASZ_4B 0 425#define AR_DMASZ_8B 1 426#define AR_DMASZ_16B 2 427#define AR_DMASZ_32B 3 428#define AR_DMASZ_64B 4 429#define AR_DMASZ_128B 5 430#define AR_DMASZ_256B 6 431#define AR_DMASZ_512B 7 432 433/* Bits for AR_TXCFG. */ 434#define AR_TXCFG_DMASZ_M 0x00000007 435#define AR_TXCFG_DMASZ_S 0 436#define AR_TXCFG_FTRIG_M 0x000003f0 437#define AR_TXCFG_FTRIG_S 4 438#define AR_TXCFG_FTRIG_IMMED ( 0 / 64) 439#define AR_TXCFG_FTRIG_64B ( 64 / 64) 440#define AR_TXCFG_FTRIG_128B (128 / 64) 441#define AR_TXCFG_FTRIG_192B (192 / 64) 442#define AR_TXCFG_FTRIG_256B (256 / 64) 443#define AR_TXCFG_FTRIG_512B (512 / 64) 444#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 445 446/* Bits for AR_RXCFG. */ 447#define AR_RXCFG_DMASZ_M 0x00000007 448#define AR_RXCFG_DMASZ_S 0 449#define AR_RXCFG_CHIRP 0x00000008 450#define AR_RXCFG_ZLFDMA 0x00000010 451 452/* Bits for AR_MIBC. */ 453#define AR_MIBC_COW 0x00000001 454#define AR_MIBC_FMC 0x00000002 455#define AR_MIBC_CMC 0x00000004 456#define AR_MIBC_MCS 0x00000008 457 458/* Bits for AR_TOPS. */ 459#define AR_TOPS_MASK 0x0000ffff 460 461/* Bits for AR_RXNPTO. */ 462#define AR_RXNPTO_MASK 0x000003ff 463 464/* Bits for AR_TXNPTO. */ 465#define AR_TXNPTO_MASK 0x000003ff 466#define AR_TXNPTO_QCU_MASK 0x000ffc00 467 468/* Bits for AR_RPGTO. */ 469#define AR_RPGTO_MASK 0x000003ff 470 471/* Bits for AR_RPCNT. */ 472#define AR_RPCNT_MASK 0x0000001f 473 474/* Bits for AR_MACMISC. */ 475#define AR_MACMISC_PCI_EXT_FORCE 0x00000010 476#define AR_MACMISC_DMA_OBS_M 0x000001e0 477#define AR_MACMISC_DMA_OBS_S 5 478#define AR_MACMISC_MISC_OBS_M 0x00000e00 479#define AR_MACMISC_MISC_OBS_S 9 480#define AR_MACMISC_MISC_OBS_BUS_LSB_M 0x00007000 481#define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 482#define AR_MACMISC_MISC_OBS_BUS_MSB_M 0x00038000 483#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 484 485/* Bits for AR_GTXTO. */ 486#define AR_GTXTO_TIMEOUT_COUNTER_M 0x0000ffff 487#define AR_GTXTO_TIMEOUT_COUNTER_S 0 488#define AR_GTXTO_TIMEOUT_LIMIT_M 0xffff0000 489#define AR_GTXTO_TIMEOUT_LIMIT_S 16 490 491/* Bits for AR_GTTM. */ 492#define AR_GTTM_USEC 0x00000001 493#define AR_GTTM_IGNORE_IDLE 0x00000002 494#define AR_GTTM_RESET_IDLE 0x00000004 495#define AR_GTTM_CST_USEC 0x00000008 496 497/* Bits for AR_CST. */ 498#define AR_CST_TIMEOUT_COUNTER_M 0x0000ffff 499#define AR_CST_TIMEOUT_COUNTER_S 0 500#define AR_CST_TIMEOUT_LIMIT_M 0xffff0000 501#define AR_CST_TIMEOUT_LIMIT_S 16 502 503/* Bits for AR_ISR. */ 504#define AR_ISR_RXOK 0x00000001 505#define AR_ISR_RXDESC 0x00000002 506#define AR_ISR_RXERR 0x00000004 507#define AR_ISR_RXNOPKT 0x00000008 508#define AR_ISR_RXEOL 0x00000010 509#define AR_ISR_RXORN 0x00000020 510#define AR_ISR_TXOK 0x00000040 511#define AR_ISR_TXDESC 0x00000080 512#define AR_ISR_TXERR 0x00000100 513#define AR_ISR_TXNOPKT 0x00000200 514#define AR_ISR_TXEOL 0x00000400 515#define AR_ISR_TXURN 0x00000800 516#define AR_ISR_MIB 0x00001000 517#define AR_ISR_SWI 0x00002000 518#define AR_ISR_RXPHY 0x00004000 519#define AR_ISR_RXKCM 0x00008000 520#define AR_ISR_SWBA 0x00010000 521#define AR_ISR_BRSSI 0x00020000 522#define AR_ISR_BMISS 0x00040000 523#define AR_ISR_TXMINTR 0x00080000 524#define AR_ISR_BNR 0x00100000 525#define AR_ISR_RXCHIRP 0x00200000 526#define AR_ISR_BCNMISC 0x00800000 527#define AR_ISR_TIM 0x00800000 528#define AR_ISR_RXMINTR 0x01000000 529#define AR_ISR_QCBROVF 0x02000000 530#define AR_ISR_QCBRURN 0x04000000 531#define AR_ISR_QTRIG 0x08000000 532#define AR_ISR_GENTMR 0x10000000 533#define AR_ISR_TXINTM 0x40000000 534#define AR_ISR_RXINTM 0x80000000 535 536/* Bits for AR_ISR_S0. */ 537#define AR_ISR_S0_QCU_TXOK_M 0x000003ff 538#define AR_ISR_S0_QCU_TXOK_S 0 539#define AR_ISR_S0_QCU_TXDESC_M 0x03ff0000 540#define AR_ISR_S0_QCU_TXDESC_S 16 541 542/* Bits for AR_ISR_S1. */ 543#define AR_ISR_S1_QCU_TXERR_M 0x000003ff 544#define AR_ISR_S1_QCU_TXERR_S 0 545#define AR_ISR_S1_QCU_TXEOL_M 0x03ff0000 546#define AR_ISR_S1_QCU_TXEOL_S 16 547 548/* Bits for AR_ISR_S2. */ 549#define AR_ISR_S2_QCU_TXURN_M 0x000003ff 550#define AR_ISR_S2_QCU_TXURN_S 0 551#define AR_ISR_S2_CST 0x00400000 552#define AR_ISR_S2_GTT 0x00800000 553#define AR_ISR_S2_TIM 0x01000000 554#define AR_ISR_S2_CABEND 0x02000000 555#define AR_ISR_S2_DTIMSYNC 0x04000000 556#define AR_ISR_S2_BCNTO 0x08000000 557#define AR_ISR_S2_CABTO 0x10000000 558#define AR_ISR_S2_DTIM 0x20000000 559#define AR_ISR_S2_TSFOOR 0x40000000 560#define AR_ISR_S2_TBTT_TIME 0x80000000 561 562/* Bits for AR_ISR_S3. */ 563#define AR_ISR_S3_QCU_QCBROVF_M 0x000003ff 564#define AR_ISR_S3_QCU_QCBROVF_S 0 565#define AR_ISR_S3_QCU_QCBRURN_M 0x03ff0000 566#define AR_ISR_S3_QCU_QCBRURN_S 0 567 568/* Bits for AR_ISR_S4. */ 569#define AR_ISR_S4_QCU_QTRIG_M 0x000003ff 570#define AR_ISR_S4_QCU_QTRIG_S 0 571 572/* Bits for AR_ISR_S5. */ 573#define AR_ISR_S5_TIMER_TRIG_M 0x000000ff 574#define AR_ISR_S5_TIMER_TRIG_S 0 575#define AR_ISR_S5_TIMER_THRESH_M 0x0007fe00 576#define AR_ISR_S5_TIMER_THRESH_S 9 577#define AR_ISR_S5_TIM_TIMER 0x00000010 578#define AR_ISR_S5_DTIM_TIMER 0x00000020 579#define AR_ISR_S5_GENTIMER_TRIG_M 0x0000ff80 580#define AR_ISR_S5_GENTIMER_TRIG_S 0 581#define AR_ISR_S5_GENTIMER_THRESH_M 0xff800000 582#define AR_ISR_S5_GENTIMER_THRESH_S 16 583 584/* Bits for AR_IMR. */ 585#define AR_IMR_RXOK 0x00000001 586#define AR_IMR_RXDESC 0x00000002 587#define AR_IMR_RXERR 0x00000004 588#define AR_IMR_RXNOPKT 0x00000008 589#define AR_IMR_RXEOL 0x00000010 590#define AR_IMR_RXORN 0x00000020 591#define AR_IMR_TXOK 0x00000040 592#define AR_IMR_TXDESC 0x00000080 593#define AR_IMR_TXERR 0x00000100 594#define AR_IMR_TXNOPKT 0x00000200 595#define AR_IMR_TXEOL 0x00000400 596#define AR_IMR_TXURN 0x00000800 597#define AR_IMR_MIB 0x00001000 598#define AR_IMR_SWI 0x00002000 599#define AR_IMR_RXPHY 0x00004000 600#define AR_IMR_RXKCM 0x00008000 601#define AR_IMR_SWBA 0x00010000 602#define AR_IMR_BRSSI 0x00020000 603#define AR_IMR_BMISS 0x00040000 604#define AR_IMR_TXMINTR 0x00080000 605#define AR_IMR_BNR 0x00100000 606#define AR_IMR_RXCHIRP 0x00200000 607#define AR_IMR_BCNMISC 0x00800000 608#define AR_IMR_TIM 0x00800000 609#define AR_IMR_RXMINTR 0x01000000 610#define AR_IMR_QCBROVF 0x02000000 611#define AR_IMR_QCBRURN 0x04000000 612#define AR_IMR_QTRIG 0x08000000 613#define AR_IMR_GENTMR 0x10000000 614#define AR_IMR_TXINTM 0x40000000 615#define AR_IMR_RXINTM 0x80000000 616 617#define AR_IMR_DEFAULT \ 618 (AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR | \ 619 AR_IMR_RXORN | AR_IMR_BCNMISC | AR_IMR_RXINTM | \ 620 AR_IMR_RXMINTR | AR_IMR_TXOK) 621#define AR_IMR_HOSTAP (AR_IMR_DEFAULT | AR_IMR_MIB) 622 623/* Bits for AR_IMR_S0. */ 624#define AR_IMR_S0_QCU_TXOK(qid) (1 << (qid)) 625#define AR_IMR_S0_QCU_TXDESC(qid) (1 << (16 + (qid))) 626 627/* Bits for AR_IMR_S1. */ 628#define AR_IMR_S1_QCU_TXERR(qid) (1 << (qid)) 629#define AR_IMR_S1_QCU_TXEOL(qid) (1 << (16 + (qid))) 630 631/* Bits for AR_IMR_S2. */ 632#define AR_IMR_S2_QCU_TXURN(qid) (1 << (qid)) 633#define AR_IMR_S2_CST 0x00400000 634#define AR_IMR_S2_GTT 0x00800000 635#define AR_IMR_S2_TIM 0x01000000 636#define AR_IMR_S2_CABEND 0x02000000 637#define AR_IMR_S2_DTIMSYNC 0x04000000 638#define AR_IMR_S2_BCNTO 0x08000000 639#define AR_IMR_S2_CABTO 0x10000000 640#define AR_IMR_S2_DTIM 0x20000000 641#define AR_IMR_S2_TSFOOR 0x40000000 642 643/* Bits for AR_IMR_S3. */ 644#define AR_IMR_S3_QCU_QCBROVF(qid) (1 << (qid)) 645#define AR_IMR_S3_QCU_QCBRURN(qid) (1 << (16 + (qid))) 646 647/* Bits for AR_IMR_S4. */ 648#define AR_IMR_S4_QCU_QTRIG(qid) (1 << (qid)) 649 650/* Bits for AR_IMR_S5. */ 651#define AR_IMR_S5_TIM_TIMER 0x00000010 652#define AR_IMR_S5_DTIM_TIMER 0x00000020 653#define AR_IMR_S5_TIMER_TRIG_M 0x000000ff 654#define AR_IMR_S5_TIMER_TRIG_S 0 655#define AR_IMR_S5_TIMER_THRESH_M 0x0000ff00 656#define AR_IMR_S5_TIMER_THRESH_S 0 657 658#define AR_NUM_QCU 10 659#define AR_QCU(x) (1 << (x)) 660 661/* Bits for AR_Q_TXE. */ 662#define AR_Q_TXE_M 0x000003ff 663#define AR_Q_TXE_S 0 664 665/* Bits for AR_Q_TXD. */ 666#define AR_Q_TXD_M 0x000003ff 667#define AR_Q_TXD_S 0 668 669/* Bits for AR_QCBRCFG_*. */ 670#define AR_Q_CBRCFG_INTERVAL_M 0x00ffffff 671#define AR_Q_CBRCFG_INTERVAL_S 0 672#define AR_Q_CBRCFG_OVF_THRESH_M 0xff000000 673#define AR_Q_CBRCFG_OVF_THRESH_S 24 674 675/* Bits for AR_Q_RDYTIMECFG_*. */ 676#define AR_Q_RDYTIMECFG_DURATION_M 0x00ffffff 677#define AR_Q_RDYTIMECFG_DURATION_S 0 678#define AR_Q_RDYTIMECFG_EN 0x01000000 679 680/* Bits for AR_Q_MISC_*. */ 681#define AR_Q_MISC_FSP_M 0x0000000f 682#define AR_Q_MISC_FSP_S 0 683#define AR_Q_MISC_FSP_ASAP 0 684#define AR_Q_MISC_FSP_CBR 1 685#define AR_Q_MISC_FSP_DBA_GATED 2 686#define AR_Q_MISC_FSP_TIM_GATED 3 687#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 688#define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 689#define AR_Q_MISC_ONE_SHOT_EN 0x00000010 690#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 691#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 692#define AR_Q_MISC_BEACON_USE 0x00000080 693#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 694#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 695#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 696#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 697 698/* Bits for AR_Q_STS_*. */ 699#define AR_Q_STS_PEND_FR_CNT_M 0x00000003 700#define AR_Q_STS_PEND_FR_CNT_S 0 701#define AR_Q_STS_CBR_EXP_CNT_M 0x0000ff00 702#define AR_Q_STS_CBR_EXP_CNT_S 8 703 704#define AR_NUM_DCU 10 705#define AR_DCU(x) (1 << (x)) 706 707/* Bits for AR_D_QCUMASK_*. */ 708#define AR_D_QCUMASK_M 0x000003ff 709#define AR_D_QCUMASK_S 0 710 711/* Bits for AR_D_GBL_IFS_SIFS. */ 712#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003ab 713 714/* Bits for AR_D_TXBLK_CMD. */ 715#define AR_D_TXBLK_WRITE_BITMASK_M 0x0000ffff 716#define AR_D_TXBLK_WRITE_BITMASK_S 0 717#define AR_D_TXBLK_WRITE_SLICE_M 0x000f0000 718#define AR_D_TXBLK_WRITE_SLICE_S 16 719#define AR_D_TXBLK_WRITE_DCU_M 0x00f00000 720#define AR_D_TXBLK_WRITE_DCU_S 20 721#define AR_D_TXBLK_WRITE_COMMAND_M 0x0f000000 722#define AR_D_TXBLK_WRITE_COMMAND_S 24 723 724/* Bits for AR_DLCL_IFS. */ 725#define AR_D_LCL_IFS_CWMIN_M 0x000003ff 726#define AR_D_LCL_IFS_CWMIN_S 0 727#define AR_D_LCL_IFS_CWMAX_M 0x000ffc00 728#define AR_D_LCL_IFS_CWMAX_S 10 729#define AR_D_LCL_IFS_AIFS_M 0x0ff00000 730#define AR_D_LCL_IFS_AIFS_S 20 731 732/* Bits for AR_D_GBL_IFS_SLOT. */ 733#define AR_D_GBL_IFS_SLOT_M 0x0000ffff 734#define AR_D_GBL_IFS_SLOT_S 0 735#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 736 737/* Bits for AR_DRETRY_LIMIT_*. */ 738#define AR_D_RETRY_LIMIT_FR_SH_M 0x0000000f 739#define AR_D_RETRY_LIMIT_FR_SH_S 0 740#define AR_D_RETRY_LIMIT_STA_SH_M 0x00003f00 741#define AR_D_RETRY_LIMIT_STA_SH_S 8 742#define AR_D_RETRY_LIMIT_STA_LG_M 0x000fc000 743#define AR_D_RETRY_LIMIT_STA_LG_S 14 744 745/* Bits for AR_D_GBL_IFS_EIFS. */ 746#define AR_D_GBL_IFS_EIFS_M 0x0000ffff 747#define AR_D_GBL_IFS_EIFS_S 0 748#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000a5eb 749 750/* Bits for AR_DCHNTIME_*. */ 751#define AR_D_CHNTIME_DUR_M 0x000fffff 752#define AR_D_CHNTIME_DUR_S 0 753#define AR_D_CHNTIME_EN 0x00100000 754 755/* Bits for AR_D_GBL_IFS_MISC. */ 756#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 757#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 758#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000ffc00 759#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 760#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 761#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 762#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 763#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 764 765/* Bits for AR_DMISC_*. */ 766#define AR_D_MISC_BKOFF_THRESH_M 0x0000003f 767#define AR_D_MISC_BKOFF_THRESH_S 0 768#define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 769#define AR_D_MISC_CW_RESET_EN 0x00000080 770#define AR_D_MISC_FRAG_WAIT_EN 0x00000100 771#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 772#define AR_D_MISC_CW_BKOFF_EN 0x00001000 773#define AR_D_MISC_VIR_COL_HANDLING_M 0x0000c000 774#define AR_D_MISC_VIR_COL_HANDLING_S 14 775#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 776#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 777#define AR_D_MISC_BEACON_USE 0x00010000 778#define AR_D_MISC_ARB_LOCKOUT_CNTRL_M 0x00060000 779#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 780#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 781#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 782#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 783#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 784#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 785#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 786#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 787#define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 788 789/* Bits for AR_D_FPCTL. */ 790#define AR_D_FPCTL_DCU_M 0x0000000f 791#define AR_D_FPCTL_DCU_S 0 792#define AR_D_FPCTL_PREFETCH_EN 0x00000010 793#define AR_D_FPCTL_BURST_PREFETCH_M 0x00007fe0 794#define AR_D_FPCTL_BURST_PREFETCH_S 5 795 796/* Bits for AR_D_TXPSE. */ 797#define AR_D_TXPSE_CTRL_M 0x000003ff 798#define AR_D_TXPSE_CTRL_S 0 799#define AR_D_TXPSE_STATUS 0x00010000 800 801/* Bits for AR_D_TXSLOTMASK. */ 802#define AR_D_TXSLOTMASK_NUM 0x0000000f 803 804/* Bits for AR_MAC_SLEEP. */ 805#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 806 807/* Bits for AR_CFG_LED. */ 808#define AR_CFG_SCLK_RATE_IND_M 0x00000003 809#define AR_CFG_SCLK_RATE_IND_S 0 810#define AR_CFG_SCLK_32MHZ 0 811#define AR_CFG_SCLK_4MHZ 1 812#define AR_CFG_SCLK_1MHZ 2 813#define AR_CFG_SCLK_32KHZ 3 814#define AR_CFG_LED_BLINK_SLOW 0x00000008 815#define AR_CFG_LED_BLINK_THRESH_SEL_M 0x00000070 816#define AR_CFG_LED_BLINK_THRESH_SEL_S 4 817#define AR_CFG_LED_MODE_SEL_M 0x00000380 818#define AR_CFG_LED_MODE_SEL_S 7 819#define AR_CFG_LED_POWER_M 0x00000280 820#define AR_CFG_LED_POWER_S 7 821#define AR_CFG_LED_NETWORK_M 0x00000300 822#define AR_CFG_LED_NETWORK_S 7 823#define AR_CFG_LED_MODE_PROP 0 824#define AR_CFG_LED_MODE_RPROP 1 825#define AR_CFG_LED_MODE_SPLIT 2 826#define AR_CFG_LED_MODE_RAND 3 827#define AR_CFG_LED_MODE_POWER_OFF 4 828#define AR_CFG_LED_MODE_POWER_ON 5 829#define AR_CFG_LED_MODE_NETWORK_OFF 4 830#define AR_CFG_LED_MODE_NETWORK_ON 6 831#define AR_CFG_LED_ASSOC_CTL_M 0x00000c00 832#define AR_CFG_LED_ASSOC_CTL_S 10 833#define AR_CFG_LED_ASSOC_NONE 0 834#define AR_CFG_LED_ASSOC_ACTIVE 1 835#define AR_CFG_LED_ASSOC_PENDING 2 836 837/* Bit for AR_RC. */ 838#define AR_RC_AHB 0x00000001 839#define AR_RC_APB 0x00000002 840#define AR_RC_HOSTIF 0x00000100 841 842/* Bits for AR_WA. */ 843#define AR5416_WA_DEFAULT 0x0000073f 844#define AR9280_WA_DEFAULT 0x0040073b 845#define AR9285_WA_DEFAULT 0x004a05cb 846#define AR_WA_UNTIE_RESET_EN 0x00008000 847#define AR_WA_RESET_EN 0x00040000 848#define AR_WA_ANALOG_SHIFT 0x00100000 849#define AR_WA_POR_SHORT 0x00200000 850 851/* Bits for AR_PM_STATE. */ 852#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 853 854/* Bits for AR_PCIE_PM_CTRL. */ 855#define AR_PCIE_PM_CTRL_ENA 0x00080000 856 857/* Bits for AR_HOST_TIMEOUT. */ 858#define AR_HOST_TIMEOUT_APB_CNTR_M 0x0000ffff 859#define AR_HOST_TIMEOUT_APB_CNTR_S 0 860#define AR_HOST_TIMEOUT_LCL_CNTR_M 0xffff0000 861#define AR_HOST_TIMEOUT_LCL_CNTR_S 16 862 863/* Bits for AR_EEPROM. */ 864#define AR_EEPROM_ABSENT 0x00000100 865#define AR_EEPROM_CORRUPT 0x00000200 866#define AR_EEPROM_PROT_MASK_M 0x03fffc00 867#define AR_EEPROM_PROT_MASK_S 10 868 869/* Bits for AR_SREV. */ 870#define AR_SREV_ID_M 0x000000ff 871#define AR_SREV_ID_S 0 872#define AR_SREV_REVISION_M 0x00000007 873#define AR_SREV_REVISION_S 0 874#define AR_SREV_VERSION_M 0x000000f0 875#define AR_SREV_VERSION_S 4 876#define AR_SREV_VERSION2_M 0xfffc0000 877#define AR_SREV_VERSION2_S 12 /* XXX Hack. */ 878#define AR_SREV_TYPE2_M 0x0003f000 879#define AR_SREV_TYPE2_S 12 880#define AR_SREV_TYPE2_CHAIN 0x00001000 881#define AR_SREV_TYPE2_HOST_MODE 0x00002000 882#define AR_SREV_REVISION2_M 0x00000f00 883#define AR_SREV_REVISION2_S 8 884#define AR_SREV_VERSION_5416_PCI 0x00d 885#define AR_SREV_VERSION_5416_PCIE 0x00c 886#define AR_SREV_REVISION_5416_10 0 887#define AR_SREV_REVISION_5416_20 1 888#define AR_SREV_REVISION_5416_22 2 889#define AR_SREV_VERSION_9100 0x014 890#define AR_SREV_VERSION_9160 0x040 891#define AR_SREV_REVISION_9160_10 0 892#define AR_SREV_REVISION_9160_11 1 893#define AR_SREV_VERSION_9280 0x080 894#define AR_SREV_REVISION_9280_10 0 895#define AR_SREV_REVISION_9280_20 1 896#define AR_SREV_REVISION_9280_21 2 897#define AR_SREV_VERSION_9285 0x0c0 898#define AR_SREV_REVISION_9285_10 0 899#define AR_SREV_REVISION_9285_11 1 900#define AR_SREV_REVISION_9285_12 2 901#define AR_SREV_VERSION_9287 0x180 902#define AR_SREV_REVISION_9287_10 0 903#define AR_SREV_REVISION_9287_11 1 904#define AR_SREV_REVISION_9287_12 2 905 906/* Bits for AR_AHB_MODE. */ 907#define AR_AHB_EXACT_WR_EN 0x00000000 908#define AR_AHB_BUF_WR_EN 0x00000001 909#define AR_AHB_EXACT_RD_EN 0x00000000 910#define AR_AHB_CACHELINE_RD_EN 0x00000002 911#define AR_AHB_PREFETCH_RD_EN 0x00000004 912#define AR_AHB_PAGE_SIZE_1K 0x00000000 913#define AR_AHB_PAGE_SIZE_2K 0x00000008 914#define AR_AHB_PAGE_SIZE_4K 0x00000010 915#define AR_AHB_CUSTOM_BURST_M 0x000000c0 916#define AR_AHB_CUSTOM_BURST_S 6 917#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 918 919/* Bits for AR_INTR_SYNC_CAUSE. */ 920#define AR_INTR_SYNC_RTC_IRQ 0x00000001 921#define AR_INTR_SYNC_MAC_IRQ 0x00000002 922#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 923#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 924#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 925#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 926#define AR_INTR_SYNC_HOST1_PERR 0x00000040 927#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 928#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 929#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 930#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 931#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 932#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 933#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 934#define AR_INTR_SYNC_PM_ACCESS 0x00004000 935#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 936#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 937#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 938#define AR_INTR_SYNC_ALL 0x0003ffff 939#define AR_INTR_SYNC_GPIO_PIN(i) (1 << (18 + (i))) 940 941#define AR_INTR_SYNC_DEFAULT \ 942 (AR_INTR_SYNC_HOST1_FATAL | \ 943 AR_INTR_SYNC_HOST1_PERR | \ 944 AR_INTR_SYNC_RADM_CPL_EP | \ 945 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 946 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | \ 947 AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 948 AR_INTR_SYNC_RADM_CPL_TIMEOUT | \ 949 AR_INTR_SYNC_LOCAL_TIMEOUT | \ 950 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 951 952/* Bits for AR_INTR_ASYNC_CAUSE. */ 953#define AR_INTR_RTC_IRQ 0x00000001 954#define AR_INTR_MAC_IRQ 0x00000002 955#define AR_INTR_EEP_PROT_ACCESS 0x00000004 956#define AR_INTR_MAC_AWAKE 0x00020000 957#define AR_INTR_MAC_ASLEEP 0x00040000 958#define AR_INTR_GPIO_PIN(i) (1 << (18 + (i))) 959#define AR_INTR_SPURIOUS 0xffffffff 960 961/* Bits for AR_GPIO_OE_OUT. */ 962#define AR_GPIO_OE_OUT_DRV_M 0x00000003 963#define AR_GPIO_OE_OUT_DRV_S 0 964#define AR_GPIO_OE_OUT_DRV_NO 0 965#define AR_GPIO_OE_OUT_DRV_LOW 1 966#define AR_GPIO_OE_OUT_DRV_HI 2 967#define AR_GPIO_OE_OUT_DRV_ALL 3 968 969/* Bits for AR_GPIO_INTR_POL. */ 970#define AR_GPIO_INTR_POL_PIN(i) (1 << (i)) 971 972/* Bits for AR_GPIO_INPUT_EN_VAL. */ 973#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 974#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 975#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 976#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 977#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 978#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 979#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 980#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 981#define AR_GPIO_JTAG_DISABLE 0x00020000 982 983/* Bits for AR_GPIO_INPUT_MUX1. */ 984#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_M 0x00000f00 985#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 986#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_M 0x000f0000 987#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 988 989/* Bits for AR_GPIO_INPUT_MUX2. */ 990#define AR_GPIO_INPUT_MUX2_CLK25_M 0x0000000f 991#define AR_GPIO_INPUT_MUX2_CLK25_S 0 992#define AR_GPIO_INPUT_MUX2_RFSILENT_M 0x000000f0 993#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 994#define AR_GPIO_INPUT_MUX2_RTC_RESET_M 0x00000f00 995#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 996 997/* Bits for AR_GPIO_OUTPUT_MUX[1-3]. */ 998#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 999#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 1000#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 1001#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 1002#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 1003#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 1004#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 1005 1006/* Bits for AR_EEPROM_STATUS_DATA. */ 1007#define AR_EEPROM_STATUS_DATA_VAL_M 0x0000ffff 1008#define AR_EEPROM_STATUS_DATA_VAL_S 0 1009#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 1010#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 1011#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 1012#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 1013 1014/* Bits for AR_PCIE_MSI. */ 1015#define AR_PCIE_MSI_ENABLE 0x00000001 1016 1017/* Bits for AR_RTC_RC. */ 1018#define AR_RTC_RC_MAC_WARM 0x00000001 1019#define AR_RTC_RC_MAC_COLD 0x00000002 1020#define AR_RTC_RC_COLD_RESET 0x00000004 1021#define AR_RTC_RC_WARM_RESET 0x00000008 1022 1023/* Bits for AR_RTC_PLL_CONTROL. */ 1024#define AR_RTC_PLL_DIV_M 0x0000001f 1025#define AR_RTC_PLL_DIV_S 0 1026#define AR_RTC_PLL_DIV2 0x00000020 1027#define AR_RTC_PLL_REFDIV_5 0x000000c0 1028#define AR_RTC_PLL_CLKSEL_M 0x00000300 1029#define AR_RTC_PLL_CLKSEL_S 8 1030#define AR_RTC_9160_PLL_DIV_M 0x000003ff 1031#define AR_RTC_9160_PLL_DIV_S 0 1032#define AR_RTC_9160_PLL_REFDIV_M 0x00003c00 1033#define AR_RTC_9160_PLL_REFDIV_S 10 1034#define AR_RTC_9160_PLL_CLKSEL_M 0x0000c000 1035#define AR_RTC_9160_PLL_CLKSEL_S 14 1036 1037/* Bits for AR_RTC_RESET. */ 1038#define AR_RTC_RESET_EN 0x00000001 1039 1040/* Bits for AR_RTC_STATUS. */ 1041#define AR_RTC_STATUS_M 0x0000000f 1042#define AR_RTC_STATUS_S 0 1043#define AR_RTC_STATUS_SHUTDOWN 0x00000001 1044#define AR_RTC_STATUS_ON 0x00000002 1045#define AR_RTC_STATUS_SLEEP 0x00000004 1046#define AR_RTC_STATUS_WAKEUP 0x00000008 1047 1048/* Bits for AR_RTC_SLEEP_CLK. */ 1049#define AR_RTC_FORCE_DERIVED_CLK 0x00000002 1050 1051/* Bits for AR_RTC_FORCE_WAKE. */ 1052#define AR_RTC_FORCE_WAKE_EN 0x00000001 1053#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 1054 1055/* 1056 * Analog registers. 1057 */ 1058/* Bits for AR_AN_RF2G1_CH0. */ 1059#define AR_AN_RF2G1_CH0_OB_M 0x03800000 1060#define AR_AN_RF2G1_CH0_OB_S 23 1061#define AR_AN_RF2G1_CH0_DB_M 0x1c000000 1062#define AR_AN_RF2G1_CH0_DB_S 26 1063 1064/* Bits for AR_AN_RF5G1_CH0. */ 1065#define AR_AN_RF5G1_CH0_OB5_M 0x00070000 1066#define AR_AN_RF5G1_CH0_OB5_S 16 1067#define AR_AN_RF5G1_CH0_DB5_M 0x00380000 1068#define AR_AN_RF5G1_CH0_DB5_S 19 1069 1070/* Bits for AR_AN_RF2G1_CH1. */ 1071#define AR_AN_RF2G1_CH1_OB_M 0x03800000 1072#define AR_AN_RF2G1_CH1_OB_S 23 1073#define AR_AN_RF2G1_CH1_DB_M 0x1c000000 1074#define AR_AN_RF2G1_CH1_DB_S 26 1075 1076/* Bits for AR_AN_RF5G1_CH1. */ 1077#define AR_AN_RF5G1_CH1_OB5_M 0x00070000 1078#define AR_AN_RF5G1_CH1_OB5_S 16 1079#define AR_AN_RF5G1_CH1_DB5_M 0x00380000 1080#define AR_AN_RF5G1_CH1_DB5_S 19 1081 1082/* Bits for AR_AN_SYNTH9. */ 1083#define AR_AN_SYNTH9_REFDIVA_M 0xf8000000 1084#define AR_AN_SYNTH9_REFDIVA_S 27 1085 1086/* Bits for AR_AN_TOP1. */ 1087#define AR_AN_TOP1_DACLPMODE 0x00040000 1088 1089/* Bits for AR_AN_TOP2. */ 1090#define AR_AN_TOP2_XPABIAS_LVL_M 0xc0000000 1091#define AR_AN_TOP2_XPABIAS_LVL_S 30 1092#define AR_AN_TOP2_LOCALBIAS 0x00200000 1093#define AR_AN_TOP2_PWDCLKIND 0x00400000 1094 1095 1096/* Bits for AR_STA_ID1. */ 1097#define AR_STA_ID1_SADH_M 0x0000ffff 1098#define AR_STA_ID1_SADH_S 0 1099#define AR_STA_ID1_STA_AP 0x00010000 1100#define AR_STA_ID1_ADHOC 0x00020000 1101#define AR_STA_ID1_PWR_SAV 0x00040000 1102#define AR_STA_ID1_KSRCHDIS 0x00080000 1103#define AR_STA_ID1_PCF 0x00100000 1104#define AR_STA_ID1_USE_DEFANT 0x00200000 1105#define AR_STA_ID1_DEFANT_UPDATE 0x00400000 1106#define AR_STA_ID1_RTS_USE_DEF 0x00800000 1107#define AR_STA_ID1_ACKCTS_6MB 0x01000000 1108#define AR_STA_ID1_BASE_RATE_11B 0x02000000 1109#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 1110#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 1111#define AR_STA_ID1_KSRCH_MODE 0x10000000 1112#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 1113#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 1114#define AR_STA_ID1_MCAST_KSRCH 0x80000000 1115 1116/* Bits for AR_BSS_ID1. */ 1117#define AR_BSS_ID1_U16_M 0x0000ffff 1118#define AR_BSS_ID1_U16_S 0 1119#define AR_BSS_ID1_AID_M 0x07ff0000 1120#define AR_BSS_ID1_AID_S 16 1121 1122/* Bits for AR_TIME_OUT. */ 1123#define AR_TIME_OUT_ACK_M 0x00003fff 1124#define AR_TIME_OUT_ACK_S 0 1125#define AR_TIME_OUT_CTS_M 0x3fff0000 1126#define AR_TIME_OUT_CTS_S 16 1127#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001d56 1128 1129/* Bits for AR_RSSI_THR. */ 1130#define AR_RSSI_THR_M 0x000000ff 1131#define AR_RSSI_THR_S 0 1132#define AR_RSSI_THR_BM_THR_M 0x0000ff00 1133#define AR_RSSI_THR_BM_THR_S 8 1134#define AR_RSSI_BCN_WEIGHT_M 0x1f000000 1135#define AR_RSSI_BCN_WEIGHT_S 24 1136#define AR_RSSI_BCN_RSSI_RST 0x20000000 1137 1138/* Bits for AR_USEC. */ 1139#define AR_USEC_USEC_M 0x0000007f 1140#define AR_USEC_USEC_S 0 1141#define AR_USEC_TX_LAT_M 0x007fc000 1142#define AR_USEC_TX_LAT_S 14 1143#define AR_USEC_RX_LAT_M 0x1f800000 1144#define AR_USEC_RX_LAT_S 23 1145#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 1146 1147/* Bits for AR_RESET_TSF. */ 1148#define AR_RESET_TSF_ONCE 0x01000000 1149 1150/* Bits for AR_RX_FILTER. */ 1151#define AR_RX_FILTER_UCAST 0x00000001 1152#define AR_RX_FILTER_MCAST 0x00000002 1153#define AR_RX_FILTER_BCAST 0x00000004 1154#define AR_RX_FILTER_CONTROL 0x00000008 1155#define AR_RX_FILTER_BEACON 0x00000010 1156#define AR_RX_FILTER_PROM 0x00000020 1157#define AR_RX_FILTER_PROBEREQ 0x00000080 1158#define AR_RX_FILTER_MYBEACON 0x00000200 1159#define AR_RX_FILTER_COMPR_BAR 0x00000400 1160#define AR_RX_FILTER_PSPOLL 0x00004000 1161 1162/* Bits for AR_DIAG_SW. */ 1163#define AR_DIAG_CACHE_ACK 0x00000001 1164#define AR_DIAG_ACK_DIS 0x00000002 1165#define AR_DIAG_CTS_DIS 0x00000004 1166#define AR_DIAG_ENCRYPT_DIS 0x00000008 1167#define AR_DIAG_DECRYPT_DIS 0x00000010 1168#define AR_DIAG_RX_DIS 0x00000020 1169#define AR_DIAG_LOOP_BACK 0x00000040 1170#define AR_DIAG_CORR_FCS 0x00000080 1171#define AR_DIAG_CHAN_INFO 0x00000100 1172#define AR_DIAG_SCRAM_SEED_M 0x0001fe00 1173#define AR_DIAG_SCRAM_SEED_S 8 /* XXX should be 9? */ 1174#define AR_DIAG_FRAME_NV0 0x00020000 1175#define AR_DIAG_OBS_PT_SEL1_M 0x000c0000 1176#define AR_DIAG_OBS_PT_SEL1_S 18 1177#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 1178#define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1179#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1180#define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1181#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1182#define AR_DIAG_RX_ABORT 0x02000000 1183#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1184#define AR_DIAG_OBS_PT_SEL2 0x08000000 1185#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1186#define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 1187 1188/* Bits for AR_AES_MUTE_MASK0. */ 1189#define AR_AES_MUTE_MASK0_FC_M 0x0000ffff 1190#define AR_AES_MUTE_MASK0_FC_S 0 1191#define AR_AES_MUTE_MASK0_QOS_M 0xffff0000 1192#define AR_AES_MUTE_MASK0_QOS_S 16 1193 1194/* Bits for AR_AES_MUTE_MASK1. */ 1195#define AR_AES_MUTE_MASK1_SEQ_M 0x0000ffff 1196#define AR_AES_MUTE_MASK1_SEQ_S 0 1197#define AR_AES_MUTE_MASK1_FC_MGMT_M 0xffff0000 1198#define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1199#define AR_AES_MUTE_MASK1_FC0_MGMT_M 0x00ff0000 1200#define AR_AES_MUTE_MASK1_FC0_MGMT_S 16 1201#define AR_AES_MUTE_MASK1_FC1_MGMT_M 0xff000000 1202#define AR_AES_MUTE_MASK1_FC1_MGMT_S 24 1203 1204/* Bits for AR_GATED_CLKS. */ 1205#define AR_GATED_CLKS_TX 0x00000002 1206#define AR_GATED_CLKS_RX 0x00000004 1207#define AR_GATED_CLKS_REG 0x00000008 1208 1209/* Bits for AR_OBS_BUS_CTRL. */ 1210#define AR_OBS_BUS_SEL_1 0x00040000 1211#define AR_OBS_BUS_SEL_2 0x00080000 1212#define AR_OBS_BUS_SEL_3 0x000c0000 1213#define AR_OBS_BUS_SEL_4 0x08040000 1214#define AR_OBS_BUS_SEL_5 0x08080000 1215 1216/* Bits for AR_OBS_BUS_1. */ 1217#define AR_OBS_BUS_1_PCU 0x00000001 1218#define AR_OBS_BUS_1_RX_END 0x00000002 1219#define AR_OBS_BUS_1_RX_WEP 0x00000004 1220#define AR_OBS_BUS_1_RX_BEACON 0x00000008 1221#define AR_OBS_BUS_1_RX_FILTER 0x00000010 1222#define AR_OBS_BUS_1_TX_HCF 0x00000020 1223#define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1224#define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1225#define AR_OBS_BUS_1_TX_HOLD 0x00000100 1226#define AR_OBS_BUS_1_TX_FRAME 0x00000200 1227#define AR_OBS_BUS_1_RX_FRAME 0x00000400 1228#define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1229#define AR_OBS_BUS_1_WEP_STATE_M 0x0003f000 1230#define AR_OBS_BUS_1_WEP_STATE_S 12 1231#define AR_OBS_BUS_1_RX_STATE_M 0x01f00000 1232#define AR_OBS_BUS_1_RX_STATE_S 20 1233#define AR_OBS_BUS_1_TX_STATE_M 0x7e000000 1234#define AR_OBS_BUS_1_TX_STATE_S 25 1235 1236/* Bits for AR_SLEEP1. */ 1237#define AR_SLEEP1_ASSUME_DTIM 0x00080000 1238#define AR_SLEEP1_CAB_TIMEOUT_M 0xffe00000 1239#define AR_SLEEP1_CAB_TIMEOUT_S 21 1240/* Default value. */ 1241#define AR_CAB_TIMEOUT_VAL 10 1242 1243/* Bits for AR_SLEEP2. */ 1244#define AR_SLEEP2_BEACON_TIMEOUT_M 0xffe00000 1245#define AR_SLEEP2_BEACON_TIMEOUT_S 21 1246 1247/* Bits for AR_TPC. */ 1248#define AR_TPC_ACK_M 0x0000003f 1249#define AR_TPC_ACK_S 0 1250#define AR_TPC_CTS_M 0x00003f00 1251#define AR_TPC_CTS_S 8 1252#define AR_TPC_CHIRP_M 0x003f0000 1253#define AR_TPC_CHIRP_S 16 1254 1255/* Bits for AR_QUIET1. */ 1256#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1257#define AR_QUIET1_NEXT_QUIET_S 0 1258#define AR_QUIET1_QUIET_ENABLE 0x00010000 1259#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 1260 1261/* Bits for AR_QUIET2. */ 1262#define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1263#define AR_QUIET2_QUIET_PERIOD_S 0 1264#define AR_QUIET2_QUIET_DUR_M 0xffff0000 1265#define AR_QUIET2_QUIET_DUR_S 16 1266 1267/* Bits for AR_TSF_PARM. */ 1268#define AR_TSF_INCREMENT_M 0x000000ff 1269#define AR_TSF_INCREMENT_S 0 1270 1271/* Bits for AR_QOS_NO_ACK. */ 1272#define AR_QOS_NO_ACK_TWO_BIT_M 0x0000000f 1273#define AR_QOS_NO_ACK_TWO_BIT_S 0 1274#define AR_QOS_NO_ACK_BIT_OFF_M 0x0000007f 1275#define AR_QOS_NO_ACK_BIT_OFF_S 4 1276#define AR_QOS_NO_ACK_BYTE_OFF_M 0x00000180 1277#define AR_QOS_NO_ACK_BYTE_OFF_S 7 1278 1279/* Bits for AR_PHY_ERR. */ 1280#define AR_PHY_ERR_DCHIRP 0x00000008 1281#define AR_PHY_ERR_RADAR 0x00000020 1282#define AR_PHY_ERR_OFDM_TIMING 0x00020000 1283#define AR_PHY_ERR_CCK_TIMING 0x02000000 1284 1285/* Bits for AR_PCU_MISC. */ 1286#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 1287#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 1288#define AR_PCU_TX_ADD_TSF 0x00000008 1289#define AR_PCU_CCK_SIFS_MODE 0x00000010 1290#define AR_PCU_RX_ANT_UPDT 0x00000800 1291#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 1292#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 1293#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 1294#define AR_PCU_FORCE_QUIET_COLL 0x00040000 1295#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1296#define AR_PCU_TBTT_PROTECT 0x00200000 1297#define AR_PCU_CLEAR_VMF 0x01000000 1298#define AR_PCU_CLEAR_BA_VALID 0x04000000 1299 1300/* Bits for AR_BT_COEX_MODE. */ 1301#define AR_BT_TIME_EXTEND_M 0x000000ff 1302#define AR_BT_TIME_EXTEND_S 0 1303#define AR_BT_TXSTATE_EXTEND 0x00000100 1304#define AR_BT_TX_FRAME_EXTEND 0x00000200 1305#define AR_BT_MODE_M 0x00000c00 1306#define AR_BT_MODE_S 10 1307#define AR_BT_MODE_LEGACY 0 1308#define AR_BT_MODE_UNSLOTTED 1 1309#define AR_BT_MODE_SLOTTED 2 1310#define AR_BT_MODE_DISABLED 3 1311#define AR_BT_QUIET 0x00001000 1312#define AR_BT_QCU_THRESH_M 0x0001e000 1313#define AR_BT_QCU_THRESH_S 13 1314#define AR_BT_RX_CLEAR_POLARITY 0x00020000 1315#define AR_BT_PRIORITY_TIME_M 0x00fc0000 1316#define AR_BT_PRIORITY_TIME_S 18 1317#define AR_BT_FIRST_SLOT_TIME_M 0xff000000 1318#define AR_BT_FIRST_SLOT_TIME_S 24 1319 1320/* Bits for AR_BT_COEX_WEIGHT. */ 1321#define AR_BTCOEX_BT_WGHT_M 0x0000ffff 1322#define AR_BTCOEX_BT_WGHT_S 0 1323#define AR_STOMP_LOW_BT_WGHT 0xff55 1324#define AR_BTCOEX_WL_WGHT_M 0xffff0000 1325#define AR_BTCOEX_WL_WGHT_S 16 1326#define AR_STOMP_LOW_WL_WGHT 0xaaa8 1327 1328/* Bits for AR_BT_COEX_MODE2. */ 1329#define AR_BT_BCN_MISS_THRESH_M 0x000000ff 1330#define AR_BT_BCN_MISS_THRESH_S 0 1331#define AR_BT_BCN_MISS_CNT_M 0x0000ff00 1332#define AR_BT_BCN_MISS_CNT_S 8 1333#define AR_BT_HOLD_RX_CLEAR 0x00010000 1334#define AR_BT_DISABLE_BT_ANT 0x00100000 1335 1336/* Bits for AR_PCU_TXBUF_CTRL. */ 1337#define AR_PCU_TXBUF_CTRL_SIZE_M 0x000007ff 1338#define AR_PCU_TXBUF_CTRL_SIZE_S 0 1339#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 1792 1340#define AR9285_PCU_TXBUF_CTRL_USABLE_SIZE (1792 / 2) 1341 1342/* Bits for AR_PCU_MISC_MODE2. */ 1343#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 1344#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 1345#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 1346#define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 1347#define AR_PCU_MISC_MODE2_MGMT_QOS_M 0x0000ff00 1348#define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 1349#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DUR 0x00010000 1350#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 1351#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 1352#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 1353 1354/* Bits for AR_MAC_PCU_LOGIC_ANALYZER. */ 1355#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1356 1357/* Bits for AR_MAC_PCU_ASYNC_FIFO_REG3. */ 1358#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 1359#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 1360 1361/* Bits for AR_PHY_ERR_[123]. */ 1362#define AR_PHY_ERR_COUNT_M 0x00ffffff 1363#define AR_PHY_ERR_COUNT_S 0 1364 1365/* Bits for AR_TSFOOR_THRESHOLD. */ 1366#define AR_TSFOOR_THRESHOLD_VAL_M 0x0000ffff 1367#define AR_TSFOOR_THRESHOLD_VAL_S 0 1368 1369/* Bit for AR_TXSIFS. */ 1370#define AR_TXSIFS_TIME_M 0x000000ff 1371#define AR_TXSIFS_TIME_S 0 1372#define AR_TXSIFS_TX_LATENCY_M 0x00000f00 1373#define AR_TXSIFS_TX_LATENCY_S 8 1374#define AR_TXSIFS_ACK_SHIFT_M 0x00007000 1375#define AR_TXSIFS_ACK_SHIFT_S 12 1376 1377/* Bits for AR_TXOP_X. */ 1378#define AR_TXOP_X_VAL 0x000000ff 1379 1380/* Bits for AR_TIMER_MODE. */ 1381#define AR_TBTT_TIMER_EN 0x00000001 1382#define AR_DBA_TIMER_EN 0x00000002 1383#define AR_SWBA_TIMER_EN 0x00000004 1384#define AR_HCF_TIMER_EN 0x00000008 1385#define AR_TIM_TIMER_EN 0x00000010 1386#define AR_DTIM_TIMER_EN 0x00000020 1387#define AR_QUIET_TIMER_EN 0x00000040 1388#define AR_NDP_TIMER_EN 0x00000080 1389#define AR_TIMER_OVERFLOW_INDEX_M 0x00000700 1390#define AR_TIMER_OVERFLOW_INDEX_S 8 1391#define AR_TIMER_THRESH_M 0xfffff000 1392#define AR_TIMER_THRESH_S 12 1393 1394/* Bits for AR_SLP32_MODE. */ 1395#define AR_SLP32_HALF_CLK_LATENCY_M 0x000fffff 1396#define AR_SLP32_HALF_CLK_LATENCY_S 0 1397#define AR_SLP32_ENA 0x00100000 1398#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 1399 1400/* Bits for AR_SLP32_WAKE. */ 1401#define AR_SLP32_WAKE_XTL_TIME_M 0x0000ffff 1402#define AR_SLP32_WAKE_XTL_TIME_S 0 1403 1404/* Bits for AR_SLP_MIB_CTRL. */ 1405#define AR_SLP_MIB_CLEAR 0x00000001 1406#define AR_SLP_MIB_PENDING 0x00000002 1407 1408/* Bits for AR_2040_MODE. */ 1409#define AR_2040_JOINED_RX_CLEAR 0x00000001 1410 1411/* Bits for AR_KEYTABLE_TYPE. */ 1412#define AR_KEYTABLE_TYPE_M 0x00000007 1413#define AR_KEYTABLE_TYPE_S 0 1414#define AR_KEYTABLE_TYPE_40 0 1415#define AR_KEYTABLE_TYPE_104 1 1416#define AR_KEYTABLE_TYPE_128 3 1417#define AR_KEYTABLE_TYPE_TKIP 4 1418#define AR_KEYTABLE_TYPE_AES 5 1419#define AR_KEYTABLE_TYPE_CCM 6 1420#define AR_KEYTABLE_TYPE_CLR 7 1421#define AR_KEYTABLE_ANT 0x00000008 1422#define AR_KEYTABLE_VALID 0x00008000 1423 1424 1425 1426/* Bits for AR_PHY_TEST. */ 1427#define AR_PHY_TEST_RFSILENT_BB 0x00002000 1428#define AR_PHY_TEST_AGC_CLR 0x10000000 1429 1430/* Bits for AR_PHY_TURBO. */ 1431#define AR_PHY_FC_TURBO_MODE 0x00000001 1432#define AR_PHY_FC_TURBO_SHORT 0x00000002 1433#define AR_PHY_FC_DYN2040_EN 0x00000004 1434#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 1435#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 1436#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 1437#define AR_PHY_FC_HT_EN 0x00000040 1438#define AR_PHY_FC_SHORT_GI_40 0x00000080 1439#define AR_PHY_FC_WALSH 0x00000100 1440#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 1441#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 1442 1443/* Bits for AR_PHY_TIMING3. */ 1444#define AR_PHY_TIMING3_DSC_MAN_M 0xfffe0000 1445#define AR_PHY_TIMING3_DSC_MAN_S 17 1446#define AR_PHY_TIMING3_DSC_EXP_M 0x0001e000 1447#define AR_PHY_TIMING3_DSC_EXP_S 13 1448 1449/* Bits for AR_PHY_CHIP_ID. */ 1450#define AR_PHY_CHIP_ID_REV_0 0x80 1451#define AR_PHY_CHIP_ID_REV_1 0x81 1452#define AR_PHY_CHIP_ID_9160_REV_0 0xb0 1453 1454/* Bits for AR_PHY_ACTIVE. */ 1455#define AR_PHY_ACTIVE_EN 0x00000001 1456#define AR_PHY_ACTIVE_DIS 0x00000000 1457 1458/* Bits for AR_PHY_RF_CTL2. */ 1459#define AR_PHY_TX_END_DATA_START_M 0x000000ff 1460#define AR_PHY_TX_END_DATA_START_S 0 1461#define AR_PHY_TX_END_PA_ON_M 0x0000ff00 1462#define AR_PHY_TX_END_PA_ON_S 8 1463 1464/* Bits for AR_PHY_RF_CTL3. */ 1465#define AR_PHY_TX_END_TO_A2_RX_ON_M 0x00ff0000 1466#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 1467 1468/* Bits for AR_PHY_ADC_CTL. */ 1469#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_M 0x00000003 1470#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 1471#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 1472#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 1473#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 1474#define AR_PHY_ADC_CTL_ON_INBUFGAIN_M 0x00030000 1475#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 1476 1477/* Bits for AR_PHY_ADC_SERIAL_CTL. */ 1478#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 1479#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 1480 1481/* Bits for AR_PHY_RF_CTL4. */ 1482#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_M 0xff000000 1483#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 1484#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_M 0x00ff0000 1485#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 1486#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_M 0x0000ff00 1487#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 1488#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_M 0x000000ff 1489#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 1490 1491/* Bits for AR_PHY_SETTLING. */ 1492#define AR_PHY_SETTLING_SWITCH_M 0x00003f80 1493#define AR_PHY_SETTLING_SWITCH_S 7 1494 1495/* Bits for AR_PHY_RXGAIN. */ 1496#define AR_PHY_RXGAIN_TXRX_ATTEN_M 0x0003f000 1497#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 1498#define AR_PHY_RXGAIN_TXRX_RF_MAX_M 0x007c0000 1499#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 1500#define AR9280_PHY_RXGAIN_TXRX_ATTEN_M 0x00003f80 1501#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 1502#define AR9280_PHY_RXGAIN_TXRX_MARGIN_M 0x001fc000 1503#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 1504 1505/* Bits for AR_PHY_DESIRED_SZ. */ 1506#define AR_PHY_DESIRED_SZ_ADC_M 0x000000ff 1507#define AR_PHY_DESIRED_SZ_ADC_S 0 1508#define AR_PHY_DESIRED_SZ_PGA_M 0x0000ff00 1509#define AR_PHY_DESIRED_SZ_PGA_S 8 1510#define AR_PHY_DESIRED_SZ_TOT_DES_M 0x0ff00000 1511#define AR_PHY_DESIRED_SZ_TOT_DES_S 20 1512 1513/* Bits for AR_PHY_FIND_SIG. */ 1514#define AR_PHY_FIND_SIG_FIRSTEP_M 0x0003f000 1515#define AR_PHY_FIND_SIG_FIRSTEP_S 12 1516#define AR_PHY_FIND_SIG_FIRPWR_M 0x03fc0000 1517#define AR_PHY_FIND_SIG_FIRPWR_S 18 1518 1519/* Bits for AR_PHY_AGC_CTL1. */ 1520#define AR_PHY_AGC_CTL1_COARSE_LOW_M 0x00007f80 1521#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 1522#define AR_PHY_AGC_CTL1_COARSE_HIGH_M 0x003f8000 1523#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 1524 1525/* Bits for AR_PHY_AGC_CONTROL. */ 1526#define AR_PHY_AGC_CONTROL_CAL 0x00000001 1527#define AR_PHY_AGC_CONTROL_NF 0x00000002 1528#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 1529#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 1530#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 1531 1532/* Bits for AR_PHY_CCA. */ 1533#define AR_PHY_MAXCCA_PWR_M 0x000001ff 1534#define AR_PHY_MAXCCA_PWR_S 0 1535#define AR_PHY_MINCCA_PWR_M 0x0ff80000 1536#define AR_PHY_MINCCA_PWR_S 19 1537#define AR_PHY_CCA_THRESH62_M 0x0007f000 1538#define AR_PHY_CCA_THRESH62_S 12 1539#define AR9280_PHY_MINCCA_PWR_M 0x1ff00000 1540#define AR9280_PHY_MINCCA_PWR_S 20 1541#define AR9280_PHY_CCA_THRESH62_M 0x000ff000 1542#define AR9280_PHY_CCA_THRESH62_S 12 1543 1544/* Bits for AR_PHY_SFCORR_LOW. */ 1545#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 1546#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M 0x00003f00 1547#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 1548#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M 0x001fc000 1549#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 1550#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M 0x0fe00000 1551#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 1552 1553/* Bits for AR_PHY_SFCORR. */ 1554#define AR_PHY_SFCORR_M2COUNT_THR_M 0x0000001f 1555#define AR_PHY_SFCORR_M2COUNT_THR_S 0 1556#define AR_PHY_SFCORR_M1_THRESH_M 0x00fe0000 1557#define AR_PHY_SFCORR_M1_THRESH_S 17 1558#define AR_PHY_SFCORR_M2_THRESH_M 0x7f000000 1559#define AR_PHY_SFCORR_M2_THRESH_S 24 1560 1561/* Bits for AR_PHY_PLL_CTL. */ 1562#define AR_PHY_PLL_CTL_40 0xaa 1563#define AR_PHY_PLL_CTL_40_5413 0x04 1564#define AR_PHY_PLL_CTL_44 0xab 1565#define AR_PHY_PLL_CTL_44_2133 0xeb 1566#define AR_PHY_PLL_CTL_40_2133 0xea 1567 1568/* Bits for AR_PHY_RX_DELAY. */ 1569#define AR_PHY_RX_DELAY_DELAY_M 0x00003fff 1570#define AR_PHY_RX_DELAY_DELAY_S 0 1571 1572/* Bits for AR_PHY_TIMING_CTRL4_0. */ 1573#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M 0x0000001f 1574#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 1575#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M 0x000007e0 1576#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 1577#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x00000800 1578#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M 0x0000f000 1579#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 1580#define AR_PHY_TIMING_CTRL4_DO_CAL 0x00010000 1581#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 1582#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 1583#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 1584#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 1585 1586/* Bits for AR_PHY_TIMING5. */ 1587#define AR_PHY_TIMING5_CYCPWR_THR1_M 0x000000fe 1588#define AR_PHY_TIMING5_CYCPWR_THR1_S 1 1589 1590/* Bits for AR_PHY_POWER_TX_RATE_MAX. */ 1591#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 1592 1593/* Bits for AR_PHY_FRAME_CTL. */ 1594#define AR_PHY_FRAME_CTL_TX_CLIP_M 0x00000038 1595#define AR_PHY_FRAME_CTL_TX_CLIP_S 3 1596 1597/* Bits for AR_PHY_TXPWRADJ. */ 1598#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_M 0x00000fc0 1599#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 1600#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_M 0x00fc0000 1601#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 1602 1603/* Bits for AR_PHY_RADAR_EXT. */ 1604#define AR_PHY_RADAR_EXT_ENA 0x00004000 1605 1606/* Bits for AR_PHY_RADAR_0. */ 1607#define AR_PHY_RADAR_0_ENA 0x00000001 1608#define AR_PHY_RADAR_0_FFT_ENA 0x80000000 1609#define AR_PHY_RADAR_0_INBAND_M 0x0000003e 1610#define AR_PHY_RADAR_0_INBAND_S 1 1611#define AR_PHY_RADAR_0_PRSSI_M 0x00000fc0 1612#define AR_PHY_RADAR_0_PRSSI_S 6 1613#define AR_PHY_RADAR_0_HEIGHT_M 0x0003f000 1614#define AR_PHY_RADAR_0_HEIGHT_S 12 1615#define AR_PHY_RADAR_0_RRSSI_M 0x00fc0000 1616#define AR_PHY_RADAR_0_RRSSI_S 18 1617#define AR_PHY_RADAR_0_FIRPWR_M 0x7f000000 1618#define AR_PHY_RADAR_0_FIRPWR_S 24 1619 1620/* Bits for AR_PHY_RADAR_1. */ 1621#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 1622#define AR_PHY_RADAR_1_USE_FIR128 0x00400000 1623#define AR_PHY_RADAR_1_RELPWR_THRESH_M 0x003f0000 1624#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 1625#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 1626#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 1627#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 1628#define AR_PHY_RADAR_1_RELSTEP_THRESH_M 0x00001f00 1629#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 1630#define AR_PHY_RADAR_1_MAXLEN_M 0x000000ff 1631#define AR_PHY_RADAR_1_MAXLEN_S 0 1632 1633/* Bits for AR_PHY_SIGMA_DELTA. */ 1634#define AR_PHY_SIGMA_DELTA_ADC_SEL_M 0x00000003 1635#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 1636#define AR_PHY_SIGMA_DELTA_FILT2_M 0x000000f8 1637#define AR_PHY_SIGMA_DELTA_FILT2_S 3 1638#define AR_PHY_SIGMA_DELTA_FILT1_M 0x00001f00 1639#define AR_PHY_SIGMA_DELTA_FILT1_S 8 1640#define AR_PHY_SIGMA_DELTA_ADC_CLIP_M 0x01ffe000 1641#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 1642 1643/* Bits for AR_PHY_RESTART. */ 1644#define AR_PHY_RESTART_DIV_GC_M 0x001c0000 1645#define AR_PHY_RESTART_DIV_GC_S 18 1646 1647/* Bits for AR_PHY_RFBUS_REQ. */ 1648#define AR_PHY_RFBUS_REQ_EN 0x00000001 1649 1650/* Bits for AR_PHY_TIMING11. */ 1651#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M 0x000fffff 1652#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 1653#define AR_PHY_TIMING11_SPUR_FREQ_SD_M 0x3ff00000 1654#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 1655#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 1656#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 1657 1658/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR(). */ 1659#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 1660#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 1661 1662/* Bits for AR_PHY_EXT_CCA0. */ 1663#define AR_PHY_EXT_CCA0_THRESH62_M 0x000000ff 1664#define AR_PHY_EXT_CCA0_THRESH62_S 0 1665 1666/* Bits for AR_PHY_EXT_CCA. */ 1667#define AR_PHY_EXT_MAXCCA_PWR_M 0x000001ff 1668#define AR_PHY_EXT_MAXCCA_PWR_S 0 1669#define AR_PHY_EXT_CCA_CYCPWR_THR1_M 0x0000fe00 1670#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 1671#define AR_PHY_EXT_CCA_THRESH62_M 0x007f0000 1672#define AR_PHY_EXT_CCA_THRESH62_S 16 1673#define AR_PHY_EXT_MINCCA_PWR_M 0xff800000 1674#define AR_PHY_EXT_MINCCA_PWR_S 23 1675#define AR9280_PHY_EXT_MINCCA_PWR_M 0x01ff0000 1676#define AR9280_PHY_EXT_MINCCA_PWR_S 16 1677 1678/* Bits for AR_PHY_SFCORR_EXT. */ 1679#define AR_PHY_SFCORR_EXT_M1_THRESH_M 0x0000007f 1680#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 1681#define AR_PHY_SFCORR_EXT_M2_THRESH_M 0x00003f80 1682#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 1683#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M 0x001fc000 1684#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 1685#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M 0x0fe00000 1686#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 1687#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_M 0xf0000000 1688#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 1689 1690/* Bits for AR_PHY_HALFGI. */ 1691#define AR_PHY_HALFGI_DSC_EXP_M 0x0000000f 1692#define AR_PHY_HALFGI_DSC_EXP_S 0 1693#define AR_PHY_HALFGI_DSC_MAN_M 0x0007fff0 1694#define AR_PHY_HALFGI_DSC_MAN_S 4 1695 1696/* Bits for AR_PHY_CHAN_INFO_MEMORY. */ 1697#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 1698 1699/* Bits for AR_PHY_HEAVY_CLIP_FACTOR_RIFS. */ 1700#define AR_PHY_RIFS_INIT_DELAY_M 0x03ff0000 1701#define AR_PHY_RIFS_INIT_DELAY_S 16 1702 1703/* Bits for AR_PHY_CALMODE. */ 1704#define AR_PHY_CALMODE_IQ 0x00000000 1705#define AR_PHY_CALMODE_ADC_GAIN 0x00000001 1706#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 1707#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 1708 1709/* Bits for AR_PHY_RFBUS_GRANT. */ 1710#define AR_PHY_RFBUS_GRANT_EN 0x00000001 1711 1712/* Bits for AR_PHY_CHAN_INFO_GAIN_DIFF. */ 1713#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 1714 1715/* Bits for AR_PHY_MODE. */ 1716#define AR_PHY_MODE_ASYNCFIFO 0x00000080 1717#define AR_PHY_MODE_AR2133 0x00000008 1718#define AR_PHY_MODE_AR5111 0x00000000 1719#define AR_PHY_MODE_AR5112 0x00000008 1720#define AR_PHY_MODE_DYNAMIC 0x00000004 1721#define AR_PHY_MODE_RF2GHZ 0x00000002 1722#define AR_PHY_MODE_RF5GHZ 0x00000000 1723#define AR_PHY_MODE_CCK 0x00000001 1724#define AR_PHY_MODE_OFDM 0x00000000 1725#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 1726 1727/* Bits for AR_PHY_CCK_TX_CTRL. */ 1728#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 1729#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_M 0x0000000c 1730#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 1731 1732/* Bits for AR_PHY_CCK_DETECT. */ 1733#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M 0x0000003f 1734#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 1735#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M 0x00001fc0 1736#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 1737#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x00002000 1738 1739/* Bits for AR_PHY_GAIN_2GHZ. */ 1740#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_M 0x00fc0000 1741#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 1742#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_M 0x00003c00 1743#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 1744#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_M 0x0000001f 1745#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 1746#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_M 0x003e0000 1747#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 1748#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_M 0x0001f000 1749#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 1750#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_M 0x00000fc0 1751#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 1752#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_M 0x0000003f 1753#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 1754 1755/* Bit for AR_PHY_CCK_RXCTRL4. */ 1756#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_M 0x01f80000 1757#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 1758 1759/* Bits for AR_PHY_DAG_CTRLCCK. */ 1760#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 1761#define AR_PHY_DAG_CTRLCCK_RSSI_THR_M 0x0001fc00 1762#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 1763 1764/* Bits for AR_PHY_FORCE_CLKEN_CCK. */ 1765#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 1766 1767/* Bits for AR_PHY_TPCRG1. */ 1768#define AR_PHY_TPCRG1_NUM_PD_GAIN_M 0x0000c000 1769#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 1770#define AR_PHY_TPCRG1_PD_GAIN_1_M 0x00030000 1771#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 1772#define AR_PHY_TPCRG1_PD_GAIN_2_M 0x000c0000 1773#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 1774#define AR_PHY_TPCRG1_PD_GAIN_3_M 0x00300000 1775#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 1776#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 1777 1778/* Bits for AR_PHY_TX_PWRCTRL4. */ 1779#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 1780#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_M 0x000001fe 1781#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1 1782 1783/* Bits for AR_PHY_TX_PWRCTRL6_[01]. */ 1784#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_M 0x03000000 1785#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24 1786 1787/* Bits for AR_PHY_TX_PWRCTRL7. */ 1788#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_M 0x01f80000 1789#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 1790 1791/* Bits for AR_PHY_TX_PWRCTRL9. */ 1792#define AR_PHY_TX_DESIRED_SCALE_CCK_M 0x00007c00 1793#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 /* XXX should be 9? */ 1794#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 1795 1796/* Bits for AR_PHY_TX_GAIN_TBL. */ 1797#define AR_PHY_TX_GAIN_M 0x0007f000 1798#define AR_PHY_TX_GAIN_S 12 1799 1800/* Bits for AR_PHY_SPUR_REG. */ 1801#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03fc0000 1802#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x00020000 1803#define AR_PHY_SPUR_REG_MASK_RATE_SELECT 0x0001fe00 1804#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x00000100 1805#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M 0x0000007f 1806#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 1807#define AR_SPUR_RSSI_THRESH 40 1808 1809/* Bits for AR_PHY_ANALOG_SWAP. */ 1810#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 1811 1812/* Bits for AR_PHY_TPCRG5. */ 1813#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_M 0x0000000f 1814#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 1815#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_M 0x000003f0 1816#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 1817#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_M 0x0000fc00 1818#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 1819#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_M 0x003f0000 1820#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 1821#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_M 0x0fc00000 1822#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 1823 1824/* Bits for AR_PHY_CL_CAL_CTL. */ 1825#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 1826#define AR_PHY_CL_CAL_ENABLE 0x00000002 1827 1828/* Bits for AR_PHY_XPA_CFG. */ 1829#define AR_PHY_FORCE_XPA_CFG 0x000000001 1830 1831/* Bits for AR_PHY_CH[01]_TX_PWRCTRL11. */ 1832#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_M 0x0000fc00 1833#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10 1834#define AR_PHY_TX_PWRCTRL_OLPC_PWR_M 0x00ff0000 1835#define AR_PHY_TX_PWRCTRL_OLPC_PWR_S 16 1836 1837/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR. */ 1838#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_M 0x0000003f 1839#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_S 0 1840#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_M 0x00000fc0 1841#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_S 6 1842#define AR_PHY_NEW_ADC_DC_GAIN_QDC_M 0x001ff000 1843#define AR_PHY_NEW_ADC_DC_GAIN_QDC_S 12 1844#define AR_PHY_NEW_ADC_DC_GAIN_IDC_M 0x3fe00000 1845#define AR_PHY_NEW_ADC_DC_GAIN_IDC_S 21 1846 1847#define AR_BASE_PHY_ACTIVE_DELAY 100 1848 1849#define AR_CLOCK_RATE_CCK 22 1850#define AR_CLOCK_RATE_5GHZ_OFDM 40 1851#define AR_CLOCK_RATE_2GHZ_OFDM 44 1852 1853#define AR_PWR_DECREASE_FOR_2_CHAIN 6 /* 10 * log10(2) * 2 */ 1854#define AR_PWR_DECREASE_FOR_3_CHAIN 9 /* 10 * log10(3) * 2 */ 1855 1856#define AR_SLEEP_SLOP 3 /* TUs */ 1857 1858#define AR_MIN_BEACON_TIMEOUT_VAL 1 1859#define AR_FUDGE 2 1860/* Divides by 1024 (usecs to TU) without doing 64-bit arithmetic. */ 1861#define AR_TSF_TO_TU(hi, lo) ((hi) << 22 | (lo) >> 10) 1862 1863#define AR_KEY_CACHE_SIZE 128 1864#define AR_RSVD_KEYTABLE_ENTRIES 4 1865 1866#define AR_CAL_SAMPLES 64 /* XXX AR9280? */ 1867#define AR_MAX_LOG_CAL 2 /* XXX AR9280? */ 1868 1869/* 1870 * Tx DMA descriptor. 1871 */ 1872struct ar_tx_desc { 1873 uint32_t ds_link; 1874 uint32_t ds_data; 1875 uint32_t ds_ctl0; 1876 uint32_t ds_ctl1; 1877 uint32_t ds_ctl2; 1878 uint32_t ds_ctl3; 1879 uint32_t ds_ctl4; 1880 uint32_t ds_ctl5; 1881 uint32_t ds_ctl6; 1882 uint32_t ds_ctl7; 1883 uint32_t ds_ctl8; 1884 uint32_t ds_ctl9; 1885 uint32_t ds_ctl10; 1886 uint32_t ds_ctl11; 1887 uint32_t ds_status0; 1888 uint32_t ds_status1; 1889 uint32_t ds_tstamp; 1890 uint32_t ds_ba_bitmap_lo; 1891 uint32_t ds_ba_bitmap_hi; 1892 uint32_t ds_evm0; 1893 uint32_t ds_evm1; 1894 uint32_t ds_evm2; 1895 uint32_t ds_status8; 1896 uint32_t ds_status9; 1897 /* 1898 * Padding to make Tx descriptors 128 bytes such that they will 1899 * not cross a 4KB boundary. 1900 */ 1901 uint32_t pad[8]; 1902} __packed; 1903 1904/* Bits for ds_ctl0. */ 1905#define AR_TXC0_FRAME_LEN_M 0x00000fff 1906#define AR_TXC0_FRAME_LEN_S 0 1907#define AR_TXC0_VIRT_MORE_FRAG 0x00001000 1908#define AR_TXC0_XMIT_POWER_M 0x003f0000 1909#define AR_TXC0_XMIT_POWER_S 16 1910#define AR_TXC0_RTS_ENABLE 0x00400000 1911#define AR_TXC0_VEOL 0x00800000 1912#define AR_TXC0_CLR_DEST_MASK 0x01000000 1913#define AR_TXC0_INTR_REQ 0x20000000 1914#define AR_TXC0_DEST_IDX_VALID 0x40000000 1915#define AR_TXC0_CTS_ENABLE 0x80000000 1916 1917/* Bits for ds_ctl1. */ 1918#define AR_TXC1_BUF_LEN_M 0x00000fff 1919#define AR_TXC1_BUF_LEN_S 0 1920#define AR_TXC1_MORE 0x00001000 1921#define AR_TXC1_DEST_IDX_M 0x000fe000 1922#define AR_TXC1_DEST_IDX_S 13 1923#define AR_TXC1_FRAME_TYPE_M 0x00f00000 1924#define AR_TXC1_FRAME_TYPE_S 20 1925#define AR_FRAME_TYPE_NORMAL 0 1926#define AR_FRAME_TYPE_ATIM 1 1927#define AR_FRAME_TYPE_PSPOLL 2 1928#define AR_FRAME_TYPE_BEACON 3 1929#define AR_FRAME_TYPE_PROBE_RESP 4 1930#define AR_TXC1_NO_ACK 0x01000000 1931#define AR_TXC1_INSERT_TS 0x02000000 1932#define AR_TXC1_EXT_ONLY 0x08000000 1933#define AR_TXC1_EXT_AND_CTL 0x10000000 1934#define AR_TXC1_MORE_AGGR 0x20000000 1935#define AR_TXC1_IS_AGGR 0x40000000 1936 1937/* Bits for ds_ctl2. */ 1938#define AR_TXC2_BURST_DUR_M 0x00007fff 1939#define AR_TXC2_BURST_DUR_S 0 1940#define AR_TXC2_DUR_UPDATE_ENA 0x00008000 1941#define AR_TXC2_XMIT_DATA_TRIES0_M 0x000f0000 1942#define AR_TXC2_XMIT_DATA_TRIES0_S 16 1943#define AR_TXC2_XMIT_DATA_TRIES1_M 0x00f00000 1944#define AR_TXC2_XMIT_DATA_TRIES1_S 20 1945#define AR_TXC2_XMIT_DATA_TRIES2_M 0x0f000000 1946#define AR_TXC2_XMIT_DATA_TRIES2_S 24 1947#define AR_TXC2_XMIT_DATA_TRIES3_M 0xf0000000 1948#define AR_TXC2_XMIT_DATA_TRIES3_S 28 1949 1950/* Bits for ds_ctl3. */ 1951#define AR_TXC3_XMIT_RATE0_M 0x000000ff 1952#define AR_TXC3_XMIT_RATE0_S 0 1953#define AR_TXC3_XMIT_RATE1_M 0x0000ff00 1954#define AR_TXC3_XMIT_RATE1_S 8 1955#define AR_TXC3_XMIT_RATE2_M 0x00ff0000 1956#define AR_TXC3_XMIT_RATE2_S 16 1957#define AR_TXC3_XMIT_RATE3_M 0xff000000 1958#define AR_TXC3_XMIT_RATE3_S 24 1959 1960/* Bits for ds_ctl4. */ 1961#define AR_TXC4_PACKET_DUR0_M 0x00007fff 1962#define AR_TXC4_PACKET_DUR0_S 0 1963#define AR_TXC4_RTSCTS_QUAL0 0x00008000 1964#define AR_TXC4_PACKET_DUR1_M 0x7fff0000 1965#define AR_TXC4_PACKET_DUR1_S 16 1966#define AR_TXC4_RTSCTS_QUAL1 0x80000000 1967/* Shortcut. */ 1968#define AR_TXC4_RTSCTS_QUAL01 \ 1969 (AR_TXC4_RTSCTS_QUAL0 | AR_TXC4_RTSCTS_QUAL1) 1970 1971/* Bits for ds_ctl5. */ 1972#define AR_TXC5_PACKET_DUR2_M 0x00007fff 1973#define AR_TXC5_PACKET_DUR2_S 0 1974#define AR_TXC5_RTSCTS_QUAL2 0x00008000 1975#define AR_TXC5_PACKET_DUR3_M 0x7fff0000 1976#define AR_TXC5_PACKET_DUR3_S 16 1977#define AR_TXC5_RTSCTS_QUAL3 0x80000000 1978/* Shortcut. */ 1979#define AR_TXC5_RTSCTS_QUAL23 \ 1980 (AR_TXC5_RTSCTS_QUAL2 | AR_TXC5_RTSCTS_QUAL3) 1981 1982/* Bits for ds_ctl6. */ 1983#define AR_TXC6_AGGR_LEN_M 0x0000ffff 1984#define AR_TXC6_AGGR_LEN_S 0 1985#define AR_TXC6_PAD_DELIM_M 0x03fc0000 1986#define AR_TXC6_PAD_DELIM_S 18 1987#define AR_TXC6_ENCR_TYPE_M 0x0c000000 1988#define AR_TXC6_ENCR_TYPE_S 26 1989#define AR_ENCR_TYPE_CLEAR 0 1990#define AR_ENCR_TYPE_WEP 1 1991#define AR_ENCR_TYPE_AES 2 1992#define AR_ENCR_TYPE_TKIP 3 1993 1994/* Bits for ds_ctl7. */ 1995#define AR_TXC7_2040_0 0x00000001 1996#define AR_TXC7_GI0 0x00000002 1997#define AR_TXC7_CHAIN_SEL0_M 0x0000001c 1998#define AR_TXC7_CHAIN_SEL0_S 2 1999#define AR_TXC7_2040_1 0x00000020 2000#define AR_TXC7_GI1 0x00000040 2001#define AR_TXC7_CHAIN_SEL1_M 0x00000380 2002#define AR_TXC7_CHAIN_SEL1_S 7 2003#define AR_TXC7_2040_2 0x00000400 2004#define AR_TXC7_GI2 0x00000800 2005#define AR_TXC7_CHAIN_SEL2_M 0x00007000 2006#define AR_TXC7_CHAIN_SEL2_S 12 2007#define AR_TXC7_2040_3 0x00008000 2008#define AR_TXC7_GI3 0x00010000 2009#define AR_TXC7_CHAIN_SEL3_M 0x000e0000 2010#define AR_TXC7_CHAIN_SEL3_S 17 2011#define AR_TXC7_RTSCTS_RATE_M 0x0ff00000 2012#define AR_TXC7_RTSCTS_RATE_S 20 2013/* Shortcuts. */ 2014#define AR_TXC7_2040_0123 \ 2015 (AR_TXC7_2040_0 | AR_TXC7_2040_1 | AR_TXC7_2040_2 | AR_TXC7_2040_3) 2016#define AR_TXC7_GI0123 \ 2017 (AR_TXC7_GI0 | AR_TXC7_GI1 | AR_TXC7_GI2 | AR_TXC7_GI3) 2018 2019/* Bits for ds_status0. */ 2020#define AR_TXS0_RSSI_ANT0(i) (((x) >> ((i) * 8)) & 0xff) 2021#define AR_TXS0_BA_STATUS 0x40000000 2022 2023/* Bits for ds_status1. */ 2024#define AR_TXS1_FRM_XMIT_OK 0x00000001 2025#define AR_TXS1_EXCESSIVE_RETRIES 0x00000002 2026#define AR_TXS1_FIFO_UNDERRUN 0x00000004 2027#define AR_TXS1_FILTERED 0x00000008 2028#define AR_TXS1_RTS_FAIL_CNT_M 0x000000f0 2029#define AR_TXS1_RTS_FAIL_CNT_S 4 2030#define AR_TXS1_DATA_FAIL_CNT_M 0x00000f00 2031#define AR_TXS1_DATA_FAIL_CNT_S 8 2032#define AR_TXS1_VIRT_RETRY_CNT_M 0x0000f000 2033#define AR_TXS1_VIRT_RETRY_CNT_S 12 2034#define AR_TXS1_TX_DELIM_UNDERRUN 0x00010000 2035#define AR_TXS1_TX_DATA_UNDERRUN 0x00020000 2036#define AR_TXS1_DESC_CFG_ERR 0x00040000 2037#define AR_TXS1_TX_TIMER_EXPIRED 0x00080000 2038/* Shortcuts. */ 2039#define AR_TXS1_UNDERRUN \ 2040 (AR_TXS1_FIFO_UNDERRUN | \ 2041 AR_TXS1_TX_DELIM_UNDERRUN | \ 2042 AR_TXS1_TX_DATA_UNDERRUN) 2043 2044/* Bits for ds_status9. */ 2045#define AR_TXS9_DONE 0x00000001 2046#define AR_TXS9_SEQNUM_M 0x00001ffe 2047#define AR_TXS9_SEQNUM_S 1 2048#define AR_TXS9_TXOP_EXCEEDED 0x00020000 2049#define AR_TXS9_FINAL_IDX_M 0x00600000 2050#define AR_TXS9_FINAL_IDX_S 21 2051#define AR_TXS9_POWER_MGMT 0x02000000 2052 2053/* 2054 * Rx DMA descriptor. 2055 */ 2056struct ar_rx_desc { 2057 uint32_t ds_link; 2058 uint32_t ds_data; 2059 uint32_t ds_ctl0; 2060 uint32_t ds_ctl1; 2061 uint32_t ds_status0; 2062 uint32_t ds_status1; 2063 uint32_t ds_status2; 2064 uint32_t ds_status3; 2065 uint32_t ds_status4; 2066 uint32_t ds_status5; 2067 uint32_t ds_status6; 2068 uint32_t ds_status7; 2069 uint32_t ds_status8; 2070 /* 2071 * Padding to make Rx descriptors 64 bytes such that they will 2072 * not cross a 4KB boundary. 2073 */ 2074 uint32_t pad[3]; 2075} __packed; 2076 2077/* Bits for ds_ctl1. */ 2078#define AR_RXC1_BUF_LEN_M 0x00000fff 2079#define AR_RXC1_BUF_LEN_S 0 2080#define AR_RXC1_INTR_REQ 0x00002000 2081 2082/* Bits for ds_ctl2. */ 2083#define AR_RXS0_RSSI_ANT00(x) (((x) >> 0) & 0xff) 2084#define AR_RXS0_RSSI_ANT01(x) (((x) >> 8) & 0xff) 2085#define AR_RXS0_RSSI_ANT02(x) (((x) >> 16) & 0xff) 2086#define AR_RXS0_RATE_M 0xff000000 2087#define AR_RXS0_RATE_S 24 2088 2089/* Bits for ds_status1. */ 2090#define AR_RXS1_DATA_LEN_M 0x00000fff 2091#define AR_RXS1_DATA_LEN_S 0 2092#define AR_RXS1_MORE 0x00001000 2093 2094/* Bits for ds_status3. */ 2095#define AR_RXS3_GI 0x00000001 2096#define AR_RXS3_2040 0x00000002 2097#define AR_RXS3_PARALLEL_40 0x00000004 2098#define AR_RXS3_ANTENNA_M 0xffffff00 2099#define AR_RXS3_ANTENNA_S 8 2100#define AR_RXS3_RATE_M 0x000003fc 2101#define AR_RXS3_RATE_S 2 2102 2103/* Bits for ds_status4. */ 2104#define AR_RXS4_RSSI_COMBINED_M 0xff000000 2105#define AR_RXS4_RSSI_COMBINED_S 24 2106 2107/* Bits for ds_status8. */ 2108#define AR_RXS8_DONE 0x00000001 2109#define AR_RXS8_FRAME_OK 0x00000002 2110#define AR_RXS8_CRC_ERR 0x00000004 2111#define AR_RXS8_DECRYPT_CRC_ERR 0x00000008 2112#define AR_RXS8_PHY_ERR 0x00000010 2113#define AR_RXS8_MICHAEL_ERR 0x00000020 2114#define AR_RXS8_PRE_DELIM_CRC_ERR 0x00000040 2115#define AR_RXS8_PHY_ERR_CODE_M 0x0000ff00 2116#define AR_RXS8_PHY_ERR_CODE_S 8 2117#define AR_RXS8_KEY_IDX_VALID 0x00000100 2118#define AR_RXS8_KEY_IDX_M 0x0000fe00 2119#define AR_RXS8_KEY_IDX_S 9 2120#define AR_RXS8_POST_DELIM_CRC_ERR 0x00040000 2121#define AR_RXS8_DECRYPT_BUSY_ERR 0x40000000 2122 2123 2124/* Maximum number of chains supported by any chipset. */ 2125#define AR_MAX_CHAINS 3 2126 2127/* Default number of key cache entries. */ 2128#define AR_KEYTABLE_SIZE 128 2129 2130/* GPIO pins. */ 2131#define AR_GPIO_WLANACTIVE_PIN 5 2132#define AR_GPIO_BTACTIVE_PIN 6 2133#define AR_GPIO_BTPRIORITY_PIN 7 2134 2135/* XXX need to cleanup that mess. */ 2136#define AR_SREV_5416(sc) \ 2137 ((sc)->mac_ver == AR_SREV_VERSION_5416_PCI || \ 2138 (sc)->mac_ver == AR_SREV_VERSION_5416_PCIE) 2139#define AR_SREV_5416_20_OR_LATER(sc) \ 2140 ((AR_SREV_5416(sc) && \ 2141 (sc)->mac_rev >= AR_SREV_REVISION_5416_20) || \ 2142 (sc)->mac_ver >= AR_SREV_VERSION_9100) 2143#define AR_SREV_5416_22_OR_LATER(sc) \ 2144 ((AR_SREV_5416(sc) && \ 2145 (sc)->mac_rev >= AR_SREV_REVISION_5416_22) || \ 2146 (sc)->mac_ver >= AR_SREV_VERSION_9100) 2147 2148#define AR_SREV_9160(sc) \ 2149 ((sc)->mac_ver == AR_SREV_VERSION_9160) 2150#define AR_SREV_9160_10_OR_LATER(sc) \ 2151 ((sc)->mac_ver >= AR_SREV_VERSION_9160) 2152#define AR_SREV_9160_11(sc) \ 2153 (AR_SREV_9160(sc) && \ 2154 (sc)->mac_rev == AR_SREV_REVISION_9160_11) 2155 2156#define AR_SREV_9280(sc) \ 2157 ((sc)->mac_ver == AR_SREV_VERSION_9280) 2158#define AR_SREV_9280_10_OR_LATER(sc) \ 2159 ((sc)->mac_ver >= AR_SREV_VERSION_9280) 2160#define AR_SREV_9280_10(sc) \ 2161 (AR_SREV_9280(sc) && \ 2162 (sc)->mac_rev == AR_SREV_REVISION_9280_10) 2163#define AR_SREV_9280_20(sc) \ 2164 (AR_SREV_9280(sc) && \ 2165 (sc)->mac_rev >= AR_SREV_REVISION_9280_20) 2166#define AR_SREV_9280_20_OR_LATER(sc) \ 2167 ((sc)->mac_ver > AR_SREV_VERSION_9280 || \ 2168 (AR_SREV_9280(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9280_20)) 2169 2170#define AR_SREV_9285(sc) \ 2171 ((sc)->mac_ver == AR_SREV_VERSION_9285) 2172#define AR_SREV_9285_10_OR_LATER(sc) \ 2173 ((sc)->mac_ver >= AR_SREV_VERSION_9285) 2174#define AR_SREV_9285_11(sc) \ 2175 (AR_SREV_9285(sc) && \ 2176 (sc)->mac_rev == AR_SREV_REVISION_9285_11) 2177#define AR_SREV_9285_11_OR_LATER(sc) \ 2178 ((sc)->mac_ver > AR_SREV_VERSION_9285 || \ 2179 (AR_SREV_9285(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9285_11)) 2180#define AR_SREV_9285_12(sc) \ 2181 (AR_SREV_9285(sc) && \ 2182 ((sc)->mac_rev == AR_SREV_REVISION_9285_12)) 2183#define AR_SREV_9285_12_OR_LATER(sc) \ 2184 ((sc)->mac_ver > AR_SREV_VERSION_9285 || \ 2185 (AR_SREV_9285(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9285_12)) 2186 2187#define AR_SREV_9287(sc) \ 2188 ((sc)->mac_ver == AR_SREV_VERSION_9287) 2189#define AR_SREV_9287_10_OR_LATER(sc) \ 2190 ((sc)->mac_ver >= AR_SREV_VERSION_9287) 2191#define AR_SREV_9287_10(sc) \ 2192 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 2193 (sc)->mac_rev == AR_SREV_REVISION_9287_10) 2194#define AR_SREV_9287_11(sc) \ 2195 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 2196 (sc)->mac_rev == AR_SREV_REVISION_9287_11) 2197#define AR_SREV_9287_11_OR_LATER(sc) \ 2198 ((sc)->mac_ver > AR_SREV_VERSION_9287 || \ 2199 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_11)) 2200#define AR_SREV_9287_12(sc) \ 2201 ((sc)->mac_ver == AR_SREV_VERSION_9287 && \ 2202 (sc)->mac_rev == AR_SREV_REVISION_9287_12) 2203#define AR_SREV_9287_12_OR_LATER(sc) \ 2204 ((sc)->mac_ver > AR_SREV_VERSION_9287 || \ 2205 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_12)) 2206 2207#define AR_SINGLE_CHIP(sc) AR_SREV_9280_10_OR_LATER(sc) 2208 2209#define AR_RADIO_SREV_MAJOR 0xf0 2210#define AR_RAD5133_SREV_MAJOR 0xc0 2211#define AR_RAD2133_SREV_MAJOR 0xd0 2212#define AR_RAD5122_SREV_MAJOR 0xe0 2213#define AR_RAD2122_SREV_MAJOR 0xf0 2214 2215/* 2216 * Common ROM structures. 2217 */ 2218#define AR_EEPROM_MAGIC_OFFSET 0x0000 2219#if BYTE_ORDER == BIG_ENDIAN 2220#define AR_EEPROM_MAGIC 0x5aa5 2221#else 2222#define AR_EEPROM_MAGIC 0xa55a 2223#endif 2224 2225#define AR_BCHAN_UNUSED 0xff 2226#define AR_NO_SPUR 0x8000 2227 2228#define AR_NUM_PDADC_VALUES 128 2229#define AR_PD_GAINS_IN_MASK 4 /* NB: Max for all chips. */ 2230 2231#define AR_MAX_PWR_RANGE_IN_HALF_DB 64 2232 2233#define AR_MAX_RATE_POWER 63 2234 2235#define AR_HT40_POWER_INC_FOR_PDADC 2 2236 2237#define AR_EEPROM_MODAL_SPURS 5 2238 2239#define AR_BASE_FREQ_2GHZ 2300 2240#define AR_BASE_FREQ_5GHZ 4900 2241 2242#define AR_PWR_TABLE_OFFSET_DB (-5) 2243 2244/* XXX does not belong here!!! */ 2245#define AR9285_PD_GAIN_BOUNDARY_DEFAULT 58 2246#define AR9280_TX_GAIN_TABLE_SIZE 22 2247 2248#define AR_EEP_TXGAIN_ORIGINAL 0 2249#define AR_EEP_TXGAIN_HIGH_POWER 1 2250 2251/* 2252 * ROM header that is common to all existing ROM layouts. 2253 */ 2254struct ar_base_eep_header { 2255 uint16_t length; 2256 uint16_t checksum; 2257 uint16_t version; 2258#define AR_EEP_VER 0xe 2259#define AR_EEP_VER_MINOR_MASK 0x0fff 2260#define AR_EEP_MINOR_VER_2 2 2261#define AR_EEP_MINOR_VER_3 3 2262#define AR_EEP_MINOR_VER_7 7 2263#define AR_EEP_MINOR_VER_9 9 2264#define AR_EEP_MINOR_VER_10 10 2265#define AR_EEP_MINOR_VER_16 16 2266#define AR_EEP_MINOR_VER_17 17 2267#define AR_EEP_MINOR_VER_19 19 2268#define AR_EEP_MINOR_VER_20 20 2269#define AR_EEP_MINOR_VER_21 21 2270#define AR_EEP_MINOR_VER_22 22 2271 2272 uint8_t opCapFlags; 2273#define AR_OPFLAGS_11A 0x01 2274#define AR_OPFLAGS_11G 0x02 2275#define AR_OPFLAGS_11N_5G40 0x04 2276#define AR_OPFLAGS_11N_2G40 0x08 2277#define AR_OPFLAGS_11N_5G20 0x10 2278#define AR_OPFLAGS_11N_2G20 0x20 2279/* Shortcut. */ 2280#define AR_OPFLAGS_11N 0x3c 2281 2282 uint8_t eepMisc; 2283 uint16_t regDmn[2]; 2284 uint8_t macAddr[6]; 2285 uint8_t rxMask; 2286 uint8_t txMask; 2287 uint16_t rfSilent; 2288#define AR_EEP_RFSILENT_ENABLED 0x0001 2289#define AR_EEP_RFSILENT_GPIO_SEL_M 0x001c 2290#define AR_EEP_RFSILENT_GPIO_SEL_S 2 2291#define AR_EEP_RFSILENT_POLARITY 0x0002 2292 2293 uint16_t blueToothOptions; 2294 uint16_t deviceCap; 2295#define AR_EEP_DEVCAP_COMPRESS_DIS 0x0001 2296#define AR_EEP_DEVCAP_AES_DIS 0x0002 2297#define AR_EEP_DEVCAP_FASTFRAME_DIS 0x0004 2298#define AR_EEP_DEVCAP_BURST_DIS 0x0008 2299#define AR_EEP_DEVCAP_MAXQCU_M 0x01f0 2300#define AR_EEP_DEVCAP_MAXQCU_S 4 2301#define AR_EEP_DEVCAP_HEAVY_CLIP_EN 0x0200 2302#define AR_EEP_DEVCAP_KC_ENTRIES_M 0xf000 2303#define AR_EEP_DEVCAP_KC_ENTRIES_S 12 2304 2305 uint32_t binBuildNumber; 2306 uint8_t deviceType; 2307} __packed; 2308 2309struct ar_spur_chan { 2310 uint16_t spurChan; 2311 uint8_t spurRangeLow; 2312 uint8_t spurRangeHigh; 2313} __packed; 2314 2315struct ar_cal_data_per_freq_olpc { 2316 uint8_t pwrPdg[2][5]; 2317 uint8_t vpdPdg[2][5]; 2318 uint8_t pcdac[2][5]; 2319 uint8_t empty[2][5]; 2320} __packed; 2321 2322struct ar_cal_target_power_leg { 2323 uint8_t bChannel; 2324 uint8_t tPow2x[4]; 2325} __packed; 2326 2327struct ar_cal_target_power_ht { 2328 uint8_t bChannel; 2329 uint8_t tPow2x[8]; 2330} __packed; 2331 2332struct ar_cal_ctl_edges { 2333 uint8_t bChannel; 2334 uint8_t tPowerFlag; 2335#define AR_CAL_CTL_EDGES_POWER_M 0x3f 2336#define AR_CAL_CTL_EDGES_POWER_S 0 2337#define AR_CAL_CTL_EDGES_FLAG_M 0xc0 2338#define AR_CAL_CTL_EDGES_FLAG_S 6 2339} __packed; 2340 2341#define AR_SD_NO_CTL 0xe0 2342#define AR_NO_CTL 0xff 2343#define AR_CTL_MODE_M 0x07 2344#define AR_CTL_MODE_S 0 2345#define AR_CTL_11A 0 2346#define AR_CTL_11B 1 2347#define AR_CTL_11G 2 2348#define AR_CTL_2GHT20 5 2349#define AR_CTL_5GHT20 6 2350#define AR_CTL_2GHT40 7 2351#define AR_CTL_5GHT40 8 2352 2353/* 2354 * Serializer/Deserializer programming for non-PCIe devices. 2355 */ 2356static const uint32_t ar_nonpcie_serdes[] = { 2357 0x9248fc00, 2358 0x24924924, 2359 0x28000029, 2360 0x57160824, 2361 0x25980579, 2362 0x00000000, 2363 0x1aaabe40, 2364 0xbe105554, 2365 0x000e1007 2366}; 2367 2368/* 2369 * Macros to access registers. 2370 */ 2371#define AR_READ(sc, reg) \ 2372 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2373 2374#define AR_WRITE(sc, reg, val) \ 2375 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2376 2377#define AR_SETBITS(sc, reg, mask) \ 2378 AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask)) 2379 2380#define AR_CLRBITS(sc, reg, mask) \ 2381 AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask)) 2382 2383/* 2384 * Macros to access subfields in registers. 2385 */ 2386/* Mask and Shift (getter). */ 2387#define MS(val, field) \ 2388 (((val) & field##_M) >> field##_S) 2389 2390/* Shift and Mask (setter). */ 2391#define SM(field, val) \ 2392 (((val) << field##_S) & field##_M) 2393 2394/* Rewrite. */ 2395#define RW(var, field, val) \ 2396 (((var) & ~field##_M) | SM(field, val)) 2397