Remove SPR_CCR0 from <powerpc/spr.h>; we already have it in
<powerpc/ibm4xx/spr.h>, together with other 4xx-specific SPRs.

Thanks uwe@ for pointing out.

Instead of hard-coding SPR# for CCR0, define SPR_CCR0 in
<powerpc/spr.h> and use it.

Idea from uwe@, thanks!
(and sorry for delayed response!)

fix build with COPTS=-O0

Include missing opt_ppcarch.h.

s/static inline/static __inline/g for consistency.

first step towards G5 SMP:
- only save/restore BATs on CPUs that have them
- treat HID0 as 64bit on 64bit CPUs

branches: 1.50.2;
fix some logic errors in the previous and fix non-kernel builds.

fix ofppc/pegasosII (and maybe others).

don't assume PPC_OEA64_BRIDGE means we have a 64 bit cpu (code
for 64 bit in bridge and normal 32 bit can co-exist due to
fixups the early boot code does has, and ofppc builds GENERIC
this way):
- fix mtmsr()/mfmsr() to use the right method based upon the
actually cpu booted on.
- fix cpu_setup() to have 32 bit and 64 bit hid0 variables
and operate on the right one based upon the current cpu.
restore a minor optimisation of not writing hid0 if it
didn't change.

in set_timebase() check if OF_finddevice("/cpus/@0") failed
and returned -1 before using it for OF_getprop().

Add a copyright (approx 16.5 years later).

fix tpyo

add mfspr/mtspr methods suitable for 64bit SPRs on ppc970 in bridge mode

branches: 1.45.20; 1.45.38;
Split <powerpc/spr.h> into a common <powerpc/spr.h> and <powerpc/XXX/spr.h>
where XXX is ibm4xx or oea.

branches: 1.44.4; 1.44.24; 1.44.28;
Add some 440 definitions

branches: 1.43.2; 1.43.6;
Add a bunch of PVR values for a variety of processors. Taken from
various manuals, and linux.

branches: 1.42.2; 1.42.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.41.10;
Recognize the Freescale G2 cores: initialize cache line size, and doze mode
While there, fix the way the major version of a PowerPC processor is computed

branches: 1.40.14; 1.40.16; 1.40.22;
1st cut of Powermac G5 support (uses bridge mode).

Fix the entries for SPR_DC_ADR and SPR_DC_DAT.

branches: 1.38.4; 1.38.8; 1.38.16;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

Add MPC5200 SVR definition

branches: 1.36.8; 1.36.14;
Add MPC7448 and change MPC745x_P macro to deal with it.

Add MPC7447A (0x8003)

branches: 1.34.4;
Minor (old) patch from me to correct CPU ID of 604e vs. 604ev.
Tested by Tim Kelly.
Also patched from Tim to
- Delay longer for second CPU spinup.
- Only attempt to print CPU speed and cache configuration on certain
CPU types.

MPC8xx DC_CST is SPR 0x238, not 0x230.
Reported by Jared Momose in private email.

Add support for MPC74[45]7

Add IBM405GPr PVR.

add some 745x-specific MSSCR0 bits.

branches: 1.29.2;
MMCRx register definitions should not be prefixed by SPR_

Add two missing L2CLK speeds.

Condition ({ ... }) by __GNUC__. Remove redundant SPR_IBAT0U definiton.

Added configuration entries for L3CR_CONFIG for L3 caches on 745x
accelerators. Thanks to Monroe Williams.

Add a bunch of mpc8xx SPR definitions.

Add some IBM 4xx CPU PVR values; sort PVRs numerically.
White space nits.

Add IBM Power3 CPUID.

Add SPR_ASR from OEA-64. Change mfspr to use register_t.

add the MSSCR0 register and some more L2CR fields.

Add VRSAVE.

Add IBM750FX (0x7000)

Include the Processor ID for the MPC8245.

branches: 1.17.2; 1.17.4;
Add some MPC745x L3CR cache definitions.

Add MPC7455

Add bit definitions for the MMCR's, and event numbers for the events
that are common to the G3 and G4.

Correct the SPR numbers of PMC3 and PMC4.
SIA wasn't retconned, but the SPR number was wrong. Re-add it, and add
USIA.

Delete the retconned SIAR SPR.

Add MPC7xx/7xxx performance monitor control registers (MMCR0-2, UMMCR0-2).

Add bit definitions for the MPC750 thermal management registers.

Add MPC601 MQ and RTCU/RTCL SPRs.

Add PVR processor type fields for IBM 405GP and IBM 405L.

branches: 1.8.2;
Include bit definitions for the Debug Status Register; from Artem Belevich
at Riverstone Networks.

branches: 1.7.2;
Spell 'occurred' with two 'r's.

branches: 1.6.2;
Add new 7450 SPRs

Make all powerpc ports use a common Makefile.powerpc (except walnut)
Enforce -Wmissing-prototypes -Wstrict-prototypes for all ppc ports.
Split out macppc cpu support and make common to mpc6xx ports. Make
other mpc6xx ports use it. Add evcnts for mpc6xx traps.

branches: 1.4.2;
Use __asm __volatile. Use _POWERPC_SPR_H_
Add PTE_RO/PTE_RW for old pmap.

DMISS/DCMP/HASH1/HASH2/IMISS/ICMP/RPA are also valid on the MPC6XX
(specially the 603 and maybe the 601)

branches: 1.2.2;
Move the DSISR SPR bit definitions from <powerpc/mpc6xx/pte.h> to
<powerpc/spr.h>. Remove unused ISI/SRR1 bit definitions.

Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

fix build with COPTS=-O0

Include missing opt_ppcarch.h.

s/static inline/static __inline/g for consistency.

first step towards G5 SMP:
- only save/restore BATs on CPUs that have them
- treat HID0 as 64bit on 64bit CPUs

branches: 1.50.2;
fix some logic errors in the previous and fix non-kernel builds.

fix ofppc/pegasosII (and maybe others).

don't assume PPC_OEA64_BRIDGE means we have a 64 bit cpu (code
for 64 bit in bridge and normal 32 bit can co-exist due to
fixups the early boot code does has, and ofppc builds GENERIC
this way):
- fix mtmsr()/mfmsr() to use the right method based upon the
actually cpu booted on.
- fix cpu_setup() to have 32 bit and 64 bit hid0 variables
and operate on the right one based upon the current cpu.
restore a minor optimisation of not writing hid0 if it
didn't change.

in set_timebase() check if OF_finddevice("/cpus/@0") failed
and returned -1 before using it for OF_getprop().

Add a copyright (approx 16.5 years later).

fix tpyo

add mfspr/mtspr methods suitable for 64bit SPRs on ppc970 in bridge mode

branches: 1.45.20; 1.45.38;
Split <powerpc/spr.h> into a common <powerpc/spr.h> and <powerpc/XXX/spr.h>
where XXX is ibm4xx or oea.

branches: 1.44.4; 1.44.24; 1.44.28;
Add some 440 definitions

branches: 1.43.2; 1.43.6;
Add a bunch of PVR values for a variety of processors. Taken from
various manuals, and linux.

branches: 1.42.2; 1.42.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.41.10;
Recognize the Freescale G2 cores: initialize cache line size, and doze mode
While there, fix the way the major version of a PowerPC processor is computed

branches: 1.40.14; 1.40.16; 1.40.22;
1st cut of Powermac G5 support (uses bridge mode).

Fix the entries for SPR_DC_ADR and SPR_DC_DAT.

branches: 1.38.4; 1.38.8; 1.38.16;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

Add MPC5200 SVR definition

branches: 1.36.8; 1.36.14;
Add MPC7448 and change MPC745x_P macro to deal with it.

Add MPC7447A (0x8003)

branches: 1.34.4;
Minor (old) patch from me to correct CPU ID of 604e vs. 604ev.
Tested by Tim Kelly.
Also patched from Tim to
- Delay longer for second CPU spinup.
- Only attempt to print CPU speed and cache configuration on certain
CPU types.

MPC8xx DC_CST is SPR 0x238, not 0x230.
Reported by Jared Momose in private email.

Add support for MPC74[45]7

Add IBM405GPr PVR.

add some 745x-specific MSSCR0 bits.

branches: 1.29.2;
MMCRx register definitions should not be prefixed by SPR_

Add two missing L2CLK speeds.

Condition ({ ... }) by __GNUC__. Remove redundant SPR_IBAT0U definiton.

Added configuration entries for L3CR_CONFIG for L3 caches on 745x
accelerators. Thanks to Monroe Williams.

Add a bunch of mpc8xx SPR definitions.

Add some IBM 4xx CPU PVR values; sort PVRs numerically.
White space nits.

Add IBM Power3 CPUID.

Add SPR_ASR from OEA-64. Change mfspr to use register_t.

add the MSSCR0 register and some more L2CR fields.

Add VRSAVE.

Add IBM750FX (0x7000)

Include the Processor ID for the MPC8245.

branches: 1.17.2; 1.17.4;
Add some MPC745x L3CR cache definitions.

Add MPC7455

Add bit definitions for the MMCR's, and event numbers for the events
that are common to the G3 and G4.

Correct the SPR numbers of PMC3 and PMC4.
SIA wasn't retconned, but the SPR number was wrong. Re-add it, and add
USIA.

Delete the retconned SIAR SPR.

Add MPC7xx/7xxx performance monitor control registers (MMCR0-2, UMMCR0-2).

Add bit definitions for the MPC750 thermal management registers.

Add MPC601 MQ and RTCU/RTCL SPRs.

Add PVR processor type fields for IBM 405GP and IBM 405L.

branches: 1.8.2;
Include bit definitions for the Debug Status Register; from Artem Belevich
at Riverstone Networks.

branches: 1.7.2;
Spell 'occurred' with two 'r's.

branches: 1.6.2;
Add new 7450 SPRs

Make all powerpc ports use a common Makefile.powerpc (except walnut)
Enforce -Wmissing-prototypes -Wstrict-prototypes for all ppc ports.
Split out macppc cpu support and make common to mpc6xx ports. Make
other mpc6xx ports use it. Add evcnts for mpc6xx traps.

branches: 1.4.2;
Use __asm __volatile. Use _POWERPC_SPR_H_
Add PTE_RO/PTE_RW for old pmap.

DMISS/DCMP/HASH1/HASH2/IMISS/ICMP/RPA are also valid on the MPC6XX
(specially the 603 and maybe the 601)

branches: 1.2.2;
Move the DSISR SPR bit definitions from <powerpc/mpc6xx/pte.h> to
<powerpc/spr.h>. Remove unused ISI/SRR1 bit definitions.

Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

Include missing opt_ppcarch.h.

s/static inline/static __inline/g for consistency.

first step towards G5 SMP:
- only save/restore BATs on CPUs that have them
- treat HID0 as 64bit on 64bit CPUs

branches: 1.50.2;
fix some logic errors in the previous and fix non-kernel builds.

fix ofppc/pegasosII (and maybe others).

don't assume PPC_OEA64_BRIDGE means we have a 64 bit cpu (code
for 64 bit in bridge and normal 32 bit can co-exist due to
fixups the early boot code does has, and ofppc builds GENERIC
this way):
- fix mtmsr()/mfmsr() to use the right method based upon the
actually cpu booted on.
- fix cpu_setup() to have 32 bit and 64 bit hid0 variables
and operate on the right one based upon the current cpu.
restore a minor optimisation of not writing hid0 if it
didn't change.

in set_timebase() check if OF_finddevice("/cpus/@0") failed
and returned -1 before using it for OF_getprop().

Add a copyright (approx 16.5 years later).

fix tpyo

add mfspr/mtspr methods suitable for 64bit SPRs on ppc970 in bridge mode

branches: 1.45.20; 1.45.38;
Split <powerpc/spr.h> into a common <powerpc/spr.h> and <powerpc/XXX/spr.h>
where XXX is ibm4xx or oea.

branches: 1.44.4; 1.44.24; 1.44.28;
Add some 440 definitions

branches: 1.43.2; 1.43.6;
Add a bunch of PVR values for a variety of processors. Taken from
various manuals, and linux.

branches: 1.42.2; 1.42.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.41.10;
Recognize the Freescale G2 cores: initialize cache line size, and doze mode
While there, fix the way the major version of a PowerPC processor is computed

branches: 1.40.14; 1.40.16; 1.40.22;
1st cut of Powermac G5 support (uses bridge mode).

Fix the entries for SPR_DC_ADR and SPR_DC_DAT.

branches: 1.38.4; 1.38.8; 1.38.16;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

Add MPC5200 SVR definition

branches: 1.36.8; 1.36.14;
Add MPC7448 and change MPC745x_P macro to deal with it.

Add MPC7447A (0x8003)

branches: 1.34.4;
Minor (old) patch from me to correct CPU ID of 604e vs. 604ev.
Tested by Tim Kelly.
Also patched from Tim to
- Delay longer for second CPU spinup.
- Only attempt to print CPU speed and cache configuration on certain
CPU types.

MPC8xx DC_CST is SPR 0x238, not 0x230.
Reported by Jared Momose in private email.

Add support for MPC74[45]7

Add IBM405GPr PVR.

add some 745x-specific MSSCR0 bits.

branches: 1.29.2;
MMCRx register definitions should not be prefixed by SPR_

Add two missing L2CLK speeds.

Condition ({ ... }) by __GNUC__. Remove redundant SPR_IBAT0U definiton.

Added configuration entries for L3CR_CONFIG for L3 caches on 745x
accelerators. Thanks to Monroe Williams.

Add a bunch of mpc8xx SPR definitions.

Add some IBM 4xx CPU PVR values; sort PVRs numerically.
White space nits.

Add IBM Power3 CPUID.

Add SPR_ASR from OEA-64. Change mfspr to use register_t.

add the MSSCR0 register and some more L2CR fields.

Add VRSAVE.

Add IBM750FX (0x7000)

Include the Processor ID for the MPC8245.

branches: 1.17.2; 1.17.4;
Add some MPC745x L3CR cache definitions.

Add MPC7455

Add bit definitions for the MMCR's, and event numbers for the events
that are common to the G3 and G4.

Correct the SPR numbers of PMC3 and PMC4.
SIA wasn't retconned, but the SPR number was wrong. Re-add it, and add
USIA.

Delete the retconned SIAR SPR.

Add MPC7xx/7xxx performance monitor control registers (MMCR0-2, UMMCR0-2).

Add bit definitions for the MPC750 thermal management registers.

Add MPC601 MQ and RTCU/RTCL SPRs.

Add PVR processor type fields for IBM 405GP and IBM 405L.

branches: 1.8.2;
Include bit definitions for the Debug Status Register; from Artem Belevich
at Riverstone Networks.

branches: 1.7.2;
Spell 'occurred' with two 'r's.

branches: 1.6.2;
Add new 7450 SPRs

Make all powerpc ports use a common Makefile.powerpc (except walnut)
Enforce -Wmissing-prototypes -Wstrict-prototypes for all ppc ports.
Split out macppc cpu support and make common to mpc6xx ports. Make
other mpc6xx ports use it. Add evcnts for mpc6xx traps.

branches: 1.4.2;
Use __asm __volatile. Use _POWERPC_SPR_H_
Add PTE_RO/PTE_RW for old pmap.

DMISS/DCMP/HASH1/HASH2/IMISS/ICMP/RPA are also valid on the MPC6XX
(specially the 603 and maybe the 601)

branches: 1.2.2;
Move the DSISR SPR bit definitions from <powerpc/mpc6xx/pte.h> to
<powerpc/spr.h>. Remove unused ISI/SRR1 bit definitions.

Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

s/static inline/static __inline/g for consistency.

first step towards G5 SMP:
- only save/restore BATs on CPUs that have them
- treat HID0 as 64bit on 64bit CPUs

branches: 1.50.2;
fix some logic errors in the previous and fix non-kernel builds.

fix ofppc/pegasosII (and maybe others).

don't assume PPC_OEA64_BRIDGE means we have a 64 bit cpu (code
for 64 bit in bridge and normal 32 bit can co-exist due to
fixups the early boot code does has, and ofppc builds GENERIC
this way):
- fix mtmsr()/mfmsr() to use the right method based upon the
actually cpu booted on.
- fix cpu_setup() to have 32 bit and 64 bit hid0 variables
and operate on the right one based upon the current cpu.
restore a minor optimisation of not writing hid0 if it
didn't change.

in set_timebase() check if OF_finddevice("/cpus/@0") failed
and returned -1 before using it for OF_getprop().

Add a copyright (approx 16.5 years later).

fix tpyo

add mfspr/mtspr methods suitable for 64bit SPRs on ppc970 in bridge mode

branches: 1.45.20; 1.45.38;
Split <powerpc/spr.h> into a common <powerpc/spr.h> and <powerpc/XXX/spr.h>
where XXX is ibm4xx or oea.

branches: 1.44.4; 1.44.24; 1.44.28;
Add some 440 definitions

branches: 1.43.2; 1.43.6;
Add a bunch of PVR values for a variety of processors. Taken from
various manuals, and linux.

branches: 1.42.2; 1.42.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.41.10;
Recognize the Freescale G2 cores: initialize cache line size, and doze mode
While there, fix the way the major version of a PowerPC processor is computed

branches: 1.40.14; 1.40.16; 1.40.22;
1st cut of Powermac G5 support (uses bridge mode).

Fix the entries for SPR_DC_ADR and SPR_DC_DAT.

branches: 1.38.4; 1.38.8; 1.38.16;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

Add MPC5200 SVR definition

branches: 1.36.8; 1.36.14;
Add MPC7448 and change MPC745x_P macro to deal with it.

Add MPC7447A (0x8003)

branches: 1.34.4;
Minor (old) patch from me to correct CPU ID of 604e vs. 604ev.
Tested by Tim Kelly.
Also patched from Tim to
- Delay longer for second CPU spinup.
- Only attempt to print CPU speed and cache configuration on certain
CPU types.

MPC8xx DC_CST is SPR 0x238, not 0x230.
Reported by Jared Momose in private email.

Add support for MPC74[45]7

Add IBM405GPr PVR.

add some 745x-specific MSSCR0 bits.

branches: 1.29.2;
MMCRx register definitions should not be prefixed by SPR_

Add two missing L2CLK speeds.

Condition ({ ... }) by __GNUC__. Remove redundant SPR_IBAT0U definiton.

Added configuration entries for L3CR_CONFIG for L3 caches on 745x
accelerators. Thanks to Monroe Williams.

Add a bunch of mpc8xx SPR definitions.

Add some IBM 4xx CPU PVR values; sort PVRs numerically.
White space nits.

Add IBM Power3 CPUID.

Add SPR_ASR from OEA-64. Change mfspr to use register_t.

add the MSSCR0 register and some more L2CR fields.

Add VRSAVE.

Add IBM750FX (0x7000)

Include the Processor ID for the MPC8245.

branches: 1.17.2; 1.17.4;
Add some MPC745x L3CR cache definitions.

Add MPC7455

Add bit definitions for the MMCR's, and event numbers for the events
that are common to the G3 and G4.

Correct the SPR numbers of PMC3 and PMC4.
SIA wasn't retconned, but the SPR number was wrong. Re-add it, and add
USIA.

Delete the retconned SIAR SPR.

Add MPC7xx/7xxx performance monitor control registers (MMCR0-2, UMMCR0-2).

Add bit definitions for the MPC750 thermal management registers.

Add MPC601 MQ and RTCU/RTCL SPRs.

Add PVR processor type fields for IBM 405GP and IBM 405L.

branches: 1.8.2;
Include bit definitions for the Debug Status Register; from Artem Belevich
at Riverstone Networks.

branches: 1.7.2;
Spell 'occurred' with two 'r's.

branches: 1.6.2;
Add new 7450 SPRs

Make all powerpc ports use a common Makefile.powerpc (except walnut)
Enforce -Wmissing-prototypes -Wstrict-prototypes for all ppc ports.
Split out macppc cpu support and make common to mpc6xx ports. Make
other mpc6xx ports use it. Add evcnts for mpc6xx traps.

branches: 1.4.2;
Use __asm __volatile. Use _POWERPC_SPR_H_
Add PTE_RO/PTE_RW for old pmap.

DMISS/DCMP/HASH1/HASH2/IMISS/ICMP/RPA are also valid on the MPC6XX
(specially the 603 and maybe the 601)

branches: 1.2.2;
Move the DSISR SPR bit definitions from <powerpc/mpc6xx/pte.h> to
<powerpc/spr.h>. Remove unused ISI/SRR1 bit definitions.

Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

fix some logic errors in the previous and fix non-kernel builds.

fix ofppc/pegasosII (and maybe others).

don't assume PPC_OEA64_BRIDGE means we have a 64 bit cpu (code
for 64 bit in bridge and normal 32 bit can co-exist due to
fixups the early boot code does has, and ofppc builds GENERIC
this way):
- fix mtmsr()/mfmsr() to use the right method based upon the
actually cpu booted on.
- fix cpu_setup() to have 32 bit and 64 bit hid0 variables
and operate on the right one based upon the current cpu.
restore a minor optimisation of not writing hid0 if it
didn't change.

in set_timebase() check if OF_finddevice("/cpus/@0") failed
and returned -1 before using it for OF_getprop().

Add a copyright (approx 16.5 years later).

fix tpyo

add mfspr/mtspr methods suitable for 64bit SPRs on ppc970 in bridge mode

branches: 1.45.20; 1.45.38;
Split <powerpc/spr.h> into a common <powerpc/spr.h> and <powerpc/XXX/spr.h>
where XXX is ibm4xx or oea.

branches: 1.44.4; 1.44.24; 1.44.28;
Add some 440 definitions

branches: 1.43.2; 1.43.6;
Add a bunch of PVR values for a variety of processors. Taken from
various manuals, and linux.

branches: 1.42.2; 1.42.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.41.10;
Recognize the Freescale G2 cores: initialize cache line size, and doze mode
While there, fix the way the major version of a PowerPC processor is computed

branches: 1.40.14; 1.40.16; 1.40.22;
1st cut of Powermac G5 support (uses bridge mode).

Fix the entries for SPR_DC_ADR and SPR_DC_DAT.

branches: 1.38.4; 1.38.8; 1.38.16;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

Add MPC5200 SVR definition

branches: 1.36.8; 1.36.14;
Add MPC7448 and change MPC745x_P macro to deal with it.

Add MPC7447A (0x8003)

branches: 1.34.4;
Minor (old) patch from me to correct CPU ID of 604e vs. 604ev.
Tested by Tim Kelly.
Also patched from Tim to
- Delay longer for second CPU spinup.
- Only attempt to print CPU speed and cache configuration on certain
CPU types.

MPC8xx DC_CST is SPR 0x238, not 0x230.
Reported by Jared Momose in private email.

Add support for MPC74[45]7

Add IBM405GPr PVR.

add some 745x-specific MSSCR0 bits.

branches: 1.29.2;
MMCRx register definitions should not be prefixed by SPR_

Add two missing L2CLK speeds.

Condition ({ ... }) by __GNUC__. Remove redundant SPR_IBAT0U definiton.

Added configuration entries for L3CR_CONFIG for L3 caches on 745x
accelerators. Thanks to Monroe Williams.

Add a bunch of mpc8xx SPR definitions.

Add some IBM 4xx CPU PVR values; sort PVRs numerically.
White space nits.

Add IBM Power3 CPUID.

Add SPR_ASR from OEA-64. Change mfspr to use register_t.

add the MSSCR0 register and some more L2CR fields.

Add VRSAVE.

Add IBM750FX (0x7000)

Include the Processor ID for the MPC8245.

branches: 1.17.2; 1.17.4;
Add some MPC745x L3CR cache definitions.

Add MPC7455

Add bit definitions for the MMCR's, and event numbers for the events
that are common to the G3 and G4.

Correct the SPR numbers of PMC3 and PMC4.
SIA wasn't retconned, but the SPR number was wrong. Re-add it, and add
USIA.

Delete the retconned SIAR SPR.

Add MPC7xx/7xxx performance monitor control registers (MMCR0-2, UMMCR0-2).

Add bit definitions for the MPC750 thermal management registers.

Add MPC601 MQ and RTCU/RTCL SPRs.

Add PVR processor type fields for IBM 405GP and IBM 405L.

branches: 1.8.2;
Include bit definitions for the Debug Status Register; from Artem Belevich
at Riverstone Networks.

branches: 1.7.2;
Spell 'occurred' with two 'r's.

branches: 1.6.2;
Add new 7450 SPRs

Make all powerpc ports use a common Makefile.powerpc (except walnut)
Enforce -Wmissing-prototypes -Wstrict-prototypes for all ppc ports.
Split out macppc cpu support and make common to mpc6xx ports. Make
other mpc6xx ports use it. Add evcnts for mpc6xx traps.

branches: 1.4.2;
Use __asm __volatile. Use _POWERPC_SPR_H_
Add PTE_RO/PTE_RW for old pmap.

DMISS/DCMP/HASH1/HASH2/IMISS/ICMP/RPA are also valid on the MPC6XX
(specially the 603 and maybe the 601)

branches: 1.2.2;
Move the DSISR SPR bit definitions from <powerpc/mpc6xx/pte.h> to
<powerpc/spr.h>. Remove unused ISI/SRR1 bit definitions.

Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.