spr.h revision 1.46 
1/*	$NetBSD: spr.h,v 1.46 2017/07/07 22:11:36 macallan Exp $	*/
2
3#ifndef _POWERPC_SPR_H_
4#define	_POWERPC_SPR_H_
5
6#ifndef _LOCORE
7#ifdef PPC_OEA64_BRIDGE
8
9static inline uint64_t
10mfspr(int reg)
11{
12	uint64_t ret;
13	register_t h, l;
14	__asm volatile( "mfspr %0,%2;" \
15			"srdi %1,%0,32;" \
16			 : "=r"(l), "=r"(h) : "K"(reg));
17	ret = ((uint64_t)h << 32) | l;
18	return ret;
19}
20
21#define mtspr(reg, v) \
22( {						\
23	volatile register_t h, l;		\
24	uint64_t val = v;			\
25	h = (val >> 32);			\
26	l = val & 0xffffffff;			\
27	__asm volatile( \
28			"sldi %2,%2,32;" \
29			"or %2,%2,%1;" \
30			"sync;" \
31			"mtspr %0,%1;" \
32			"mfspr %1,%0;" \
33			"mfspr %1,%0;" \
34			"mfspr %1,%0;" \
35			"mfspr %1,%0;" \
36			"mfspr %1,%0;" \
37			"mfspr %1,%0;" \
38			 : : "K"(reg), "r"(l), "r"(h)); \
39} )
40
41#else
42#define	mtspr(reg, val)							\
43	__asm volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
44#ifdef __GNUC__
45#define	mfspr(reg)							\
46	( { register_t val;						\
47	  __asm volatile("mfspr %0,%1" : "=r"(val) : "K"(reg));	\
48	  val; } )
49#endif
50#endif /* PPC_OEA64_BRIDGE */
51#endif /* _LOCORE */
52
53/*
54 * Special Purpose Register declarations.
55 *
56 * The first column in the comments indicates which PowerPC architectures the
57 * SPR is valid on - E for BookE series, 4 for 4xx series,
58 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx (but not 85xx) series.
59 */
60
61#define	SPR_XER			0x001	/* E468 Fixed Point Exception Register */
62#define	SPR_LR			0x008	/* E468 Link Register */
63#define	SPR_CTR			0x009	/* E468 Count Register */
64#define	SPR_DEC			0x016	/* E468 DECrementer register */
65#define	SPR_SRR0		0x01a	/* E468 Save/Restore Register 0 */
66#define	SPR_SRR1		0x01b	/* E468 Save/Restore Register 1 */
67#define	SPR_SPRG0		0x110	/* E468 SPR General 0 */
68#define	SPR_SPRG1		0x111	/* E468 SPR General 1 */
69#define	SPR_SPRG2		0x112	/* E468 SPR General 2 */
70#define	SPR_SPRG3		0x113	/* E468 SPR General 3 */
71#define	SPR_SPRG4		0x114	/* E4.. SPR General 4 */
72#define	SPR_SPRG5		0x115	/* E4.. SPR General 5 */
73#define	SPR_SPRG6		0x116	/* E4.. SPR General 6 */
74#define	SPR_SPRG7		0x117	/* E4.. SPR General 7 */
75#define	SPR_TBL			0x11c	/* E468 Time Base Lower */
76#define	SPR_TBU			0x11d	/* E468 Time Base Upper */
77#define	SPR_PVR			0x11f	/* E468 Processor Version Register */
78
79/* Time Base Register declarations */
80#define	TBR_TBL			0x10c	/* E468 Time Base Lower */
81#define	TBR_TBU			0x10d	/* E468 Time Base Upper */
82
83#endif /* !_POWERPC_SPR_H_ */
84