spr.h revision 1.2
1#ifndef _SPR_H_ 2#define _SPR_H_ 3 4#ifndef _LOCORE 5#define mtspr(reg, val) \ 6 asm volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 7#define mfspr(reg) \ 8 ( { u_int32_t val; \ 9 asm volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 10 val; } ) 11#endif /* _LOCORE */ 12 13/* 14 * Special Purpose Register declarations. 15 * 16 * The first column in the comments indicates which PowerPC 17 * architectures the SPR is valid on - 4 for 4xx series, 18 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. 19 */ 20 21#define SPR_XER 0x001 /* 468 Fixed Point Exception Register */ 22#define SPR_LR 0x008 /* 468 Link Register */ 23#define SPR_CTR 0x009 /* 468 Count Register */ 24#define SPR_DSISR 0x012 /* .68 DSI exception source */ 25#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ 26#define DSISR_NOTFOUND 0x40000000 /* Translation not found */ 27#define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ 28#define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ 29#define DSISR_STORE 0x02000000 /* Store operation */ 30#define DSISR_DABR 0x00400000 /* DABR match */ 31#define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ 32#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ 33#define SPR_DAR 0x013 /* .68 Data Address Register */ 34#define SPR_DEC 0x016 /* .68 DECrementer register */ 35#define SPR_SDR1 0x019 /* .68 Page table base address register */ 36#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ 37#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ 38#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */ 39#define SPR_SPRG0 0x110 /* 468 SPR General 0 */ 40#define SPR_SPRG1 0x111 /* 468 SPR General 1 */ 41#define SPR_SPRG2 0x112 /* 468 SPR General 2 */ 42#define SPR_SPRG3 0x113 /* 468 SPR General 3 */ 43#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */ 44#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ 45#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ 46#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ 47#define SPR_EAR 0x11a /* .68 External Access Register */ 48#define SPR_TBL 0x11c /* 468 Time Base Lower */ 49#define SPR_TBU 0x11d /* 468 Time Base Upper */ 50#define SPR_PVR 0x11f /* 468 Processor Version Register */ 51#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ 52#define SPR_IBAT0L 0x211 /* .68 Instruction BAT Reg 0 Lower */ 53#define SPR_IBAT1U 0x212 /* .68 Instruction BAT Reg 1 Upper */ 54#define SPR_IBAT1L 0x213 /* .68 Instruction BAT Reg 1 Lower */ 55#define SPR_IBAT2U 0x214 /* .68 Instruction BAT Reg 2 Upper */ 56#define SPR_IBAT2L 0x215 /* .68 Instruction BAT Reg 2 Lower */ 57#define SPR_IBAT3U 0x216 /* .68 Instruction BAT Reg 3 Upper */ 58#define SPR_IBAT3L 0x217 /* .68 Instruction BAT Reg 3 Lower */ 59#define SPR_DBAT0U 0x218 /* .68 Data BAT Reg 0 Upper */ 60#define SPR_DBAT0L 0x219 /* .68 Data BAT Reg 0 Lower */ 61#define SPR_DBAT1U 0x21a /* .68 Data BAT Reg 1 Upper */ 62#define SPR_DBAT1L 0x21b /* .68 Data BAT Reg 1 Lower */ 63#define SPR_DBAT2U 0x21c /* .68 Data BAT Reg 2 Upper */ 64#define SPR_DBAT2L 0x21d /* .68 Data BAT Reg 2 Lower */ 65#define SPR_DBAT3U 0x21e /* .68 Data BAT Reg 3 Upper */ 66#define SPR_DBAT3L 0x21f /* .68 Data BAT Reg 3 Lower */ 67#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */ 68#define SPR_PID 0x3b1 /* 4.. Process ID */ 69#define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */ 70#define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */ 71#define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */ 72#define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */ 73#define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */ 74#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ 75#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ 76#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ 77#define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */ 78#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */ 79#define SPR_DMISS 0x3d0 /* ..8 Data TLB Miss Address Register */ 80#define SPR_DCMP 0x3d1 /* ..8 Data TLB Compare Register */ 81#define SPR_HASH1 0x3d2 /* ..8 Primary Hash Address Register */ 82#define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */ 83#define SPR_HASH2 0x3d3 /* ..8 Secondary Hash Address Register */ 84#define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */ 85#define ESR_MCI 0x80000000 /* Machine check - instruction */ 86#define ESR_PIL 0x08000000 /* Program interrupt - illegal */ 87#define ESR_PPR 0x04000000 /* Program interrupt - privileged */ 88#define ESR_PTR 0x02000000 /* Program interrupt - trap */ 89#define ESR_DST 0x00800000 /* Data storage interrupt - store fault */ 90#define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */ 91#define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */ 92#define SPR_IMISS 0x3d4 /* ..8 Instruction TLB Miss Address Register */ 93#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */ 94#define SPR_ICMP 0x3d5 /* ..8 Instruction TLB Compare Register */ 95#define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */ 96#define SPR_RPA 0x3d6 /* ..8 Required Physical Address Register */ 97#define SPR_TSR 0x3d8 /* 4.. Timer Status Register */ 98#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 99#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ 100#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ 101#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occured */ 102#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ 103#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ 104#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ 105#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 106#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 107#define SPR_TCR 0x3da /* 4.. Timer Control Register */ 108#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ 109#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ 110#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ 111#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ 112#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ 113#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ 114#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ 115#define TCR_WRC_CORE 0x10000000 /* Core reset */ 116#define TCR_WRC_CHIP 0x20000000 /* Chip reset */ 117#define TCR_WRC_SYSTEM 0x30000000 /* System reset */ 118#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ 119#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 120#define TCR_FP_MASK 0x03000000 /* FIT Period */ 121#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ 122#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ 123#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ 124#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ 125#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 126#define TCR_ARE 0x00400000 /* Auto Reload Enable */ 127#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */ 128#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */ 129#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ 130#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ 131#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ 132#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ 133#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */ 134#define DBCR0_EDM 0x80000000 /* External Debug Mode */ 135#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 136#define DBCR0_RST_MASK 0x30000000 /* ReSeT */ 137#define DBCR0_RST_NONE 0x00000000 /* No action */ 138#define DBCR0_RST_CORE 0x10000000 /* Core reset */ 139#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ 140#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ 141#define DBCR0_IC 0x08000000 /* Instruction Completion debug event */ 142#define DBCR0_BT 0x04000000 /* Branch Taken debug event */ 143#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ 144#define DBCR0_TDE 0x01000000 /* Trap Debug Event */ 145#define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */ 146#define DBCR0_IA2 0x00400000 /* IAC 2 debug event */ 147#define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */ 148#define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */ 149#define DBCR0_IA3 0x00080000 /* IAC 3 debug event */ 150#define DBCR0_IA4 0x00040000 /* IAC 4 debug event */ 151#define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */ 152#define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */ 153#define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */ 154#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ 155#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 156#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ 157#define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ 158#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ 159#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ 160#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ 161#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ 162#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ 163#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ 164#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ 165#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */ 166#define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */ 167#define SPR_PIR 0x3ff /* .6. Processor Identification Register */ 168 169/* Time Base Register declarations */ 170#define TBR_TBL 0x10c /* 468 Time Base Lower */ 171#define TBR_TBU 0x10d /* 468 Time Base Upper */ 172 173#endif /* !_SPR_H_ */ 174