spr.h revision 1.52
1/* $NetBSD: spr.h,v 1.52 2018/04/19 21:50:07 christos Exp $ */ 2 3/* 4 * Copyright (c) 2001, The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#ifndef _POWERPC_SPR_H_ 29#define _POWERPC_SPR_H_ 30 31#if !defined(_LOCORE) && defined(_KERNEL) 32 33#include <powerpc/oea/cpufeat.h> 34 35#if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 36static __inline uint64_t 37mfspr64(int reg) 38{ 39 uint64_t ret; 40 register_t hi, l; 41 42 __asm volatile( "mfspr %0,%2;" 43 "srdi %1,%0,32;" 44 : "=r"(l), "=r"(hi) : "K"(reg)); 45 ret = ((uint64_t)hi << 32) | l; 46 return ret; 47} 48 49/* This as an inline breaks as 'reg' ends up not being an immediate */ 50#define mtspr64(reg, v) \ 51( { \ 52 volatile register_t hi, l; \ 53 \ 54 uint64_t val = v; \ 55 hi = (val >> 32); \ 56 l = val & 0xffffffff; \ 57 __asm volatile( "sldi %2,%2,32;" \ 58 "or %2,%2,%1;" \ 59 "sync;" \ 60 "mtspr %0,%2;" \ 61 "mfspr %2,%0;" \ 62 "mfspr %2,%0;" \ 63 "mfspr %2,%0;" \ 64 "mfspr %2,%0;" \ 65 "mfspr %2,%0;" \ 66 "mfspr %2,%0;" \ 67 : : "K"(reg), "r"(l), "r"(hi)); \ 68} ) 69#endif /* PPC_OEA64_BRIDGE || _ARCH_PPC64 */ 70 71static __inline uint64_t 72mfspr32(int reg) 73{ 74 register_t val; 75 76 __asm volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); 77 return val; 78} 79 80static __inline void 81mtspr32(int reg, uint32_t val) 82{ 83 84 __asm volatile("mtspr %0,%1" : : "K"(reg), "r"(val)); 85} 86 87#if (defined(PPC_OEA) + defined(PPC_OEA64) + defined(PPC_OEA64_BRIDGE)) > 1 88static __inline uint64_t 89mfspr(int reg) 90{ 91 if ((oeacpufeat & (OEACPU_64_BRIDGE|OEACPU_64)) != 0) 92 return mfspr64(reg); 93 return mfspr32(reg); 94} 95 96/* This as an inline breaks as 'reg' ends up not being an immediate */ 97#define mtspr(reg, val) \ 98( { \ 99 if ((oeacpufeat & (OEACPU_64_BRIDGE|OEACPU_64)) != 0) \ 100 mtspr64(reg, (uint64_t)val); \ 101 else \ 102 mtspr32(reg, val); \ 103} ) 104#else /* PPC_OEA + PPC_OEA64 + PPC_OEA64_BRIDGE != 1 */ 105 106#if defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE) 107#define mfspr(r) mfspr64(r) 108#define mtspr(r,v) mtspr64(r,v) 109#else 110#define mfspr(r) mfspr32(r) 111#define mtspr(r,v) mtspr32(r,v) 112#endif 113 114#endif /* PPC_OEA + PPC_OEA64 + PPC_OEA64_BRIDGE > 1 */ 115 116#endif /* !_LOCORE && _KERNEL */ 117 118/* 119 * Special Purpose Register declarations. 120 * 121 * The first column in the comments indicates which PowerPC architectures the 122 * SPR is valid on - E for BookE series, 4 for 4xx series, 123 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx (but not 85xx) series. 124 */ 125 126#define SPR_XER 0x001 /* E468 Fixed Point Exception Register */ 127#define SPR_LR 0x008 /* E468 Link Register */ 128#define SPR_CTR 0x009 /* E468 Count Register */ 129#define SPR_DEC 0x016 /* E468 DECrementer register */ 130#define SPR_SRR0 0x01a /* E468 Save/Restore Register 0 */ 131#define SPR_SRR1 0x01b /* E468 Save/Restore Register 1 */ 132#define SPR_SPRG0 0x110 /* E468 SPR General 0 */ 133#define SPR_SPRG1 0x111 /* E468 SPR General 1 */ 134#define SPR_SPRG2 0x112 /* E468 SPR General 2 */ 135#define SPR_SPRG3 0x113 /* E468 SPR General 3 */ 136#define SPR_SPRG4 0x114 /* E4.. SPR General 4 */ 137#define SPR_SPRG5 0x115 /* E4.. SPR General 5 */ 138#define SPR_SPRG6 0x116 /* E4.. SPR General 6 */ 139#define SPR_SPRG7 0x117 /* E4.. SPR General 7 */ 140#define SPR_TBL 0x11c /* E468 Time Base Lower */ 141#define SPR_TBU 0x11d /* E468 Time Base Upper */ 142#define SPR_PVR 0x11f /* E468 Processor Version Register */ 143 144/* Time Base Register declarations */ 145#define TBR_TBL 0x10c /* E468 Time Base Lower */ 146#define TBR_TBU 0x10d /* E468 Time Base Upper */ 147 148#endif /* !_POWERPC_SPR_H_ */ 149