kern/58195: arm: Support drvctl -d and -r for cpufeaturebus

This is required for detaching and re-attaching the vmt(4) driver on aarch64.

arm: Use device_set_private for cpuN.

For cpu at fdt, nix the fdt softc -- this was leaked and never used
for anything. The device's private storage is the cpu_info.

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

For some classic CPUs, info->[id]cache_sets are not initialized.
Calculate and print numbers of sets in this case.

pN steppings are used for ARM926EJ-S, although only r0 seems to be available.

Print the cache information in similar formats and arm and aarch64, e.g.

arm before
[ 1.0000000] cpu0: 32KB/64B 2-way L1 PIPT Instruction cache
[ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
[ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache

arm after
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) PIPT Instruction cache
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) write-back-locking-C PIPT Data cache
[ 1.0000000] cpu0: L2 2304KB/64B 16-way (2304 set) write-through PIPT Unified cache

aarch64 before
[ 1.0000030] cpu1: L1 48KB/64B*256L*3W PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B*256L*2W PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B*2048L*16W PIPT Unified cache

aarch64 after
[ 1.0000030] cpu1: L1 48KB/64B 3-way (256 set) PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B 2-way (256 set) PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B 16-way (2048 set) PIPT Unified cache

Assume all ARM11[37]6 r0 variants are missing ISAR and friends. This is
certainly the case for r0 variants I could find TRMs for.

PR/50596 CPU_ID_ARM1136JS r0p4 does not support feature registers

branches: 1.147.6;
Initialize ci_kfpu_spl earlier for secondary CPUs. From riastradh

Implement fpu_kern_enter/leave for arm32.

KNF #includes

Remove some unnecessary ones while I'm here.

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

#ifdef whack-a-mole for the pmap_maxproc_set functionality

s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages
change

Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.

- Many small tweaks to the SMT awareness in the scheduler. It does a much
better job now at keeping all physical CPUs busy, while using the extra
threads to help out. In particular, during preempt() if we're using SMT,
try to find a better CPU to run on and teleport curlwp there.

- Change the CPU topology stuff so it can work on asymmetric systems. This
mainly entails rearranging one of the CPU lists so it makes sense in all
configurations.

- Add a parameter to cpu_topology_set() to note that a CPU is "slow", for
where there are fast CPUs and slow CPUs, like with the Rockwell RK3399.
Extend the SMT awareness to try and handle that situation too (keep fast
CPUs busy, use slow CPUs as helpers).

When attaching the first fdtbus, use the root "comptabile" (or failing that:
"model") property to set the cpu model (in userland aka sysctl hw.model).
When attaching the first cpu, do not overwrite a cpu model if it already
had been set.

cpu_hatch is too late to report AP topology, do it at attach time instead

branches: 1.136.2;
Some more CPU topology stuff:

- Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each
CPU as it is attached.

- For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT
IDs as "primaries", link back to the primaries from secondaries, and build
a circular list of CPUs in each package with identical SMT IDs.

- No need for package/core/smt/numa IDs to be anything other than a u_int.

Take the basic CPU topology information we already collect, and use it
to make circular lists of CPU siblings in the same core, and in the
same package. Nothing fancy, just enough to have a bit of fun in the
scheduler trying out different tactics.

cpu_hatched_p only for MULTIPROCESSOR

Increase aarch64 MAXCPUS to 256.

aprint_debug_dev output alignment

report A12 as A17 to the user. A12 is retcon'ed by ARM.

Cortex A12 is marketed as A17 but has a distinct part number

observed on Rockchip RK3288

branches: 1.129.4;
Wrap arm_cpu_marker if #ifdef MPDEBUG.

One day a9_mpsubr.S will die

Merge the [pgoyette-compat] branch

Make sure ci_{smt,core,package}_id are all filled in appropriately.

Previously the BP was missed and __SHIFTOUT wasn't used.

Read mpidr and cpuid from the secondary processor itself instead of the
boot processor. While here, add Cortex-A15 r4p0 to supported list.

Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.

Towards big.LITTLE support.

Don't overwrite the setting of cpu_core_id from mpidr

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Trialing whitespace

Use __BIT. NFC.

KNF

Fix includes (sys/cdefs.h then sys/param.h)

Sprinkle #include "opt_cputypes.h"

Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.

ok jmcneill@ skrll@

branches: 1.116.2; 1.116.4;
Add Cortex-A35 CPU ID.

branches: 1.115.6;
remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Add Cortex-A9 r1.

Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
While I'm here add some A57/A72 info as well.

My RPI3 works with FB console - the uart needs some help with its clocks.

Rename the cpu_id() define to cpu_idnum() so that it does not conflict with
dtrace and friends.

change some register dumps from aprint_verbose to aprint_debug

aprint_verbose [sa]ctlr

Print the Revision ID regster (verbose)

Print out mpidr on MP systems (verbose print)

cache type 12 is "write-back", from matt

branches: 1.106.2;
Add entry for Cortex-A17 r1

Increase the `freqbuf' buffer that holds the result of humanize_number(). Now
it prints 1600 Mhz instead of 1 Ghz.
Pitty enough humanize_number(9) doesn't do 1.6 Ghz type output.

branches: 1.104.4;
Various MP changes.

use cpu_{g,s}etmodel

Define cache type 13

Add most of the cpu_* variables to <arm/locore.h>
Add and initialize cpu_synchprim_present

Keep track of what each cache is (VIVT/VIPT/PIPT).

cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache

Add a machdep.hwdiv_present sysctl (cortex A7 and A15 have hwdiv instructions)

Add CPU_ID_CORTEXA7R0 entry

Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.96.2;
Nuke cpu_pfr, just use the armreg_pfr?_read inlines

Use the armreg_pfr?_read inlines.

Plug support for PJ4B into our ARM CPU infrastructure.

Obtained from Marvell, Semihalf.

Add a machdep.cpu_arch sysctl

Add simple sysctls for cpu_id, fpu_id, neon_present, simd_present,
simdex_present.
Add struct sysctls to return the isar, mmfr, pfr, and mvfr sets.

ARMFPE hasn't compiled since NetBSD 4. Remove it.
Complete support for FPU_VFP.
fpregs now contains vfpreg.
XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later
have 32 64-bit FP registers.

Use snprintf() instead of sprintf().

s/,/;/

C99 types

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

branches: 1.86.2;
Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Use new armv7 CP15 register to print out cache types.
If the cpu_cc_freq is set, report it.
Add macros to make inlines for reading/writing co-processor registers.

Use device_t

Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]

Refresh cortex cpus

Remove the ARM1156T2 bloat - it only has an MPU. Prompted by matt@

Add the ARM1156T2-S

Add the 'Z' to the 1176 cpu product name.

ok matt@

branches: 1.78.4; 1.78.8; 1.78.10;
add MPCore to CPU-ID table
add branch predict bit to arm11_options

branches: 1.77.2;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Fix cache probing on Cortex. Add missing CORTEX dependency in cpu.c

Fix c&p error.

Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

branches: 1.72.2; 1.72.4;
rename a local cpu_name structure member to avoid potential conflict
with <sys/cpu.h>'s.

branches: 1.71.4; 1.71.12;
Fix some missing things for CPU_ID_FA526.

Add entry for FA526.

Add Cortex cpus

branches: 1.68.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.67.2; 1.67.4;
VFP support.

branches: 1.66.12; 1.66.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.65.10; 1.65.12;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.64.2; 1.64.6; 1.64.8; 1.64.14;
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

From Scott Alan in http://mail-index.netbsd.org/port-arm/2006/07/26/0000.html
identify_arm_cpu() prints out a helpful message when it detects that you're
trying to run on a CPU that you didn't configure for. Unfortunately, the
check for class_option being NULL is backward, so it either won't print the
class_option, or it will try to dereference a NULL. The patch just flips the
!= NULL to be == NULL.

branches: 1.62.10; 1.62.14;
use km_alloc to get wired kernel memory for kernel stacks
of idle processes for secondary CPUs
(affects the MULTIPROCESSOR case only - does this exist?)
(untested)

branches: 1.61.4; 1.61.6; 1.61.8; 1.61.10;
merge ktrace-lwp.

Added i80219.

branches: 1.59.2;
The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined,
CPU is determined run-time.

Very basic support for the ARM1136.

This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.

Add support for arm1026ej-s.

distinguish PXA255/26x from PXA2[15]0 in CPU attach message

Uppercase CPU, plural is CPUs.

Fix up some unitialised variables.

Support for ARM10E class devices.

Recognize some TI processors -- not that you'd want to use them.

branches: 1.51.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

support IXP425 Intel Network Processor
running on BigEndian

Use aprint*().

Add CPU IDs for PXA B2 and C0 steppings.

specified, not specifed.

change uvm_uarea_alloc() to indicate whether the returned uarea is already
backed by physical pages (ie. because it reused a previously-freed one),
so that we can skip a bunch of useless work in that case.
this fixes the underlying problem behind PR 18543, and also speeds up fork()
quite a bit (eg. 7% on my pc, 1% on my ultra2) when we get a cache hit.

branches: 1.45.2;
Fix arm kernel build breaks for non multiprocessor systems.

It appears that MI code requires ci_cpuid to be the CPU number of the CPU
in question, whereas the ARM code was using it to hold the model
identification. To fix this, rename:

ci_cpuid -> ci_arm_cpuid
ci_cputype -> ci_arm_cputype (for consistency)
ci_cpurev -> ci_arm_cpurev (ditto)
ci_cpunum -> ci_cpuid

This makes top(1) give correct CPU numbers in its "STATE" column (all 0 for
now).

Remember the location of each CPU's idle PCB in struct cpu_info.
Move allocation of the idle PCB from hydra.c to cpu.c and add some
extra initialisation from cpu_fork().

constify various string tables.

Merge the gehenna-devsw branch into the trunk.

This merge changes the device switch tables from static array to
dynamically generated by config(8).

- All device switches is defined as a constant structure in device drivers.

- The new grammer ``device-major'' is introduced to ``files''.

device-major <prefix> char <num> [block <num>] [<rules>]

- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.

- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.

- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.

- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.

- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.

Handle i80200 step D0 and i80321 step B0

add cpu id for "PXA250/210 3rd version CPUcore".

for using many PDA/xscale-core.

Add the CPU ID for the 600MHz i80321 part.

branches: 1.37.2; 1.37.4;
change ICP12x0 steppings.
define CPU_IXP12X0

Add IXP1200 steppings.

Add support for the Intel PXA210 and PXA250. From Hiroyuki Bessho, PR 16617.

Enable CPU_CLASS_SA1 for SA1100 and SA1110.

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

The 80321 manual lies; it does have a CPU ID distinct from the 80200.
Add that CPU ID, and add a case for it.

Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.

Cache the cpu type and cpu revision in cpu_info.

Only put the CPU type into cpu_model, not the state of the control register.
Instead, print the control register state on the next line at startup.

Add CPU ID for the ARM1022ES.
Also add a CPU class for ARM10E processors in general.

When ARMFPE wasn't enabled the `usearmfpe' flag was statically initialised
but not used resulting in a compiler error. By splitting the declaration
and the initialisation this is solved.

Better would be to not even declare the flag when ARMFPE isnt enabled but
that would just add to the #ifdef jungle.

__RCSID -> __KERNEL_RCSID

Re-work the way that FPAs are handled. If ARMFPE isn't configured, don't
even bother probing for an FPA. If ARMFPE is configured, always use it,
even if there's an FPA (since it provides the FPA support code). Move all
printfs about FPAs into armfpe_init.c.

This means I can delete the last two elements from struct _cpu, so that the
structure, and the whole of <arm/cpus.h> is redundant and can be deleted.

Remove fpu_model from struct _cpu. Instead, have initialise_arm_fpe()
printf() the FPE version number itself.

Add a ci_dev element to struct cpu_info, pointing to the device that
corresponds to the CPU.

Kill the fpu_flags element from struct _cpu. It was only ever set to 0
anyway.

Clean up inline assembler. Rather than saving R0, copying FPSR to R0,
copying it to the output register and then restoring R0, just copy the
FPSR straight to the output.

Remove the cpu_model member from struct _cpu, and just use the cpu_model
variable directly. While we're at it, make cpu_model rather larger.

Remove the cpu_class element from struct _cpu, and make it a local variable
in identify_arm_cpu(), since it's almost unused elsewhere.

Change the detection of bugged StrongARMs to use the cpu ID rather than the
class. This turns "almost" into "entirely".

Replace cpu_id and cpu_ctrl in struct _cpu with ci_cpuid and ci_ctrl in
struct cpu_info. Also kill the cpuctrl global while we're here, and make
identify_arm_cpu() take a struct cpu_info * as an argument alongside the CPU
number.

Move arm700bugcount into stuct cpu_info, and attach it in
identify_master_cpu().

Our assembler handles FPA instructions fine, so don't use .word for them.

ANSIfy, and othe KNF cleanup.

Add revision->stepping maps for the SA-110, SA-1100 and SA-1110.
Those for the SA-1100 and SA-1110 are from Intel's documentation.
The mapping for the SA-110 is from various sources on the net, since Intel
don't seem to document it.

Also, change the layout of the maps to have four steppings per line,
so they aren't quite so unwieldy.

Use a table to look up stepping names. Add a generic stepping
table ("rev 0", "rev 1", etc.) and an i80200 stepping table that
has the stepping names that appear in the i80200 manuals/errata..

Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors. Report this when the processor is attached.

Move the ARM, Ltd. floating point emulator to arch/arm.

Use <arm/undefined.h> instead of <machine/undefined.h>.

branches: 1.9.2;
Const poisoning of cpu/class names.

"i80200", not "80200".

"XScale", not "Xscale".

branches: 1.6.2;
Support for ARM9.

Add extra arg to fpa_test as it should have 4 args. Also add prototypes for fpa_test and fpa_handler.

branches: 1.4.2;
Flesh XSCALE support.

branches: 1.3.2; 1.3.4;
Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32.

Shouldn't effect any currently in tree ports.

Use get_bootconf_option() to find boot options, rather than home-grown
strstr()-based hacks.

branches: 1.1.2;
Split cpu from mainbus so that cpu can attached to other buses (like ofbus).

arm: Use device_set_private for cpuN.

For cpu at fdt, nix the fdt softc -- this was leaked and never used
for anything. The device's private storage is the cpu_info.

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

For some classic CPUs, info->[id]cache_sets are not initialized.
Calculate and print numbers of sets in this case.

pN steppings are used for ARM926EJ-S, although only r0 seems to be available.

Print the cache information in similar formats and arm and aarch64, e.g.

arm before
[ 1.0000000] cpu0: 32KB/64B 2-way L1 PIPT Instruction cache
[ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
[ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache

arm after
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) PIPT Instruction cache
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) write-back-locking-C PIPT Data cache
[ 1.0000000] cpu0: L2 2304KB/64B 16-way (2304 set) write-through PIPT Unified cache

aarch64 before
[ 1.0000030] cpu1: L1 48KB/64B*256L*3W PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B*256L*2W PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B*2048L*16W PIPT Unified cache

aarch64 after
[ 1.0000030] cpu1: L1 48KB/64B 3-way (256 set) PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B 2-way (256 set) PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B 16-way (2048 set) PIPT Unified cache

Assume all ARM11[37]6 r0 variants are missing ISAR and friends. This is
certainly the case for r0 variants I could find TRMs for.

PR/50596 CPU_ID_ARM1136JS r0p4 does not support feature registers

branches: 1.147.6;
Initialize ci_kfpu_spl earlier for secondary CPUs. From riastradh

Implement fpu_kern_enter/leave for arm32.

KNF #includes

Remove some unnecessary ones while I'm here.

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

#ifdef whack-a-mole for the pmap_maxproc_set functionality

s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages
change

Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.

- Many small tweaks to the SMT awareness in the scheduler. It does a much
better job now at keeping all physical CPUs busy, while using the extra
threads to help out. In particular, during preempt() if we're using SMT,
try to find a better CPU to run on and teleport curlwp there.

- Change the CPU topology stuff so it can work on asymmetric systems. This
mainly entails rearranging one of the CPU lists so it makes sense in all
configurations.

- Add a parameter to cpu_topology_set() to note that a CPU is "slow", for
where there are fast CPUs and slow CPUs, like with the Rockwell RK3399.
Extend the SMT awareness to try and handle that situation too (keep fast
CPUs busy, use slow CPUs as helpers).

When attaching the first fdtbus, use the root "comptabile" (or failing that:
"model") property to set the cpu model (in userland aka sysctl hw.model).
When attaching the first cpu, do not overwrite a cpu model if it already
had been set.

cpu_hatch is too late to report AP topology, do it at attach time instead

branches: 1.136.2;
Some more CPU topology stuff:

- Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each
CPU as it is attached.

- For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT
IDs as "primaries", link back to the primaries from secondaries, and build
a circular list of CPUs in each package with identical SMT IDs.

- No need for package/core/smt/numa IDs to be anything other than a u_int.

Take the basic CPU topology information we already collect, and use it
to make circular lists of CPU siblings in the same core, and in the
same package. Nothing fancy, just enough to have a bit of fun in the
scheduler trying out different tactics.

cpu_hatched_p only for MULTIPROCESSOR

Increase aarch64 MAXCPUS to 256.

aprint_debug_dev output alignment

report A12 as A17 to the user. A12 is retcon'ed by ARM.

Cortex A12 is marketed as A17 but has a distinct part number

observed on Rockchip RK3288

branches: 1.129.4;
Wrap arm_cpu_marker if #ifdef MPDEBUG.

One day a9_mpsubr.S will die

Merge the [pgoyette-compat] branch

Make sure ci_{smt,core,package}_id are all filled in appropriately.

Previously the BP was missed and __SHIFTOUT wasn't used.

Read mpidr and cpuid from the secondary processor itself instead of the
boot processor. While here, add Cortex-A15 r4p0 to supported list.

Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.

Towards big.LITTLE support.

Don't overwrite the setting of cpu_core_id from mpidr

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Trialing whitespace

Use __BIT. NFC.

KNF

Fix includes (sys/cdefs.h then sys/param.h)

Sprinkle #include "opt_cputypes.h"

Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.

ok jmcneill@ skrll@

branches: 1.116.2; 1.116.4;
Add Cortex-A35 CPU ID.

branches: 1.115.6;
remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Add Cortex-A9 r1.

Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
While I'm here add some A57/A72 info as well.

My RPI3 works with FB console - the uart needs some help with its clocks.

Rename the cpu_id() define to cpu_idnum() so that it does not conflict with
dtrace and friends.

change some register dumps from aprint_verbose to aprint_debug

aprint_verbose [sa]ctlr

Print the Revision ID regster (verbose)

Print out mpidr on MP systems (verbose print)

cache type 12 is "write-back", from matt

branches: 1.106.2;
Add entry for Cortex-A17 r1

Increase the `freqbuf' buffer that holds the result of humanize_number(). Now
it prints 1600 Mhz instead of 1 Ghz.
Pitty enough humanize_number(9) doesn't do 1.6 Ghz type output.

branches: 1.104.4;
Various MP changes.

use cpu_{g,s}etmodel

Define cache type 13

Add most of the cpu_* variables to <arm/locore.h>
Add and initialize cpu_synchprim_present

Keep track of what each cache is (VIVT/VIPT/PIPT).

cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache

Add a machdep.hwdiv_present sysctl (cortex A7 and A15 have hwdiv instructions)

Add CPU_ID_CORTEXA7R0 entry

Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.96.2;
Nuke cpu_pfr, just use the armreg_pfr?_read inlines

Use the armreg_pfr?_read inlines.

Plug support for PJ4B into our ARM CPU infrastructure.

Obtained from Marvell, Semihalf.

Add a machdep.cpu_arch sysctl

Add simple sysctls for cpu_id, fpu_id, neon_present, simd_present,
simdex_present.
Add struct sysctls to return the isar, mmfr, pfr, and mvfr sets.

ARMFPE hasn't compiled since NetBSD 4. Remove it.
Complete support for FPU_VFP.
fpregs now contains vfpreg.
XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later
have 32 64-bit FP registers.

Use snprintf() instead of sprintf().

s/,/;/

C99 types

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

branches: 1.86.2;
Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Use new armv7 CP15 register to print out cache types.
If the cpu_cc_freq is set, report it.
Add macros to make inlines for reading/writing co-processor registers.

Use device_t

Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]

Refresh cortex cpus

Remove the ARM1156T2 bloat - it only has an MPU. Prompted by matt@

Add the ARM1156T2-S

Add the 'Z' to the 1176 cpu product name.

ok matt@

branches: 1.78.4; 1.78.8; 1.78.10;
add MPCore to CPU-ID table
add branch predict bit to arm11_options

branches: 1.77.2;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Fix cache probing on Cortex. Add missing CORTEX dependency in cpu.c

Fix c&p error.

Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

branches: 1.72.2; 1.72.4;
rename a local cpu_name structure member to avoid potential conflict
with <sys/cpu.h>'s.

branches: 1.71.4; 1.71.12;
Fix some missing things for CPU_ID_FA526.

Add entry for FA526.

Add Cortex cpus

branches: 1.68.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.67.2; 1.67.4;
VFP support.

branches: 1.66.12; 1.66.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.65.10; 1.65.12;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.64.2; 1.64.6; 1.64.8; 1.64.14;
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

From Scott Alan in http://mail-index.netbsd.org/port-arm/2006/07/26/0000.html
identify_arm_cpu() prints out a helpful message when it detects that you're
trying to run on a CPU that you didn't configure for. Unfortunately, the
check for class_option being NULL is backward, so it either won't print the
class_option, or it will try to dereference a NULL. The patch just flips the
!= NULL to be == NULL.

branches: 1.62.10; 1.62.14;
use km_alloc to get wired kernel memory for kernel stacks
of idle processes for secondary CPUs
(affects the MULTIPROCESSOR case only - does this exist?)
(untested)

branches: 1.61.4; 1.61.6; 1.61.8; 1.61.10;
merge ktrace-lwp.

Added i80219.

branches: 1.59.2;
The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined,
CPU is determined run-time.

Very basic support for the ARM1136.

This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.

Add support for arm1026ej-s.

distinguish PXA255/26x from PXA2[15]0 in CPU attach message

Uppercase CPU, plural is CPUs.

Fix up some unitialised variables.

Support for ARM10E class devices.

Recognize some TI processors -- not that you'd want to use them.

branches: 1.51.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

support IXP425 Intel Network Processor
running on BigEndian

Use aprint*().

Add CPU IDs for PXA B2 and C0 steppings.

specified, not specifed.

change uvm_uarea_alloc() to indicate whether the returned uarea is already
backed by physical pages (ie. because it reused a previously-freed one),
so that we can skip a bunch of useless work in that case.
this fixes the underlying problem behind PR 18543, and also speeds up fork()
quite a bit (eg. 7% on my pc, 1% on my ultra2) when we get a cache hit.

branches: 1.45.2;
Fix arm kernel build breaks for non multiprocessor systems.

It appears that MI code requires ci_cpuid to be the CPU number of the CPU
in question, whereas the ARM code was using it to hold the model
identification. To fix this, rename:

ci_cpuid -> ci_arm_cpuid
ci_cputype -> ci_arm_cputype (for consistency)
ci_cpurev -> ci_arm_cpurev (ditto)
ci_cpunum -> ci_cpuid

This makes top(1) give correct CPU numbers in its "STATE" column (all 0 for
now).

Remember the location of each CPU's idle PCB in struct cpu_info.
Move allocation of the idle PCB from hydra.c to cpu.c and add some
extra initialisation from cpu_fork().

constify various string tables.

Merge the gehenna-devsw branch into the trunk.

This merge changes the device switch tables from static array to
dynamically generated by config(8).

- All device switches is defined as a constant structure in device drivers.

- The new grammer ``device-major'' is introduced to ``files''.

device-major <prefix> char <num> [block <num>] [<rules>]

- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.

- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.

- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.

- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.

- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.

Handle i80200 step D0 and i80321 step B0

add cpu id for "PXA250/210 3rd version CPUcore".

for using many PDA/xscale-core.

Add the CPU ID for the 600MHz i80321 part.

branches: 1.37.2; 1.37.4;
change ICP12x0 steppings.
define CPU_IXP12X0

Add IXP1200 steppings.

Add support for the Intel PXA210 and PXA250. From Hiroyuki Bessho, PR 16617.

Enable CPU_CLASS_SA1 for SA1100 and SA1110.

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

The 80321 manual lies; it does have a CPU ID distinct from the 80200.
Add that CPU ID, and add a case for it.

Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.

Cache the cpu type and cpu revision in cpu_info.

Only put the CPU type into cpu_model, not the state of the control register.
Instead, print the control register state on the next line at startup.

Add CPU ID for the ARM1022ES.
Also add a CPU class for ARM10E processors in general.

When ARMFPE wasn't enabled the `usearmfpe' flag was statically initialised
but not used resulting in a compiler error. By splitting the declaration
and the initialisation this is solved.

Better would be to not even declare the flag when ARMFPE isnt enabled but
that would just add to the #ifdef jungle.

__RCSID -> __KERNEL_RCSID

Re-work the way that FPAs are handled. If ARMFPE isn't configured, don't
even bother probing for an FPA. If ARMFPE is configured, always use it,
even if there's an FPA (since it provides the FPA support code). Move all
printfs about FPAs into armfpe_init.c.

This means I can delete the last two elements from struct _cpu, so that the
structure, and the whole of <arm/cpus.h> is redundant and can be deleted.

Remove fpu_model from struct _cpu. Instead, have initialise_arm_fpe()
printf() the FPE version number itself.

Add a ci_dev element to struct cpu_info, pointing to the device that
corresponds to the CPU.

Kill the fpu_flags element from struct _cpu. It was only ever set to 0
anyway.

Clean up inline assembler. Rather than saving R0, copying FPSR to R0,
copying it to the output register and then restoring R0, just copy the
FPSR straight to the output.

Remove the cpu_model member from struct _cpu, and just use the cpu_model
variable directly. While we're at it, make cpu_model rather larger.

Remove the cpu_class element from struct _cpu, and make it a local variable
in identify_arm_cpu(), since it's almost unused elsewhere.

Change the detection of bugged StrongARMs to use the cpu ID rather than the
class. This turns "almost" into "entirely".

Replace cpu_id and cpu_ctrl in struct _cpu with ci_cpuid and ci_ctrl in
struct cpu_info. Also kill the cpuctrl global while we're here, and make
identify_arm_cpu() take a struct cpu_info * as an argument alongside the CPU
number.

Move arm700bugcount into stuct cpu_info, and attach it in
identify_master_cpu().

Our assembler handles FPA instructions fine, so don't use .word for them.

ANSIfy, and othe KNF cleanup.

Add revision->stepping maps for the SA-110, SA-1100 and SA-1110.
Those for the SA-1100 and SA-1110 are from Intel's documentation.
The mapping for the SA-110 is from various sources on the net, since Intel
don't seem to document it.

Also, change the layout of the maps to have four steppings per line,
so they aren't quite so unwieldy.

Use a table to look up stepping names. Add a generic stepping
table ("rev 0", "rev 1", etc.) and an i80200 stepping table that
has the stepping names that appear in the i80200 manuals/errata..

Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors. Report this when the processor is attached.

Move the ARM, Ltd. floating point emulator to arch/arm.

Use <arm/undefined.h> instead of <machine/undefined.h>.

branches: 1.9.2;
Const poisoning of cpu/class names.

"i80200", not "80200".

"XScale", not "Xscale".

branches: 1.6.2;
Support for ARM9.

Add extra arg to fpa_test as it should have 4 args. Also add prototypes for fpa_test and fpa_handler.

branches: 1.4.2;
Flesh XSCALE support.

branches: 1.3.2; 1.3.4;
Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32.

Shouldn't effect any currently in tree ports.

Use get_bootconf_option() to find boot options, rather than home-grown
strstr()-based hacks.

branches: 1.1.2;
Split cpu from mainbus so that cpu can attached to other buses (like ofbus).

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

For some classic CPUs, info->[id]cache_sets are not initialized.
Calculate and print numbers of sets in this case.

pN steppings are used for ARM926EJ-S, although only r0 seems to be available.

Print the cache information in similar formats and arm and aarch64, e.g.

arm before
[ 1.0000000] cpu0: 32KB/64B 2-way L1 PIPT Instruction cache
[ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
[ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache

arm after
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) PIPT Instruction cache
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) write-back-locking-C PIPT Data cache
[ 1.0000000] cpu0: L2 2304KB/64B 16-way (2304 set) write-through PIPT Unified cache

aarch64 before
[ 1.0000030] cpu1: L1 48KB/64B*256L*3W PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B*256L*2W PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B*2048L*16W PIPT Unified cache

aarch64 after
[ 1.0000030] cpu1: L1 48KB/64B 3-way (256 set) PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B 2-way (256 set) PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B 16-way (2048 set) PIPT Unified cache

Assume all ARM11[37]6 r0 variants are missing ISAR and friends. This is
certainly the case for r0 variants I could find TRMs for.

PR/50596 CPU_ID_ARM1136JS r0p4 does not support feature registers

branches: 1.147.6;
Initialize ci_kfpu_spl earlier for secondary CPUs. From riastradh

Implement fpu_kern_enter/leave for arm32.

KNF #includes

Remove some unnecessary ones while I'm here.

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

#ifdef whack-a-mole for the pmap_maxproc_set functionality

s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages
change

Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.

- Many small tweaks to the SMT awareness in the scheduler. It does a much
better job now at keeping all physical CPUs busy, while using the extra
threads to help out. In particular, during preempt() if we're using SMT,
try to find a better CPU to run on and teleport curlwp there.

- Change the CPU topology stuff so it can work on asymmetric systems. This
mainly entails rearranging one of the CPU lists so it makes sense in all
configurations.

- Add a parameter to cpu_topology_set() to note that a CPU is "slow", for
where there are fast CPUs and slow CPUs, like with the Rockwell RK3399.
Extend the SMT awareness to try and handle that situation too (keep fast
CPUs busy, use slow CPUs as helpers).

When attaching the first fdtbus, use the root "comptabile" (or failing that:
"model") property to set the cpu model (in userland aka sysctl hw.model).
When attaching the first cpu, do not overwrite a cpu model if it already
had been set.

cpu_hatch is too late to report AP topology, do it at attach time instead

branches: 1.136.2;
Some more CPU topology stuff:

- Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each
CPU as it is attached.

- For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT
IDs as "primaries", link back to the primaries from secondaries, and build
a circular list of CPUs in each package with identical SMT IDs.

- No need for package/core/smt/numa IDs to be anything other than a u_int.

Take the basic CPU topology information we already collect, and use it
to make circular lists of CPU siblings in the same core, and in the
same package. Nothing fancy, just enough to have a bit of fun in the
scheduler trying out different tactics.

cpu_hatched_p only for MULTIPROCESSOR

Increase aarch64 MAXCPUS to 256.

aprint_debug_dev output alignment

report A12 as A17 to the user. A12 is retcon'ed by ARM.

Cortex A12 is marketed as A17 but has a distinct part number

observed on Rockchip RK3288

branches: 1.129.4;
Wrap arm_cpu_marker if #ifdef MPDEBUG.

One day a9_mpsubr.S will die

Merge the [pgoyette-compat] branch

Make sure ci_{smt,core,package}_id are all filled in appropriately.

Previously the BP was missed and __SHIFTOUT wasn't used.

Read mpidr and cpuid from the secondary processor itself instead of the
boot processor. While here, add Cortex-A15 r4p0 to supported list.

Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.

Towards big.LITTLE support.

Don't overwrite the setting of cpu_core_id from mpidr

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Trialing whitespace

Use __BIT. NFC.

KNF

Fix includes (sys/cdefs.h then sys/param.h)

Sprinkle #include "opt_cputypes.h"

Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.

ok jmcneill@ skrll@

branches: 1.116.2; 1.116.4;
Add Cortex-A35 CPU ID.

branches: 1.115.6;
remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Add Cortex-A9 r1.

Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
While I'm here add some A57/A72 info as well.

My RPI3 works with FB console - the uart needs some help with its clocks.

Rename the cpu_id() define to cpu_idnum() so that it does not conflict with
dtrace and friends.

change some register dumps from aprint_verbose to aprint_debug

aprint_verbose [sa]ctlr

Print the Revision ID regster (verbose)

Print out mpidr on MP systems (verbose print)

cache type 12 is "write-back", from matt

branches: 1.106.2;
Add entry for Cortex-A17 r1

Increase the `freqbuf' buffer that holds the result of humanize_number(). Now
it prints 1600 Mhz instead of 1 Ghz.
Pitty enough humanize_number(9) doesn't do 1.6 Ghz type output.

branches: 1.104.4;
Various MP changes.

use cpu_{g,s}etmodel

Define cache type 13

Add most of the cpu_* variables to <arm/locore.h>
Add and initialize cpu_synchprim_present

Keep track of what each cache is (VIVT/VIPT/PIPT).

cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache

Add a machdep.hwdiv_present sysctl (cortex A7 and A15 have hwdiv instructions)

Add CPU_ID_CORTEXA7R0 entry

Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.96.2;
Nuke cpu_pfr, just use the armreg_pfr?_read inlines

Use the armreg_pfr?_read inlines.

Plug support for PJ4B into our ARM CPU infrastructure.

Obtained from Marvell, Semihalf.

Add a machdep.cpu_arch sysctl

Add simple sysctls for cpu_id, fpu_id, neon_present, simd_present,
simdex_present.
Add struct sysctls to return the isar, mmfr, pfr, and mvfr sets.

ARMFPE hasn't compiled since NetBSD 4. Remove it.
Complete support for FPU_VFP.
fpregs now contains vfpreg.
XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later
have 32 64-bit FP registers.

Use snprintf() instead of sprintf().

s/,/;/

C99 types

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

branches: 1.86.2;
Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Use new armv7 CP15 register to print out cache types.
If the cpu_cc_freq is set, report it.
Add macros to make inlines for reading/writing co-processor registers.

Use device_t

Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]

Refresh cortex cpus

Remove the ARM1156T2 bloat - it only has an MPU. Prompted by matt@

Add the ARM1156T2-S

Add the 'Z' to the 1176 cpu product name.

ok matt@

branches: 1.78.4; 1.78.8; 1.78.10;
add MPCore to CPU-ID table
add branch predict bit to arm11_options

branches: 1.77.2;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Fix cache probing on Cortex. Add missing CORTEX dependency in cpu.c

Fix c&p error.

Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

branches: 1.72.2; 1.72.4;
rename a local cpu_name structure member to avoid potential conflict
with <sys/cpu.h>'s.

branches: 1.71.4; 1.71.12;
Fix some missing things for CPU_ID_FA526.

Add entry for FA526.

Add Cortex cpus

branches: 1.68.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.67.2; 1.67.4;
VFP support.

branches: 1.66.12; 1.66.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.65.10; 1.65.12;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.64.2; 1.64.6; 1.64.8; 1.64.14;
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

From Scott Alan in http://mail-index.netbsd.org/port-arm/2006/07/26/0000.html
identify_arm_cpu() prints out a helpful message when it detects that you're
trying to run on a CPU that you didn't configure for. Unfortunately, the
check for class_option being NULL is backward, so it either won't print the
class_option, or it will try to dereference a NULL. The patch just flips the
!= NULL to be == NULL.

branches: 1.62.10; 1.62.14;
use km_alloc to get wired kernel memory for kernel stacks
of idle processes for secondary CPUs
(affects the MULTIPROCESSOR case only - does this exist?)
(untested)

branches: 1.61.4; 1.61.6; 1.61.8; 1.61.10;
merge ktrace-lwp.

Added i80219.

branches: 1.59.2;
The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined,
CPU is determined run-time.

Very basic support for the ARM1136.

This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.

Add support for arm1026ej-s.

distinguish PXA255/26x from PXA2[15]0 in CPU attach message

Uppercase CPU, plural is CPUs.

Fix up some unitialised variables.

Support for ARM10E class devices.

Recognize some TI processors -- not that you'd want to use them.

branches: 1.51.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

support IXP425 Intel Network Processor
running on BigEndian

Use aprint*().

Add CPU IDs for PXA B2 and C0 steppings.

specified, not specifed.

change uvm_uarea_alloc() to indicate whether the returned uarea is already
backed by physical pages (ie. because it reused a previously-freed one),
so that we can skip a bunch of useless work in that case.
this fixes the underlying problem behind PR 18543, and also speeds up fork()
quite a bit (eg. 7% on my pc, 1% on my ultra2) when we get a cache hit.

branches: 1.45.2;
Fix arm kernel build breaks for non multiprocessor systems.

It appears that MI code requires ci_cpuid to be the CPU number of the CPU
in question, whereas the ARM code was using it to hold the model
identification. To fix this, rename:

ci_cpuid -> ci_arm_cpuid
ci_cputype -> ci_arm_cputype (for consistency)
ci_cpurev -> ci_arm_cpurev (ditto)
ci_cpunum -> ci_cpuid

This makes top(1) give correct CPU numbers in its "STATE" column (all 0 for
now).

Remember the location of each CPU's idle PCB in struct cpu_info.
Move allocation of the idle PCB from hydra.c to cpu.c and add some
extra initialisation from cpu_fork().