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331722 |
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29-Mar-2018 |
eadler |
Revert r330897:
This was intended to be a non-functional change. It wasn't. The commit message was thus wrong. In addition it broke arm, and merged crypto related code.
Revert with prejudice.
This revert skips files touched in r316370 since that commit was since MFCed. This revert also skips files that require $FreeBSD$ property changes.
Thank you to those who helped me get out of this mess including but not limited to gonzo, kevans, rgrimes.
Requested by: gjb (re)
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330897 |
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14-Mar-2018 |
eadler |
Partial merge of the SPDX changes
These changes are incomplete but are making it difficult to determine what other changes can/should be merged.
No objections from: pfg
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317002 |
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16-Apr-2017 |
mmel |
MFC r306631,r306640,r306641,r306650,r306656:
r306631: Use C99 designated initializers to create the armv6 cpu_functions structs. This will help with a later cleanup of what functions we implement. r306640: Only define the CF_* macros on ARMv4/v5. They are unused on armv6. r306641: Remove the parts of cpu_functions from armv6 that are unused on that architecture. r306650: Add the Cortex-A{53,57,72} ID register values. These can all run 32-bit code so could run a 32-bit kernel. r306656: Use the cortex functions when booting on one of the Cortex-A ARMv8 CPUs. This list is incomplete, however we don't have the ID values for the missing Cortex-A32 or A35.
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302408 |
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07-Jul-2016 |
gjb |
Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle. Prune svn:mergeinfo from the new branch, as nothing has been merged here.
Additional commits post-branch will follow.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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301561 |
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07-Jun-2016 |
andrew |
Start to clean MIDR values using the CPUID scheme. We don't need to know the exact CPU we are running on to set the cpu functions. Relax the check to ignore the CPU revision. Even so this may still be too specific.
Reviewed by: mmel Sponsored by: ABT Systems Ltd Differential Revision: https://reviews.freebsd.org/D6504
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300694 |
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25-May-2016 |
ian |
Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't have ACLE support built in. The ACLE (ARM C Language Extensions) defines a set of standardized symbols which indicate the architecture version and features available. ACLE support is built in to modern compilers (both clang and gcc), but absent from gcc prior to 4.4.
ARM (the company) provides the acle-compat.h header file to define the right symbols for older versions of gcc. Basically, acle-compat.h does for arm about the same thing cdefs.h does for freebsd: defines standardized macros that work no matter which compiler you use. If ARM hadn't provided this file we would have ended up with a big #ifdef __arm__ section in cdefs.h with our own compatibility shims.
Remove #include <machine/acle-compat.h> from the zillion other places (an ever-growing list) that it appears. Since style(9) requires sys/types.h or sys/param.h early in the include list, and both of those lead to including cdefs.h, only a couple special cases still need to include acle-compat.h directly.
Loves it: imp
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291425 |
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28-Nov-2015 |
mmel |
ARM: Add support for new KRAIT 300 CPU revision.
Approved by: kib (mentor)
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290648 |
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10-Nov-2015 |
mmel |
ARM: Remove trailing whitespace from sys/arm/include No functional changes.
Approved by: kib (mentor)
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290369 |
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04-Nov-2015 |
skra |
Fix comment about unpriviledged instructions. Now, it matches with current state after r289372.
While here, do some style and comment cleanups. No functional changes.
Approved by: kib (mentor)
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290273 |
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02-Nov-2015 |
zbb |
Add support for branch instruction on armv7 with ptrace single step
Previous code supported only "continuous" code without any kind of branch instructions. To change that, new function was implemented which parses current instruction and returns an addres where the jump might happen (alternative addr). mdthread structure was extended to support two breakpoints (one directly below current instruction and the second placed at the alternative location). One of them must trigger regardless the instruction has or has not been executed due to condition field. Upon cleanup, both software breakpoints are removed.
This implementation parses only the most common instructions that are present in the code (like 99.99% of all), but there is a chance there are some left, not covered by the parsing routine. Parsing is done only for 32-bit instruction, no Thumb nor Thumb-2 support is provided.
Reviewed by: kib Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf Sponsored by: Juniper Networks Inc. Differential Revision: https://reviews.freebsd.org/D4021
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286725 |
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13-Aug-2015 |
marcel |
The Broadcom BCM56060 chip has a Cortex-A9R4 core.
Submitted by: Steve Kiernan <stevek@juniper.net> Reviewed by: imp@ Differential Revision: https://reviews.freebsd.org/D3357
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282547 |
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06-May-2015 |
zbb |
Add new CP15 operations and DB_SHOW_COMMAND to print CP15 registers
Submitted by: Wojciech Macek <wma@semihalf.com> Reviewed by: imp, Michal Meloun <meloun@miracle.cz> Obtained from: Semihalf
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278518 |
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10-Feb-2015 |
zbb |
Resolve cache line size from CP15
Switch the cache line size during invalidations/flushes to be read from CP15 cache type register.
Submitted by: Wojciech Macek <wma@semihalf.com> Reviewed by: ian, imp Obtained from: Semihalf
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277156 |
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13-Jan-2015 |
ganbold |
Correct cpu type, it was rather Cortex A12 R0.
Approved by: stas (mentor)
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277116 |
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13-Jan-2015 |
ganbold |
Add CPU ID for ARM Cortex A17.
Approved by: stas (mentor)
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276638 |
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03-Jan-2015 |
ian |
Add a new trap-v6.c which has support for all armv7 exceptions. This mostly paves the way for the new pmap code, and shouldn't result in any noticible behavior differences.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz
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271398 |
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10-Sep-2014 |
andrew |
Unify interrupts bit definition and usage. While here remove PSR_C_bit.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>, Michal Meloun <meloun at miracle.cz> Differential Revision: https://reviews.freebsd.org/D754
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271394 |
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10-Sep-2014 |
andrew |
Add more register values to armreg.h and remove CPU_CONTROL_32BP_ENABLE from asm.h as they were already defined in armreg.h.
Submitted by: Michal Meloun <meloun at miracle.cz>
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263982 |
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01-Apr-2014 |
br |
Add Cortex-A15 cpu id revisions.
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262958 |
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09-Mar-2014 |
ian |
Remove all traces of support for ARM chips prior to the arm9 series. We never actually ran on these chips (other than using SA1 support in an emulator to do the early porting to FreeBSD long long ago). The clutter and complexity of some of this code keeps getting in the way of other maintenance, so it's time to go.
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261808 |
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12-Feb-2014 |
ian |
Use the right symbols for determining arm architecture. Include the necessary header file which has the new FAULT_WNR symbol defined in it.
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259640 |
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19-Dec-2013 |
ganbold |
Add identification and necessary type checks for Krait CPU cores. Krait CPU is used in Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064.
Approved by: stas (mentor)
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258780 |
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30-Nov-2013 |
eadler |
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result.
This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases.
A similar change was made in OpenBSD.
Discussed with: -arch, rdivacky Reviewed by: cperciva
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257281 |
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28-Oct-2013 |
zbb |
Remove not working and deprecated PJ4Bv6 support
Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada SoC family. Current in-tree support for PJ4Bv6 will not work and also there should be no platforms in active use that would incorporate that CPU revision.
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256629 |
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16-Oct-2013 |
br |
Add CPU ID for ARM Cortex A5.
Approved by: cognet (mentor)
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253857 |
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01-Aug-2013 |
ganbold |
Add identification for Cortex-A7 (R0) cores.
Reviewed by: cognet@
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252361 |
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28-Jun-2013 |
ray |
Add identification for Cortex-A15 (R0) cores.
Submitted by: Ruslan Bukin <br@bsdpad.com>
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250928 |
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23-May-2013 |
gber |
Switch to AP[2:1] access permissions model. Store "referenced" bit in PTE.
Enable Access Flag in CPU control. With AF enabled each valid mapping needs to have referenced bit in PTE set in order to be able to cache it in the TLB.
AP[0] bit is to be used as reference flag. All access permissions are encoded by AP[2:1] wherein AP[1] is in fact "user enable" and AP[2](APX) is "write disable".
All mappings are always set to be valid. Reference emulation is performed by setting/clearing reference flag in PTE.
md.pvh_attrs are no longer necessary however pv_flags are still being used for now.
Marking vm_page as "dirty" or "referenced" is being performed on: - page or flag fault servicing in pmap_fault_fixup(), basing on the fault type - vm_fault servicing in pmap_enter() according to the desired protections and faulty access type Redundant page marking has been removed as on ARM we know exactly when the particular page is referenced or is going to be written.
Submitted by: Zbigniew Bodek <zbb@semihalf.com> Sponsored by: The FreeBSD Foundation, Semihalf
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249999 |
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27-Apr-2013 |
wkoszek |
Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port.
Submitted by: Thomas Skibo <ThomasSkibo (at) sbcglobal.net> Tested by: wkoszek (ZedBoard) Reviewed by: wkoszek, freebsd-arm@ (no objections raised)
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244480 |
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20-Dec-2012 |
gonzo |
Replace generic ARM11 option with more specific support for ARM1136 and ARM1176
Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
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240486 |
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14-Sep-2012 |
gber |
Support identification of new PJ4B cores.
Obtained from: Semihalf
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239268 |
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15-Aug-2012 |
gonzo |
Merging projects/armv6, part 1
Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
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236992 |
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13-Jun-2012 |
imp |
trim trailing whitespace
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234337 |
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16-Apr-2012 |
andrew |
Replace the C implementation of __aeabi_read_tp with an assembly version. This ensures we follow the ABI by preserving registers r1-r3.
Reviewed by: jmallett, imp
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234006 |
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07-Apr-2012 |
stas |
- Revert part of r234005, which I did not intend to commit. Sorry! :(
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234005 |
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07-Apr-2012 |
stas |
- Add kernel config file for QEMU-emulated gumstix board.
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204121 |
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20-Feb-2010 |
kevlo |
Correct both FA526/FA626TE cpu ids since the cpu id is always masked with 0xfffffff0
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203852 |
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14-Feb-2010 |
kevlo |
Correct cpu id for FA526. While I'm here, add cpu id for FA626TE.
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186417 |
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23-Dec-2008 |
sam |
add IXP465 and generic IXP425 definition
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186352 |
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20-Dec-2008 |
sam |
Merge support for Gateworks Cambria boards: o add support for IXP435 cpu's (e.g. 64 irq's) o add support for Cambria-specific devices: npe, led's (front panel and octal latch), ehci, mcu, ide cf o redo memory mapping for xscale/ixp4xx boards: previously memory was assumed aliased to 0x10000000 but this appears to be true only for ixp425 systems and breaks operation on others; rework so memory is assumed to start at 0 o rework NPE configuration support to use NPE id's instead of port #'s; these changes also rename the associated MAC's to follow the NPE's they are attached to o update npe firmware to latest rev (same license) and update default fw imageid's to match; in particular this adds NPE-A and crypto support o re-style NPE fw handling code and add a console msg identifying the attributes of the loaded fw o fix numerous problems with handling failures during npe setup o fix npe rx q setup; need to spin waiting for mailbox responses during early boot stages as qmgr interrupts are not delivered; this fixes the problem where all 8 traffic classifications were not tied to the rx q (and eliminates the console msg "remember to fix rx q setup") o add DELAY to npe MII wait logic for IXP435 o strip down builtin phys->virt address translation table in resource handling to just those resources that require it and add a console msg to alert people when this (kludge) table needs to be extended o purge a bunch of dead netbsd-ism's o cleanup avila led driver o add Cambria support to boot2 and rework code for better multi-board support
Notes: 1. NPE-A doesn't work and causes NPE-C to stop working; it is disabled in the hints 2. USB isn't working yet; controller communicates ok but device discovery fails 3. Cambria support must be configured separately from IXP425 boards; multi-board support is TBD
Sponsored by: Hobnob, Gateworks (board donation) Reviewed by: imp
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183835 |
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13-Oct-2008 |
raj |
Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.
They are compliant with ARMv5TE and integrated on 88F6281 (Kirkwood) and MV78100 (Discovery) system-on-chip families.
Obtained from: Marvell, Semihalf
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172734 |
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18-Oct-2007 |
imp |
Merge definitions for ARM9E, ARM10 and ARM11 processors from p4 (which got them from NetBSD).
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171630 |
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27-Jul-2007 |
cognet |
XScale core 3 definitions.
Approved by: re (blanket)
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164080 |
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07-Nov-2006 |
cognet |
Identify the xscale 81342.
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161592 |
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24-Aug-2006 |
cognet |
Finally bring it support for the i80219 XScale processor.
Submitted by: Max M. Boyarov <m.boyarov bsd by>
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152653 |
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21-Nov-2005 |
cognet |
Add an alternate ID for the arm920t (the real solution is to have per-cpu class masks, but oh well).
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139735 |
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05-Jan-2005 |
imp |
Start all license statements with /*-
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129198 |
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14-May-2004 |
cognet |
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
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