armreg.h revision 290648
1/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * $FreeBSD: head/sys/arm/include/armreg.h 290648 2015-11-10 12:02:41Z mmel $ 39 */ 40 41#ifndef MACHINE_ARMREG_H 42#define MACHINE_ARMREG_H 43 44#include <machine/acle-compat.h> 45 46#define INSN_SIZE 4 47#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 48#define PSR_MODE 0x0000001f /* mode mask */ 49#define PSR_USR32_MODE 0x00000010 50#define PSR_FIQ32_MODE 0x00000011 51#define PSR_IRQ32_MODE 0x00000012 52#define PSR_SVC32_MODE 0x00000013 53#define PSR_MON32_MODE 0x00000016 54#define PSR_ABT32_MODE 0x00000017 55#define PSR_HYP32_MODE 0x0000001a 56#define PSR_UND32_MODE 0x0000001b 57#define PSR_SYS32_MODE 0x0000001f 58#define PSR_32_MODE 0x00000010 59#define PSR_T 0x00000020 /* Instruction set bit */ 60#define PSR_F 0x00000040 /* FIQ disable bit */ 61#define PSR_I 0x00000080 /* IRQ disable bit */ 62#define PSR_A 0x00000100 /* Imprecise abort bit */ 63#define PSR_E 0x00000200 /* Data endianess bit */ 64#define PSR_GE 0x000f0000 /* Greater than or equal to bits */ 65#define PSR_J 0x01000000 /* Java bit */ 66#define PSR_Q 0x08000000 /* Sticky overflow bit */ 67#define PSR_V 0x10000000 /* Overflow bit */ 68#define PSR_C 0x20000000 /* Carry bit */ 69#define PSR_Z 0x40000000 /* Zero bit */ 70#define PSR_N 0x80000000 /* Negative bit */ 71#define PSR_FLAGS 0xf0000000 /* Flags mask. */ 72 73/* The high-order byte is always the implementor */ 74#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 75#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 76#define CPU_ID_DEC 0x44000000 /* 'D' */ 77#define CPU_ID_INTEL 0x69000000 /* 'i' */ 78#define CPU_ID_TI 0x54000000 /* 'T' */ 79#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 80 81/* How to decide what format the CPUID is in. */ 82#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 83#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 84#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 85 86/* On recent ARMs this byte holds the architecture and variant (sub-model) */ 87#define CPU_ID_ARCH_MASK 0x000f0000 88#define CPU_ID_ARCH_V3 0x00000000 89#define CPU_ID_ARCH_V4 0x00010000 90#define CPU_ID_ARCH_V4T 0x00020000 91#define CPU_ID_ARCH_V5 0x00030000 92#define CPU_ID_ARCH_V5T 0x00040000 93#define CPU_ID_ARCH_V5TE 0x00050000 94#define CPU_ID_ARCH_V5TEJ 0x00060000 95#define CPU_ID_ARCH_V6 0x00070000 96#define CPU_ID_CPUID_SCHEME 0x000f0000 97#define CPU_ID_VARIANT_MASK 0x00f00000 98 99/* Next three nybbles are part number */ 100#define CPU_ID_PARTNO_MASK 0x0000fff0 101 102/* Intel XScale has sub fields in part number */ 103#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 104#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 105#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 106 107/* And finally, the revision number. */ 108#define CPU_ID_REVISION_MASK 0x0000000f 109 110/* Individual CPUs are probably best IDed by everything but the revision. */ 111#define CPU_ID_CPU_MASK 0xfffffff0 112 113/* ARM9 and later CPUs */ 114#define CPU_ID_ARM920T 0x41129200 115#define CPU_ID_ARM920T_ALT 0x41009200 116#define CPU_ID_ARM922T 0x41029220 117#define CPU_ID_ARM926EJS 0x41069260 118#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 119#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 120#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 121#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 122#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 123#define CPU_ID_ARM1022ES 0x4105a220 124#define CPU_ID_ARM1026EJS 0x4106a260 125#define CPU_ID_ARM1136JS 0x4107b360 126#define CPU_ID_ARM1136JSR1 0x4117b360 127#define CPU_ID_ARM1176JZS 0x410fb760 128#define CPU_ID_CORTEXA5 0x410fc050 129#define CPU_ID_CORTEXA7 0x410fc070 130#define CPU_ID_CORTEXA8R1 0x411fc080 131#define CPU_ID_CORTEXA8R2 0x412fc080 132#define CPU_ID_CORTEXA8R3 0x413fc080 133#define CPU_ID_CORTEXA9R1 0x411fc090 134#define CPU_ID_CORTEXA9R2 0x412fc090 135#define CPU_ID_CORTEXA9R3 0x413fc090 136#define CPU_ID_CORTEXA9R4 0x414fc090 137#define CPU_ID_CORTEXA12R0 0x410fc0d0 138#define CPU_ID_CORTEXA15R0 0x410fc0f0 139#define CPU_ID_CORTEXA15R1 0x411fc0f0 140#define CPU_ID_CORTEXA15R2 0x412fc0f0 141#define CPU_ID_CORTEXA15R3 0x413fc0f0 142#define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */ 143#define CPU_ID_TI925T 0x54029250 144#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 145#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 146#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 147 148/* 149 * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported 150 * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. 151 */ 152#ifdef SOC_MV_LOKIPLUS 153#define CPU_ID_MV88FR571_41 0x00000000 154#else 155#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 156#endif 157 158#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ 159#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ 160/* Marvell's CPUIDs with ARM ID in implementor field */ 161#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ 162 163#define CPU_ID_FA526 0x66015260 164#define CPU_ID_FA626TE 0x66056260 165#define CPU_ID_80200 0x69052000 166#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 167#define CPU_ID_PXA210 0x69052120 168#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 169#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 170#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 171#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 172#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 173#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 174#define CPU_ID_PXA27X 0x69054110 175#define CPU_ID_80321_400 0x69052420 176#define CPU_ID_80321_600 0x69052430 177#define CPU_ID_80321_400_B0 0x69052c20 178#define CPU_ID_80321_600_B0 0x69052c30 179#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 180#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 181#define CPU_ID_81342 0x69056810 182#define CPU_ID_IXP425 0x690541c0 183#define CPU_ID_IXP425_533 0x690541c0 184#define CPU_ID_IXP425_400 0x690541d0 185#define CPU_ID_IXP425_266 0x690541f0 186#define CPU_ID_IXP435 0x69054040 187#define CPU_ID_IXP465 0x69054200 188 189/* CPUID registers */ 190#define ARM_PFR0_ARM_ISA_MASK 0x0000000f 191 192#define ARM_PFR0_THUMB_MASK 0x000000f0 193#define ARM_PFR0_THUMB 0x10 194#define ARM_PFR0_THUMB2 0x30 195 196#define ARM_PFR0_JAZELLE_MASK 0x00000f00 197#define ARM_PFR0_THUMBEE_MASK 0x0000f000 198 199#define ARM_PFR1_ARMV4_MASK 0x0000000f 200#define ARM_PFR1_SEC_EXT_MASK 0x000000f0 201#define ARM_PFR1_MICROCTRL_MASK 0x00000f00 202 203/* 204 * Post-ARM3 CP15 registers: 205 * 206 * 1 Control register 207 * 208 * 2 Translation Table Base 209 * 210 * 3 Domain Access Control 211 * 212 * 4 Reserved 213 * 214 * 5 Fault Status 215 * 216 * 6 Fault Address 217 * 218 * 7 Cache/write-buffer Control 219 * 220 * 8 TLB Control 221 * 222 * 9 Cache Lockdown 223 * 224 * 10 TLB Lockdown 225 * 226 * 11 Reserved 227 * 228 * 12 Reserved 229 * 230 * 13 Process ID (for FCSE) 231 * 232 * 14 Reserved 233 * 234 * 15 Implementation Dependent 235 */ 236 237/* Some of the definitions below need cleaning up for V3/V4 architectures */ 238 239/* CPU control register (CP15 register 1) */ 240#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 241#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 242#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 243#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 244#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 245#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 246#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 247#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 248#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 249#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 250#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 251#define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */ 252#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 253#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 254#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 255#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 256#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 257#define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */ 258#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 259#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 260#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ 261#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 262#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 263#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 264#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 265#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/ 266#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */ 267#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 268 269#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 270 271/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 272#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 273#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 274#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 275#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 276#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 277#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 278#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 279#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 280 281/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 282#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 283 /* This is an undocumented flag 284 * used to work around a cache bug 285 * in r0 steppings. See errata 286 * 364296. 287 */ 288/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 289#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 290#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 291#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 292#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 293 294/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 295#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 296#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 297/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 298#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 299#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 300#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 301#define XSCALE_AUXCTL_MD_MASK 0x00000030 302 303/* Xscale Core 3 only */ 304#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 305 306/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ 307#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ 308#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ 309#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ 310#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ 311#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 312#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ 313#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ 314#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ 315#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ 316#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ 317 318/* Cache type register definitions */ 319#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 320#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 321#define CPU_CT_S (1U << 24) /* split cache */ 322#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 323#define CPU_CT_FORMAT(x) ((x) >> 29) 324/* Cache type register definitions for ARM v7 */ 325#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */ 326#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */ 327 328#define CPU_CT_CTYPE_WT 0 /* write-through */ 329#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 330#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 331#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 332#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 333 334#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 335#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 336#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 337#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 338 339#define CPU_CT_ARMV7 0x4 340/* ARM v7 Cache type definitions */ 341#define CPUV7_CT_CTYPE_WT (1U << 31) 342#define CPUV7_CT_CTYPE_WB (1 << 30) 343#define CPUV7_CT_CTYPE_RA (1 << 29) 344#define CPUV7_CT_CTYPE_WA (1 << 28) 345 346#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ 347#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ 348#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ 349 350#define CPUV7_L2CTLR_NPROC_SHIFT 24 351#define CPUV7_L2CTLR_NPROC(r) ((((r) >> CPUV7_L2CTLR_NPROC_SHIFT) & 3) + 1) 352 353#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) 354#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) 355#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) 356#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) 357 358#define CACHE_ICACHE 1 359#define CACHE_DCACHE 2 360#define CACHE_SEP_CACHE 3 361#define CACHE_UNI_CACHE 4 362 363/* Fault status register definitions */ 364#define FAULT_USER 0x10 365 366#if __ARM_ARCH < 6 367#define FAULT_TYPE_MASK 0x0f 368#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 369#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 370#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 371#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 372#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 373#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 374#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 375#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 376#define FAULT_ALIGN_0 0x01 /* Alignment */ 377#define FAULT_ALIGN_1 0x03 /* Alignment */ 378#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 379#define FAULT_TRANS_F 0x06 /* Translation -- Flag */ 380#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 381#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 382#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 383#define FAULT_PERM_S 0x0d /* Permission -- Section */ 384#define FAULT_PERM_P 0x0f /* Permission -- Page */ 385 386#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 387#define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */ 388#define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */ 389 390#else /* __ARM_ARCH < 6 */ 391 392#define FAULT_ALIGN 0x001 /* Alignment Fault */ 393#define FAULT_DEBUG 0x002 /* Debug Event */ 394#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */ 395#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */ 396#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */ 397#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */ 398#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */ 399#define FAULT_EA_PREC 0x008 /* External Abort */ 400#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */ 401#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */ 402#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */ 403#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */ 404#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */ 405#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */ 406#define FAULT_TLB_CONFLICT 0x010 /* TLB Conflict Abort */ 407#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */ 408#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */ 409#define FAULT_PARITY 0x019 /* Parity Error */ 410#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */ 411#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */ 412 413#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \ 414 ((((fsr) & (1 << 10)) >> (10 - 4)))) 415#define FSR_LPAE (1 << 9) /* LPAE indicator */ 416#define FSR_WNR (1 << 11) /* Write-not-Read access */ 417#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/ 418#define FSR_CM (1 << 13) /* Cache maintenance fault */ 419#endif /* !__ARM_ARCH < 6 */ 420 421/* 422 * Address of the vector page, low and high versions. 423 */ 424#ifndef __ASSEMBLER__ 425#define ARM_VECTORS_LOW 0x00000000U 426#define ARM_VECTORS_HIGH 0xffff0000U 427#else 428#define ARM_VECTORS_LOW 0 429#define ARM_VECTORS_HIGH 0xffff0000 430#endif 431 432/* 433 * ARM Instructions 434 * 435 * 3 3 2 2 2 436 * 1 0 9 8 7 0 437 * +-------+-------------------------------------------------------+ 438 * | cond | instruction dependant | 439 * |c c c c| | 440 * +-------+-------------------------------------------------------+ 441 */ 442 443#define INSN_SIZE 4 /* Always 4 bytes */ 444#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 445#define INSN_COND_AL 0xe0000000 /* Always condition */ 446 447/* ARM register defines */ 448#define ARM_REG_SIZE 4 449#define ARM_REG_NUM_PC 15 450#define ARM_REG_NUM_LR 14 451#define ARM_REG_NUM_SP 13 452 453#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 454 455#endif /* !MACHINE_ARMREG_H */ 456