if_ti.c revision 219547
1139825Simp/*- 245386Swpaul * Copyright (c) 1997, 1998, 1999 345386Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 445386Swpaul * 545386Swpaul * Redistribution and use in source and binary forms, with or without 645386Swpaul * modification, are permitted provided that the following conditions 745386Swpaul * are met: 845386Swpaul * 1. Redistributions of source code must retain the above copyright 945386Swpaul * notice, this list of conditions and the following disclaimer. 1045386Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1145386Swpaul * notice, this list of conditions and the following disclaimer in the 1245386Swpaul * documentation and/or other materials provided with the distribution. 1345386Swpaul * 3. All advertising materials mentioning features or use of this software 1445386Swpaul * must display the following acknowledgement: 1545386Swpaul * This product includes software developed by Bill Paul. 1645386Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1745386Swpaul * may be used to endorse or promote products derived from this software 1845386Swpaul * without specific prior written permission. 1945386Swpaul * 2045386Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2145386Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2245386Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2345386Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2445386Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2545386Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2645386Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2745386Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2845386Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2945386Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3045386Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3145386Swpaul */ 3245386Swpaul 3345386Swpaul/* 3445386Swpaul * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3545386Swpaul * Manuals, sample driver and firmware source kits are available 3645386Swpaul * from http://www.alteon.com/support/openkits. 37131652Sbms * 3845386Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 3945386Swpaul * Electrical Engineering Department 4045386Swpaul * Columbia University, New York City 4145386Swpaul */ 4245386Swpaul 4345386Swpaul/* 4445386Swpaul * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4545386Swpaul * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4645386Swpaul * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4745386Swpaul * Tigon supports hardware IP, TCP and UCP checksumming, multicast 4845386Swpaul * filtering and jumbo (9014 byte) frames. The hardware is largely 4945386Swpaul * controlled by firmware, which must be loaded into the NIC during 5045386Swpaul * initialization. 5145386Swpaul * 5245386Swpaul * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5345386Swpaul * revision, which supports new features such as extended commands, 5445386Swpaul * extended jumbo receive ring desciptors and a mini receive ring. 5545386Swpaul * 5645386Swpaul * Alteon Networks is to be commended for releasing such a vast amount 5745386Swpaul * of development material for the Tigon NIC without requiring an NDA 5845386Swpaul * (although they really should have done it a long time ago). With 5945386Swpaul * any luck, the other vendors will finally wise up and follow Alteon's 6045386Swpaul * stellar example. 6145386Swpaul * 6245386Swpaul * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6345386Swpaul * this driver by #including it as a C header file. This bloats the 6445386Swpaul * driver somewhat, but it's the easiest method considering that the 6545386Swpaul * driver code and firmware code need to be kept in sync. The source 6645386Swpaul * for the firmware is not provided with the FreeBSD distribution since 6745386Swpaul * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 6845386Swpaul * 6945386Swpaul * The following people deserve special thanks: 7045386Swpaul * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7145386Swpaul * for testing 7245386Swpaul * - Raymond Lee of Netgear, for providing a pair of Netgear 7345386Swpaul * GA620 Tigon 2 boards for testing 7445386Swpaul * - Ulf Zimmermann, for bringing the GA260 to my attention and 7545386Swpaul * convincing me to write this driver. 7645386Swpaul * - Andrew Gallatin for providing FreeBSD/Alpha support. 7745386Swpaul */ 7845386Swpaul 79113038Sobrien#include <sys/cdefs.h> 80113038Sobrien__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 219547 2011-03-11 22:32:17Z marius $"); 81113038Sobrien 8298849Sken#include "opt_ti.h" 8398849Sken 8445386Swpaul#include <sys/param.h> 8545386Swpaul#include <sys/systm.h> 8645386Swpaul#include <sys/sockio.h> 8745386Swpaul#include <sys/mbuf.h> 8845386Swpaul#include <sys/malloc.h> 8945386Swpaul#include <sys/kernel.h> 90129878Sphk#include <sys/module.h> 9145386Swpaul#include <sys/socket.h> 9245386Swpaul#include <sys/queue.h> 9398849Sken#include <sys/conf.h> 94153770Syongari#include <sys/sf_buf.h> 9545386Swpaul 9645386Swpaul#include <net/if.h> 9745386Swpaul#include <net/if_arp.h> 9845386Swpaul#include <net/ethernet.h> 9945386Swpaul#include <net/if_dl.h> 10045386Swpaul#include <net/if_media.h> 10183115Sbrooks#include <net/if_types.h> 10283115Sbrooks#include <net/if_vlan_var.h> 10345386Swpaul 10445386Swpaul#include <net/bpf.h> 10545386Swpaul 10645386Swpaul#include <netinet/in_systm.h> 10745386Swpaul#include <netinet/in.h> 10845386Swpaul#include <netinet/ip.h> 10945386Swpaul 11045386Swpaul#include <machine/bus.h> 11149011Swpaul#include <machine/resource.h> 11249011Swpaul#include <sys/bus.h> 11349011Swpaul#include <sys/rman.h> 11445386Swpaul 11598849Sken/* #define TI_PRIVATE_JUMBOS */ 116153770Syongari#ifndef TI_PRIVATE_JUMBOS 117153770Syongari#include <vm/vm.h> 11898849Sken#include <vm/vm_page.h> 119153770Syongari#endif 12098849Sken 121119288Simp#include <dev/pci/pcireg.h> 122119288Simp#include <dev/pci/pcivar.h> 12345386Swpaul 12498849Sken#include <sys/tiio.h> 125153280Sscottl#include <dev/ti/if_tireg.h> 126153280Sscottl#include <dev/ti/ti_fw.h> 127153280Sscottl#include <dev/ti/ti_fw2.h> 12845386Swpaul 12958698Sjlemon#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 13098849Sken/* 13198849Sken * We can only turn on header splitting if we're using extended receive 13298849Sken * BDs. 13398849Sken */ 13498849Sken#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 13598849Sken#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 13698849Sken#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 13745386Swpaul 13898849Skentypedef enum { 13998849Sken TI_SWAP_HTON, 14098849Sken TI_SWAP_NTOH 14198849Sken} ti_swap_type; 14298849Sken 14398849Sken 14445386Swpaul/* 14545386Swpaul * Various supported device vendors/types and their names. 14645386Swpaul */ 14745386Swpaul 148219547Smariusstatic const struct ti_type const ti_devs[] = { 14945386Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC, 15063702Swpaul "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 15163699Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 15263702Swpaul "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 15345386Swpaul { TC_VENDORID, TC_DEVICEID_3C985, 15445386Swpaul "3Com 3c985-SX Gigabit Ethernet" }, 15545386Swpaul { NG_VENDORID, NG_DEVICEID_GA620, 15664139Swpaul "Netgear GA620 1000baseSX Gigabit Ethernet" }, 15764139Swpaul { NG_VENDORID, NG_DEVICEID_GA620T, 15864139Swpaul "Netgear GA620 1000baseT Gigabit Ethernet" }, 15945386Swpaul { SGI_VENDORID, SGI_DEVICEID_TIGON, 16045386Swpaul "Silicon Graphics Gigabit Ethernet" }, 16156206Swpaul { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 16256206Swpaul "Farallon PN9000SX Gigabit Ethernet" }, 16345386Swpaul { 0, 0, NULL } 16445386Swpaul}; 16545386Swpaul 16698849Sken 16798849Skenstatic d_open_t ti_open; 16898849Skenstatic d_close_t ti_close; 16998849Skenstatic d_ioctl_t ti_ioctl2; 17098849Sken 17198849Skenstatic struct cdevsw ti_cdevsw = { 172126080Sphk .d_version = D_VERSION, 173153281Sscottl .d_flags = 0, 174111815Sphk .d_open = ti_open, 175111815Sphk .d_close = ti_close, 176111815Sphk .d_ioctl = ti_ioctl2, 177111815Sphk .d_name = "ti", 17898849Sken}; 17998849Sken 180142407Simpstatic int ti_probe(device_t); 181142407Simpstatic int ti_attach(device_t); 182142407Simpstatic int ti_detach(device_t); 183142407Simpstatic void ti_txeof(struct ti_softc *); 184142407Simpstatic void ti_rxeof(struct ti_softc *); 18545386Swpaul 186142407Simpstatic void ti_stats_update(struct ti_softc *); 187153982Syongaristatic int ti_encap(struct ti_softc *, struct mbuf **); 18845386Swpaul 189142407Simpstatic void ti_intr(void *); 190142407Simpstatic void ti_start(struct ifnet *); 191153770Syongaristatic void ti_start_locked(struct ifnet *); 192142407Simpstatic int ti_ioctl(struct ifnet *, u_long, caddr_t); 193142407Simpstatic void ti_init(void *); 194153770Syongaristatic void ti_init_locked(void *); 195142407Simpstatic void ti_init2(struct ti_softc *); 196142407Simpstatic void ti_stop(struct ti_softc *); 197199559Sjhbstatic void ti_watchdog(void *); 198173839Syongaristatic int ti_shutdown(device_t); 199142407Simpstatic int ti_ifmedia_upd(struct ifnet *); 200142407Simpstatic void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 20145386Swpaul 202142407Simpstatic u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 203142407Simpstatic u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 204142407Simpstatic int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 20545386Swpaul 206142407Simpstatic void ti_add_mcast(struct ti_softc *, struct ether_addr *); 207142407Simpstatic void ti_del_mcast(struct ti_softc *, struct ether_addr *); 208142407Simpstatic void ti_setmulti(struct ti_softc *); 20945386Swpaul 210153770Syongaristatic void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *); 211153770Syongaristatic void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, void *); 212153770Syongaristatic void ti_mem_zero(struct ti_softc *, u_int32_t, u_int32_t); 213142407Simpstatic int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int); 214142407Simpstatic int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, 215142407Simp int, int, int); 216142407Simpstatic int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 217142407Simpstatic void ti_loadfw(struct ti_softc *); 218142407Simpstatic void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 219142407Simpstatic void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 220142407Simpstatic void ti_handle_events(struct ti_softc *); 221153396Sscottlstatic int ti_alloc_dmamaps(struct ti_softc *); 222153396Sscottlstatic void ti_free_dmamaps(struct ti_softc *); 223153396Sscottlstatic int ti_alloc_jumbo_mem(struct ti_softc *); 22498849Sken#ifdef TI_PRIVATE_JUMBOS 225142407Simpstatic void *ti_jalloc(struct ti_softc *); 226142407Simpstatic void ti_jfree(void *, void *); 22798849Sken#endif /* TI_PRIVATE_JUMBOS */ 228142407Simpstatic int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 229142407Simpstatic int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 230142407Simpstatic int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 231142407Simpstatic int ti_init_rx_ring_std(struct ti_softc *); 232142407Simpstatic void ti_free_rx_ring_std(struct ti_softc *); 233142407Simpstatic int ti_init_rx_ring_jumbo(struct ti_softc *); 234142407Simpstatic void ti_free_rx_ring_jumbo(struct ti_softc *); 235142407Simpstatic int ti_init_rx_ring_mini(struct ti_softc *); 236142407Simpstatic void ti_free_rx_ring_mini(struct ti_softc *); 237142407Simpstatic void ti_free_tx_ring(struct ti_softc *); 238142407Simpstatic int ti_init_tx_ring(struct ti_softc *); 23945386Swpaul 240142407Simpstatic int ti_64bitslot_war(struct ti_softc *); 241142407Simpstatic int ti_chipinit(struct ti_softc *); 242142407Simpstatic int ti_gibinit(struct ti_softc *); 24345386Swpaul 24498849Sken#ifdef TI_JUMBO_HDRSPLIT 24599013Speterstatic __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 24699013Speter int pkt_len, int idx); 24798849Sken#endif /* TI_JUMBO_HDRSPLIT */ 24898849Sken 24949011Swpaulstatic device_method_t ti_methods[] = { 25049011Swpaul /* Device interface */ 25149011Swpaul DEVMETHOD(device_probe, ti_probe), 25249011Swpaul DEVMETHOD(device_attach, ti_attach), 25349011Swpaul DEVMETHOD(device_detach, ti_detach), 25449011Swpaul DEVMETHOD(device_shutdown, ti_shutdown), 25549011Swpaul { 0, 0 } 25649011Swpaul}; 25749011Swpaul 25849011Swpaulstatic driver_t ti_driver = { 25951455Swpaul "ti", 26049011Swpaul ti_methods, 26149011Swpaul sizeof(struct ti_softc) 26249011Swpaul}; 26349011Swpaul 26449011Swpaulstatic devclass_t ti_devclass; 26549011Swpaul 266113506SmdoddDRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 267113506SmdoddMODULE_DEPEND(ti, pci, 1, 1, 1); 268113506SmdoddMODULE_DEPEND(ti, ether, 1, 1, 1); 26949011Swpaul 27045386Swpaul/* 27145386Swpaul * Send an instruction or address to the EEPROM, check for ACK. 27245386Swpaul */ 27345386Swpaulstatic u_int32_t ti_eeprom_putbyte(sc, byte) 27445386Swpaul struct ti_softc *sc; 27545386Swpaul int byte; 27645386Swpaul{ 277153770Syongari int i, ack = 0; 27845386Swpaul 27945386Swpaul /* 28045386Swpaul * Make sure we're in TX mode. 28145386Swpaul */ 28245386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 28345386Swpaul 28445386Swpaul /* 28545386Swpaul * Feed in each bit and stobe the clock. 28645386Swpaul */ 28745386Swpaul for (i = 0x80; i; i >>= 1) { 28845386Swpaul if (byte & i) { 28945386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 29045386Swpaul } else { 29145386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 29245386Swpaul } 29345386Swpaul DELAY(1); 29445386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 29545386Swpaul DELAY(1); 29645386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 29745386Swpaul } 29845386Swpaul 29945386Swpaul /* 30045386Swpaul * Turn off TX mode. 30145386Swpaul */ 30245386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 30345386Swpaul 30445386Swpaul /* 30545386Swpaul * Check for ack. 30645386Swpaul */ 30745386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 30845386Swpaul ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 30945386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 31045386Swpaul 311131654Sbms return (ack); 31245386Swpaul} 31345386Swpaul 31445386Swpaul/* 31545386Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 31645386Swpaul * We have to send two address bytes since the EEPROM can hold 31745386Swpaul * more than 256 bytes of data. 31845386Swpaul */ 31945386Swpaulstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 32045386Swpaul struct ti_softc *sc; 32145386Swpaul int addr; 32245386Swpaul u_int8_t *dest; 32345386Swpaul{ 324153770Syongari int i; 32545386Swpaul u_int8_t byte = 0; 32645386Swpaul 32745386Swpaul EEPROM_START; 32845386Swpaul 32945386Swpaul /* 33045386Swpaul * Send write control code to EEPROM. 33145386Swpaul */ 33245386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 333162321Sglebius device_printf(sc->ti_dev, 334150719Sjhb "failed to send write command, status: %x\n", 335150719Sjhb CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 336131654Sbms return (1); 33745386Swpaul } 33845386Swpaul 33945386Swpaul /* 34045386Swpaul * Send first byte of address of byte we want to read. 34145386Swpaul */ 34245386Swpaul if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 343162321Sglebius device_printf(sc->ti_dev, "failed to send address, status: %x\n", 344150719Sjhb CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 345131654Sbms return (1); 34645386Swpaul } 34745386Swpaul /* 34845386Swpaul * Send second byte address of byte we want to read. 34945386Swpaul */ 35045386Swpaul if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 351162321Sglebius device_printf(sc->ti_dev, "failed to send address, status: %x\n", 352150719Sjhb CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 353131654Sbms return (1); 35445386Swpaul } 35545386Swpaul 35645386Swpaul EEPROM_STOP; 35745386Swpaul EEPROM_START; 35845386Swpaul /* 35945386Swpaul * Send read control code to EEPROM. 36045386Swpaul */ 36145386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 362162321Sglebius device_printf(sc->ti_dev, 363150719Sjhb "failed to send read command, status: %x\n", 364150719Sjhb CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 365131654Sbms return (1); 36645386Swpaul } 36745386Swpaul 36845386Swpaul /* 36945386Swpaul * Start reading bits from EEPROM. 37045386Swpaul */ 37145386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 37245386Swpaul for (i = 0x80; i; i >>= 1) { 37345386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 37445386Swpaul DELAY(1); 37545386Swpaul if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 37645386Swpaul byte |= i; 37745386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 37845386Swpaul DELAY(1); 37945386Swpaul } 38045386Swpaul 38145386Swpaul EEPROM_STOP; 38245386Swpaul 38345386Swpaul /* 38445386Swpaul * No ACK generated for read, so just return byte. 38545386Swpaul */ 38645386Swpaul 38745386Swpaul *dest = byte; 38845386Swpaul 389131654Sbms return (0); 39045386Swpaul} 39145386Swpaul 39245386Swpaul/* 39345386Swpaul * Read a sequence of bytes from the EEPROM. 39445386Swpaul */ 395102336Salfredstatic int 396102336Salfredti_read_eeprom(sc, dest, off, cnt) 39745386Swpaul struct ti_softc *sc; 39845386Swpaul caddr_t dest; 39945386Swpaul int off; 40045386Swpaul int cnt; 40145386Swpaul{ 40245386Swpaul int err = 0, i; 40345386Swpaul u_int8_t byte = 0; 40445386Swpaul 40545386Swpaul for (i = 0; i < cnt; i++) { 40645386Swpaul err = ti_eeprom_getbyte(sc, off + i, &byte); 40745386Swpaul if (err) 40845386Swpaul break; 40945386Swpaul *(dest + i) = byte; 41045386Swpaul } 41145386Swpaul 412131654Sbms return (err ? 1 : 0); 41345386Swpaul} 41445386Swpaul 41545386Swpaul/* 416153770Syongari * NIC memory read function. 417153770Syongari * Can be used to copy data from NIC local memory. 41845386Swpaul */ 419102336Salfredstatic void 420153770Syongariti_mem_read(sc, addr, len, buf) 42145386Swpaul struct ti_softc *sc; 42245386Swpaul u_int32_t addr, len; 423153770Syongari void *buf; 42445386Swpaul{ 42545386Swpaul int segptr, segsize, cnt; 426153770Syongari char *ptr; 42745386Swpaul 42845386Swpaul segptr = addr; 42945386Swpaul cnt = len; 43045386Swpaul ptr = buf; 43145386Swpaul 432131654Sbms while (cnt) { 43345386Swpaul if (cnt < TI_WINLEN) 43445386Swpaul segsize = cnt; 43545386Swpaul else 43645386Swpaul segsize = TI_WINLEN - (segptr % TI_WINLEN); 43745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 438153770Syongari bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 439153770Syongari TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 440153770Syongari segsize / 4); 441153770Syongari ptr += segsize; 44245386Swpaul segptr += segsize; 44345386Swpaul cnt -= segsize; 44445386Swpaul } 44545386Swpaul} 44645386Swpaul 447153770Syongari 448153770Syongari/* 449153770Syongari * NIC memory write function. 450153770Syongari * Can be used to copy data into NIC local memory. 451153770Syongari */ 452153770Syongaristatic void 453153770Syongariti_mem_write(sc, addr, len, buf) 454153770Syongari struct ti_softc *sc; 455153770Syongari u_int32_t addr, len; 456153770Syongari void *buf; 457153770Syongari{ 458153770Syongari int segptr, segsize, cnt; 459153770Syongari char *ptr; 460153770Syongari 461153770Syongari segptr = addr; 462153770Syongari cnt = len; 463153770Syongari ptr = buf; 464153770Syongari 465153770Syongari while (cnt) { 466153770Syongari if (cnt < TI_WINLEN) 467153770Syongari segsize = cnt; 468153770Syongari else 469153770Syongari segsize = TI_WINLEN - (segptr % TI_WINLEN); 470153770Syongari CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 471153770Syongari bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 472153770Syongari TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 473153770Syongari segsize / 4); 474153770Syongari ptr += segsize; 475153770Syongari segptr += segsize; 476153770Syongari cnt -= segsize; 477153770Syongari } 478153770Syongari} 479153770Syongari 480153770Syongari/* 481153770Syongari * NIC memory read function. 482153770Syongari * Can be used to clear a section of NIC local memory. 483153770Syongari */ 484153770Syongaristatic void 485153770Syongariti_mem_zero(sc, addr, len) 486153770Syongari struct ti_softc *sc; 487153770Syongari u_int32_t addr, len; 488153770Syongari{ 489153770Syongari int segptr, segsize, cnt; 490153770Syongari 491153770Syongari segptr = addr; 492153770Syongari cnt = len; 493153770Syongari 494153770Syongari while (cnt) { 495153770Syongari if (cnt < TI_WINLEN) 496153770Syongari segsize = cnt; 497153770Syongari else 498153770Syongari segsize = TI_WINLEN - (segptr % TI_WINLEN); 499153770Syongari CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 500153770Syongari bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 501153770Syongari TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 502153770Syongari segptr += segsize; 503153770Syongari cnt -= segsize; 504153770Syongari } 505153770Syongari} 506153770Syongari 50798849Skenstatic int 50898849Skenti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 50998849Sken struct ti_softc *sc; 51098849Sken u_int32_t tigon_addr, len; 51198849Sken caddr_t buf; 51298849Sken int useraddr, readdata; 51398849Sken{ 51498849Sken int segptr, segsize, cnt; 51598849Sken caddr_t ptr; 51698849Sken u_int32_t origwin; 51798849Sken u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 51898849Sken int resid, segresid; 51998849Sken int first_pass; 52098849Sken 521153770Syongari TI_LOCK_ASSERT(sc); 522153770Syongari 52398849Sken /* 52498849Sken * At the moment, we don't handle non-aligned cases, we just bail. 52598849Sken * If this proves to be a problem, it will be fixed. 52698849Sken */ 52798849Sken if ((readdata == 0) 52898849Sken && (tigon_addr & 0x3)) { 529162321Sglebius device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 530162321Sglebius "word-aligned\n", __func__, tigon_addr); 531162321Sglebius device_printf(sc->ti_dev, "%s: unaligned writes aren't " 532162321Sglebius "yet supported\n", __func__); 533131654Sbms return (EINVAL); 53498849Sken } 53598849Sken 53698849Sken segptr = tigon_addr & ~0x3; 53798849Sken segresid = tigon_addr - segptr; 53898849Sken 53998849Sken /* 54098849Sken * This is the non-aligned amount left over that we'll need to 54198849Sken * copy. 54298849Sken */ 54398849Sken resid = len & 0x3; 54498849Sken 54598849Sken /* Add in the left over amount at the front of the buffer */ 54698849Sken resid += segresid; 54798849Sken 54898849Sken cnt = len & ~0x3; 54998849Sken /* 55098849Sken * If resid + segresid is >= 4, add multiples of 4 to the count and 55198849Sken * decrease the residual by that much. 55298849Sken */ 55398849Sken cnt += resid & ~0x3; 55498849Sken resid -= resid & ~0x3; 55598849Sken 55698849Sken ptr = buf; 55798849Sken 55898849Sken first_pass = 1; 55998849Sken 56098849Sken /* 56198849Sken * Save the old window base value. 56298849Sken */ 56398849Sken origwin = CSR_READ_4(sc, TI_WINBASE); 56498849Sken 565131654Sbms while (cnt) { 56698849Sken bus_size_t ti_offset; 56798849Sken 56898849Sken if (cnt < TI_WINLEN) 56998849Sken segsize = cnt; 57098849Sken else 57198849Sken segsize = TI_WINLEN - (segptr % TI_WINLEN); 57298849Sken CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 57398849Sken 57498849Sken ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 57598849Sken 57698849Sken if (readdata) { 57798849Sken 57898849Sken bus_space_read_region_4(sc->ti_btag, 57998849Sken sc->ti_bhandle, ti_offset, 58098849Sken (u_int32_t *)tmparray, 58198849Sken segsize >> 2); 58298849Sken if (useraddr) { 58398849Sken /* 58498849Sken * Yeah, this is a little on the kludgy 58598849Sken * side, but at least this code is only 58698849Sken * used for debugging. 58798849Sken */ 58898849Sken ti_bcopy_swap(tmparray, tmparray2, segsize, 58998849Sken TI_SWAP_NTOH); 59098849Sken 591153281Sscottl TI_UNLOCK(sc); 59298849Sken if (first_pass) { 59398849Sken copyout(&tmparray2[segresid], ptr, 59498849Sken segsize - segresid); 59598849Sken first_pass = 0; 59698849Sken } else 59798849Sken copyout(tmparray2, ptr, segsize); 598153281Sscottl TI_LOCK(sc); 59998849Sken } else { 60098849Sken if (first_pass) { 60198849Sken 60298849Sken ti_bcopy_swap(tmparray, tmparray2, 60398849Sken segsize, TI_SWAP_NTOH); 604153281Sscottl TI_UNLOCK(sc); 60598849Sken bcopy(&tmparray2[segresid], ptr, 60698849Sken segsize - segresid); 607153281Sscottl TI_LOCK(sc); 60898849Sken first_pass = 0; 60998849Sken } else 61098849Sken ti_bcopy_swap(tmparray, ptr, segsize, 61198849Sken TI_SWAP_NTOH); 61298849Sken } 61398849Sken 61498849Sken } else { 61598849Sken if (useraddr) { 616153281Sscottl TI_UNLOCK(sc); 61798849Sken copyin(ptr, tmparray2, segsize); 618153281Sscottl TI_LOCK(sc); 61998849Sken ti_bcopy_swap(tmparray2, tmparray, segsize, 62098849Sken TI_SWAP_HTON); 62198849Sken } else 62298849Sken ti_bcopy_swap(ptr, tmparray, segsize, 62398849Sken TI_SWAP_HTON); 62498849Sken 62598849Sken bus_space_write_region_4(sc->ti_btag, 62698849Sken sc->ti_bhandle, ti_offset, 62798849Sken (u_int32_t *)tmparray, 62898849Sken segsize >> 2); 62998849Sken } 63098849Sken segptr += segsize; 63198849Sken ptr += segsize; 63298849Sken cnt -= segsize; 63398849Sken } 63498849Sken 63598849Sken /* 63698849Sken * Handle leftover, non-word-aligned bytes. 63798849Sken */ 63898849Sken if (resid != 0) { 63998849Sken u_int32_t tmpval, tmpval2; 64098849Sken bus_size_t ti_offset; 64198849Sken 64298849Sken /* 64398849Sken * Set the segment pointer. 64498849Sken */ 64598849Sken CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 64698849Sken 64798849Sken ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 64898849Sken 64998849Sken /* 65098849Sken * First, grab whatever is in our source/destination. 65198849Sken * We'll obviously need this for reads, but also for 65298849Sken * writes, since we'll be doing read/modify/write. 65398849Sken */ 65498849Sken bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 65598849Sken ti_offset, &tmpval, 1); 65698849Sken 65798849Sken /* 65898849Sken * Next, translate this from little-endian to big-endian 65998849Sken * (at least on i386 boxes). 66098849Sken */ 66198849Sken tmpval2 = ntohl(tmpval); 66298849Sken 66398849Sken if (readdata) { 66498849Sken /* 66598849Sken * If we're reading, just copy the leftover number 66698849Sken * of bytes from the host byte order buffer to 66798849Sken * the user's buffer. 66898849Sken */ 669153281Sscottl if (useraddr) { 670153281Sscottl TI_UNLOCK(sc); 67198849Sken copyout(&tmpval2, ptr, resid); 672153281Sscottl TI_LOCK(sc); 673153281Sscottl } else 67498849Sken bcopy(&tmpval2, ptr, resid); 67598849Sken } else { 67698849Sken /* 67798849Sken * If we're writing, first copy the bytes to be 67898849Sken * written into the network byte order buffer, 67998849Sken * leaving the rest of the buffer with whatever was 68098849Sken * originally in there. Then, swap the bytes 68198849Sken * around into host order and write them out. 68298849Sken * 68398849Sken * XXX KDM the read side of this has been verified 68498849Sken * to work, but the write side of it has not been 68598849Sken * verified. So user beware. 68698849Sken */ 687153281Sscottl if (useraddr) { 688153281Sscottl TI_UNLOCK(sc); 68998849Sken copyin(ptr, &tmpval2, resid); 690153281Sscottl TI_LOCK(sc); 691153281Sscottl } else 69298849Sken bcopy(ptr, &tmpval2, resid); 69398849Sken 69498849Sken tmpval = htonl(tmpval2); 69598849Sken 69698849Sken bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 69798849Sken ti_offset, &tmpval, 1); 69898849Sken } 69998849Sken } 70098849Sken 70198849Sken CSR_WRITE_4(sc, TI_WINBASE, origwin); 70298849Sken 703131654Sbms return (0); 70498849Sken} 70598849Sken 70698849Skenstatic int 70798849Skenti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 70898849Sken struct ti_softc *sc; 70998849Sken u_int32_t tigon_addr, len; 71098849Sken caddr_t buf; 71198849Sken int useraddr, readdata; 71298849Sken int cpu; 71398849Sken{ 71498849Sken u_int32_t segptr; 71598849Sken int cnt; 71698849Sken u_int32_t tmpval, tmpval2; 71798849Sken caddr_t ptr; 71898849Sken 719153770Syongari TI_LOCK_ASSERT(sc); 720153770Syongari 72198849Sken /* 72298849Sken * At the moment, we don't handle non-aligned cases, we just bail. 72398849Sken * If this proves to be a problem, it will be fixed. 72498849Sken */ 72598849Sken if (tigon_addr & 0x3) { 726162321Sglebius device_printf(sc->ti_dev, "%s: tigon address %#x " 727162321Sglebius "isn't word-aligned\n", __func__, tigon_addr); 728131654Sbms return (EINVAL); 72998849Sken } 73098849Sken 73198849Sken if (len & 0x3) { 732162321Sglebius device_printf(sc->ti_dev, "%s: transfer length %d " 733162321Sglebius "isn't word-aligned\n", __func__, len); 734131654Sbms return (EINVAL); 73598849Sken } 73698849Sken 73798849Sken segptr = tigon_addr; 73898849Sken cnt = len; 73998849Sken ptr = buf; 74098849Sken 74198849Sken while (cnt) { 74298849Sken CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 74398849Sken 74498849Sken if (readdata) { 74598849Sken tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 74698849Sken 74798849Sken tmpval = ntohl(tmpval2); 74898849Sken 74998849Sken /* 75098849Sken * Note: I've used this debugging interface 75198849Sken * extensively with Alteon's 12.3.15 firmware, 75298849Sken * compiled with GCC 2.7.2.1 and binutils 2.9.1. 75398849Sken * 75498849Sken * When you compile the firmware without 75598849Sken * optimization, which is necessary sometimes in 75698849Sken * order to properly step through it, you sometimes 757131652Sbms * read out a bogus value of 0xc0017c instead of 75898849Sken * whatever was supposed to be in that scratchpad 75998849Sken * location. That value is on the stack somewhere, 76098849Sken * but I've never been able to figure out what was 76198849Sken * causing the problem. 76298849Sken * 76398849Sken * The address seems to pop up in random places, 76498849Sken * often not in the same place on two subsequent 76598849Sken * reads. 76698849Sken * 76798849Sken * In any case, the underlying data doesn't seem 76898849Sken * to be affected, just the value read out. 76998849Sken * 77098849Sken * KDM, 3/7/2000 77198849Sken */ 77298849Sken 77398849Sken if (tmpval2 == 0xc0017c) 774162321Sglebius device_printf(sc->ti_dev, "found 0xc0017c at " 775162321Sglebius "%#x (tmpval2)\n", segptr); 77698849Sken 77798849Sken if (tmpval == 0xc0017c) 778162321Sglebius device_printf(sc->ti_dev, "found 0xc0017c at " 779162321Sglebius "%#x (tmpval)\n", segptr); 78098849Sken 78198849Sken if (useraddr) 78298849Sken copyout(&tmpval, ptr, 4); 78398849Sken else 78498849Sken bcopy(&tmpval, ptr, 4); 78598849Sken } else { 78698849Sken if (useraddr) 78798849Sken copyin(ptr, &tmpval2, 4); 78898849Sken else 78998849Sken bcopy(ptr, &tmpval2, 4); 79098849Sken 79198849Sken tmpval = htonl(tmpval2); 79298849Sken 79398849Sken CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 79498849Sken } 79598849Sken 79698849Sken cnt -= 4; 79798849Sken segptr += 4; 79898849Sken ptr += 4; 79998849Sken } 80098849Sken 801131654Sbms return (0); 80298849Sken} 80398849Sken 80498849Skenstatic int 80598849Skenti_bcopy_swap(src, dst, len, swap_type) 80698849Sken const void *src; 80798849Sken void *dst; 80898849Sken size_t len; 80998849Sken ti_swap_type swap_type; 81098849Sken{ 81198849Sken const u_int8_t *tmpsrc; 81298849Sken u_int8_t *tmpdst; 81398849Sken size_t tmplen; 81498849Sken 81598849Sken if (len & 0x3) { 816106627Sjhb printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 81798849Sken len); 818131654Sbms return (-1); 81998849Sken } 82098849Sken 82198849Sken tmpsrc = src; 82298849Sken tmpdst = dst; 82398849Sken tmplen = len; 82498849Sken 82598849Sken while (tmplen) { 82698849Sken if (swap_type == TI_SWAP_NTOH) 82798849Sken *(u_int32_t *)tmpdst = 82898849Sken ntohl(*(const u_int32_t *)tmpsrc); 82998849Sken else 83098849Sken *(u_int32_t *)tmpdst = 83198849Sken htonl(*(const u_int32_t *)tmpsrc); 83298849Sken 83398849Sken tmpsrc += 4; 83498849Sken tmpdst += 4; 83598849Sken tmplen -= 4; 83698849Sken } 83798849Sken 838131654Sbms return (0); 83998849Sken} 84098849Sken 84145386Swpaul/* 84245386Swpaul * Load firmware image into the NIC. Check that the firmware revision 84345386Swpaul * is acceptable and see if we want the firmware for the Tigon 1 or 84445386Swpaul * Tigon 2. 84545386Swpaul */ 846102336Salfredstatic void 847102336Salfredti_loadfw(sc) 84845386Swpaul struct ti_softc *sc; 84945386Swpaul{ 850153770Syongari 851153770Syongari TI_LOCK_ASSERT(sc); 852153770Syongari 853131654Sbms switch (sc->ti_hwrev) { 85445386Swpaul case TI_HWREV_TIGON: 85545386Swpaul if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 85645386Swpaul tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 85745386Swpaul tigonFwReleaseFix != TI_FIRMWARE_FIX) { 858162321Sglebius device_printf(sc->ti_dev, "firmware revision mismatch; " 859150719Sjhb "want %d.%d.%d, got %d.%d.%d\n", 86045386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 86145386Swpaul TI_FIRMWARE_FIX, tigonFwReleaseMajor, 86245386Swpaul tigonFwReleaseMinor, tigonFwReleaseFix); 86345386Swpaul return; 86445386Swpaul } 865153770Syongari ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 866153770Syongari ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 867153770Syongari ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 868153770Syongari tigonFwRodata); 869153770Syongari ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 870153770Syongari ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 87145386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 87245386Swpaul break; 87345386Swpaul case TI_HWREV_TIGON_II: 87445386Swpaul if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 87545386Swpaul tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 87645386Swpaul tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 877162321Sglebius device_printf(sc->ti_dev, "firmware revision mismatch; " 878150719Sjhb "want %d.%d.%d, got %d.%d.%d\n", 87945386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 88045386Swpaul TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 88145386Swpaul tigon2FwReleaseMinor, tigon2FwReleaseFix); 88245386Swpaul return; 88345386Swpaul } 884153770Syongari ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 885153770Syongari tigon2FwText); 886153770Syongari ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 887153770Syongari tigon2FwData); 888153770Syongari ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 889153770Syongari tigon2FwRodata); 890153770Syongari ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 891153770Syongari ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 89245386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 89345386Swpaul break; 89445386Swpaul default: 895162321Sglebius device_printf(sc->ti_dev, 896150719Sjhb "can't load firmware: unknown hardware rev\n"); 89745386Swpaul break; 89845386Swpaul } 89945386Swpaul} 90045386Swpaul 90145386Swpaul/* 90245386Swpaul * Send the NIC a command via the command ring. 90345386Swpaul */ 904102336Salfredstatic void 905102336Salfredti_cmd(sc, cmd) 90645386Swpaul struct ti_softc *sc; 90745386Swpaul struct ti_cmd_desc *cmd; 90845386Swpaul{ 909153982Syongari int index; 91045386Swpaul 91145386Swpaul index = sc->ti_cmd_saved_prodidx; 91245386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 91345386Swpaul TI_INC(index, TI_CMD_RING_CNT); 91445386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 91545386Swpaul sc->ti_cmd_saved_prodidx = index; 91645386Swpaul} 91745386Swpaul 91845386Swpaul/* 91945386Swpaul * Send the NIC an extended command. The 'len' parameter specifies the 92045386Swpaul * number of command slots to include after the initial command. 92145386Swpaul */ 922102336Salfredstatic void 923102336Salfredti_cmd_ext(sc, cmd, arg, len) 92445386Swpaul struct ti_softc *sc; 92545386Swpaul struct ti_cmd_desc *cmd; 92645386Swpaul caddr_t arg; 92745386Swpaul int len; 92845386Swpaul{ 929153982Syongari int index; 930153770Syongari int i; 93145386Swpaul 93245386Swpaul index = sc->ti_cmd_saved_prodidx; 93345386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 93445386Swpaul TI_INC(index, TI_CMD_RING_CNT); 93545386Swpaul for (i = 0; i < len; i++) { 93645386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 93745386Swpaul *(u_int32_t *)(&arg[i * 4])); 93845386Swpaul TI_INC(index, TI_CMD_RING_CNT); 93945386Swpaul } 94045386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 94145386Swpaul sc->ti_cmd_saved_prodidx = index; 94245386Swpaul} 94345386Swpaul 94445386Swpaul/* 94545386Swpaul * Handle events that have triggered interrupts. 94645386Swpaul */ 947102336Salfredstatic void 948102336Salfredti_handle_events(sc) 94945386Swpaul struct ti_softc *sc; 95045386Swpaul{ 95145386Swpaul struct ti_event_desc *e; 95245386Swpaul 95345386Swpaul if (sc->ti_rdata->ti_event_ring == NULL) 95445386Swpaul return; 95545386Swpaul 95645386Swpaul while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 95745386Swpaul e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 958153770Syongari switch (TI_EVENT_EVENT(e)) { 95945386Swpaul case TI_EV_LINKSTAT_CHANGED: 960153770Syongari sc->ti_linkstat = TI_EVENT_CODE(e); 961153770Syongari if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 962162321Sglebius device_printf(sc->ti_dev, "10/100 link up\n"); 963153770Syongari else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 964162321Sglebius device_printf(sc->ti_dev, "gigabit link up\n"); 965153770Syongari else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 966162321Sglebius device_printf(sc->ti_dev, "link down\n"); 96745386Swpaul break; 96845386Swpaul case TI_EV_ERROR: 969153770Syongari if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 970162321Sglebius device_printf(sc->ti_dev, "invalid command\n"); 971153770Syongari else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 972162321Sglebius device_printf(sc->ti_dev, "unknown command\n"); 973153770Syongari else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 974162321Sglebius device_printf(sc->ti_dev, "bad config data\n"); 97545386Swpaul break; 97645386Swpaul case TI_EV_FIRMWARE_UP: 97745386Swpaul ti_init2(sc); 97845386Swpaul break; 97945386Swpaul case TI_EV_STATS_UPDATED: 98045386Swpaul ti_stats_update(sc); 98145386Swpaul break; 98245386Swpaul case TI_EV_RESET_JUMBO_RING: 98345386Swpaul case TI_EV_MCAST_UPDATED: 98445386Swpaul /* Who cares. */ 98545386Swpaul break; 98645386Swpaul default: 987162321Sglebius device_printf(sc->ti_dev, "unknown event: %d\n", 988153770Syongari TI_EVENT_EVENT(e)); 98945386Swpaul break; 99045386Swpaul } 99145386Swpaul /* Advance the consumer index. */ 99245386Swpaul TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 99345386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 99445386Swpaul } 99545386Swpaul} 99645386Swpaul 997153396Sscottlstatic int 998153396Sscottlti_alloc_dmamaps(struct ti_softc *sc) 999153396Sscottl{ 1000153396Sscottl int i; 1001153396Sscottl 1002153396Sscottl for (i = 0; i < TI_TX_RING_CNT; i++) { 1003153982Syongari sc->ti_cdata.ti_txdesc[i].tx_m = NULL; 1004153982Syongari sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1005153396Sscottl if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0, 1006153982Syongari &sc->ti_cdata.ti_txdesc[i].tx_dmamap)) 1007153396Sscottl return (ENOBUFS); 1008153396Sscottl } 1009153396Sscottl for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1010153396Sscottl if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1011153396Sscottl &sc->ti_cdata.ti_rx_std_maps[i])) 1012153396Sscottl return (ENOBUFS); 1013153396Sscottl } 1014153396Sscottl 1015153396Sscottl for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1016153396Sscottl if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 1017153396Sscottl &sc->ti_cdata.ti_rx_jumbo_maps[i])) 1018153396Sscottl return (ENOBUFS); 1019153396Sscottl } 1020153396Sscottl for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1021153396Sscottl if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1022153396Sscottl &sc->ti_cdata.ti_rx_mini_maps[i])) 1023153396Sscottl return (ENOBUFS); 1024153396Sscottl } 1025153396Sscottl 1026153396Sscottl return (0); 1027153396Sscottl} 1028153396Sscottl 1029153396Sscottlstatic void 1030153396Sscottlti_free_dmamaps(struct ti_softc *sc) 1031153396Sscottl{ 1032153396Sscottl int i; 1033153396Sscottl 1034153770Syongari if (sc->ti_mbuftx_dmat) 1035153770Syongari for (i = 0; i < TI_TX_RING_CNT; i++) 1036153982Syongari if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1037153770Syongari bus_dmamap_destroy(sc->ti_mbuftx_dmat, 1038153982Syongari sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1039153982Syongari sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1040153770Syongari } 1041153396Sscottl 1042153770Syongari if (sc->ti_mbufrx_dmat) 1043153770Syongari for (i = 0; i < TI_STD_RX_RING_CNT; i++) 1044153770Syongari if (sc->ti_cdata.ti_rx_std_maps[i]) { 1045153770Syongari bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1046153770Syongari sc->ti_cdata.ti_rx_std_maps[i]); 1047153770Syongari sc->ti_cdata.ti_rx_std_maps[i] = 0; 1048153770Syongari } 1049153396Sscottl 1050153770Syongari if (sc->ti_jumbo_dmat) 1051153770Syongari for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) 1052153770Syongari if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1053153770Syongari bus_dmamap_destroy(sc->ti_jumbo_dmat, 1054153770Syongari sc->ti_cdata.ti_rx_jumbo_maps[i]); 1055153770Syongari sc->ti_cdata.ti_rx_jumbo_maps[i] = 0; 1056153770Syongari } 1057153770Syongari if (sc->ti_mbufrx_dmat) 1058153770Syongari for (i = 0; i < TI_MINI_RX_RING_CNT; i++) 1059153770Syongari if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1060153770Syongari bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1061153770Syongari sc->ti_cdata.ti_rx_mini_maps[i]); 1062153770Syongari sc->ti_cdata.ti_rx_mini_maps[i] = 0; 1063153770Syongari } 1064153396Sscottl} 1065153396Sscottl 106698849Sken#ifdef TI_PRIVATE_JUMBOS 106798849Sken 106845386Swpaul/* 106945386Swpaul * Memory management for the jumbo receive ring is a pain in the 107045386Swpaul * butt. We need to allocate at least 9018 bytes of space per frame, 107145386Swpaul * _and_ it has to be contiguous (unless you use the extended 107245386Swpaul * jumbo descriptor format). Using malloc() all the time won't 107345386Swpaul * work: malloc() allocates memory in powers of two, which means we 107445386Swpaul * would end up wasting a considerable amount of space by allocating 107545386Swpaul * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 107645386Swpaul * to do our own memory management. 107745386Swpaul * 107845386Swpaul * The driver needs to allocate a contiguous chunk of memory at boot 107945386Swpaul * time. We then chop this up ourselves into 9K pieces and use them 108045386Swpaul * as external mbuf storage. 108145386Swpaul * 108245386Swpaul * One issue here is how much memory to allocate. The jumbo ring has 108345386Swpaul * 256 slots in it, but at 9K per slot than can consume over 2MB of 108445386Swpaul * RAM. This is a bit much, especially considering we also need 108545386Swpaul * RAM for the standard ring and mini ring (on the Tigon 2). To 108645386Swpaul * save space, we only actually allocate enough memory for 64 slots 108745386Swpaul * by default, which works out to between 500 and 600K. This can 108845386Swpaul * be tuned by changing a #define in if_tireg.h. 108945386Swpaul */ 109045386Swpaul 1091102336Salfredstatic int 1092102336Salfredti_alloc_jumbo_mem(sc) 109345386Swpaul struct ti_softc *sc; 109445386Swpaul{ 109545386Swpaul caddr_t ptr; 1096153770Syongari int i; 109745386Swpaul struct ti_jpool_entry *entry; 109845386Swpaul 1099153396Sscottl /* 1100153396Sscottl * Grab a big chunk o' storage. Since we are chopping this pool up 1101153396Sscottl * into ~9k chunks, there doesn't appear to be a need to use page 1102153396Sscottl * alignment. 1103153396Sscottl */ 1104153288Sscottl if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1105153396Sscottl 1, 0, /* algnmnt, boundary */ 1106153396Sscottl BUS_SPACE_MAXADDR, /* lowaddr */ 1107153288Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 1108153288Sscottl NULL, NULL, /* filter, filterarg */ 1109153288Sscottl TI_JMEM, /* maxsize */ 1110153288Sscottl 1, /* nsegments */ 1111153288Sscottl TI_JMEM, /* maxsegsize */ 1112153288Sscottl 0, /* flags */ 1113153288Sscottl NULL, NULL, /* lockfunc, lockarg */ 1114153288Sscottl &sc->ti_jumbo_dmat) != 0) { 1115153396Sscottl device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1116153288Sscottl return (ENOBUFS); 1117153288Sscottl } 111845386Swpaul 1119153288Sscottl if (bus_dmamem_alloc(sc->ti_jumbo_dmat, 1120153288Sscottl (void**)&sc->ti_cdata.ti_jumbo_buf, 1121219547Smarius BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 1122219547Smarius &sc->ti_jumbo_dmamap) != 0) { 1123153396Sscottl device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n"); 1124131654Sbms return (ENOBUFS); 112545386Swpaul } 112645386Swpaul 112745386Swpaul SLIST_INIT(&sc->ti_jfree_listhead); 112845386Swpaul SLIST_INIT(&sc->ti_jinuse_listhead); 112945386Swpaul 113045386Swpaul /* 113145386Swpaul * Now divide it up into 9K pieces and save the addresses 113267405Sbmilekic * in an array. 113345386Swpaul */ 113445386Swpaul ptr = sc->ti_cdata.ti_jumbo_buf; 113545386Swpaul for (i = 0; i < TI_JSLOTS; i++) { 113667405Sbmilekic sc->ti_cdata.ti_jslots[i] = ptr; 113767405Sbmilekic ptr += TI_JLEN; 1138131652Sbms entry = malloc(sizeof(struct ti_jpool_entry), 113945386Swpaul M_DEVBUF, M_NOWAIT); 114045386Swpaul if (entry == NULL) { 1141153396Sscottl device_printf(sc->ti_dev, "no memory for jumbo " 1142150719Sjhb "buffer queue!\n"); 1143131654Sbms return (ENOBUFS); 114445386Swpaul } 114545386Swpaul entry->slot = i; 114645386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 114745386Swpaul } 114845386Swpaul 1149131654Sbms return (0); 115045386Swpaul} 115145386Swpaul 115245386Swpaul/* 115345386Swpaul * Allocate a jumbo buffer. 115445386Swpaul */ 115545386Swpaulstatic void *ti_jalloc(sc) 115645386Swpaul struct ti_softc *sc; 115745386Swpaul{ 1158131655Sbms struct ti_jpool_entry *entry; 1159131652Sbms 116045386Swpaul entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1161131652Sbms 116245386Swpaul if (entry == NULL) { 1163162321Sglebius device_printf(sc->ti_dev, "no free jumbo buffers\n"); 1164131654Sbms return (NULL); 116545386Swpaul } 116645386Swpaul 116745386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 116845386Swpaul SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1169131654Sbms return (sc->ti_cdata.ti_jslots[entry->slot]); 117045386Swpaul} 117145386Swpaul 117245386Swpaul/* 117345386Swpaul * Release a jumbo buffer. 117445386Swpaul */ 1175102336Salfredstatic void 1176102336Salfredti_jfree(buf, args) 117799058Salfred void *buf; 117864837Sdwmalone void *args; 117945386Swpaul{ 118045386Swpaul struct ti_softc *sc; 1181131655Sbms int i; 1182131655Sbms struct ti_jpool_entry *entry; 118345386Swpaul 118445386Swpaul /* Extract the softc struct pointer. */ 118567405Sbmilekic sc = (struct ti_softc *)args; 118645386Swpaul 118745386Swpaul if (sc == NULL) 118867405Sbmilekic panic("ti_jfree: didn't get softc pointer!"); 118945386Swpaul 119045386Swpaul /* calculate the slot this buffer belongs to */ 119167405Sbmilekic i = ((vm_offset_t)buf 119245386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 119345386Swpaul 119445386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 119545386Swpaul panic("ti_jfree: asked to free buffer that we don't manage!"); 119645386Swpaul 119764837Sdwmalone entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 119864837Sdwmalone if (entry == NULL) 119964837Sdwmalone panic("ti_jfree: buffer not in use!"); 120064837Sdwmalone entry->slot = i; 120164837Sdwmalone SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 120264837Sdwmalone SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 120345386Swpaul} 120445386Swpaul 1205153396Sscottl#else 1206153396Sscottl 1207153396Sscottlstatic int 1208153396Sscottlti_alloc_jumbo_mem(sc) 1209153396Sscottl struct ti_softc *sc; 1210153396Sscottl{ 1211153396Sscottl 1212153396Sscottl /* 1213153396Sscottl * The VM system will take care of providing aligned pages. Alignment 1214153396Sscottl * is set to 1 here so that busdma resources won't be wasted. 1215153396Sscottl */ 1216153396Sscottl if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1217153396Sscottl 1, 0, /* algnmnt, boundary */ 1218153396Sscottl BUS_SPACE_MAXADDR, /* lowaddr */ 1219153396Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 1220153396Sscottl NULL, NULL, /* filter, filterarg */ 1221153396Sscottl PAGE_SIZE * 4 /*XXX*/, /* maxsize */ 1222153396Sscottl 4, /* nsegments */ 1223153396Sscottl PAGE_SIZE, /* maxsegsize */ 1224153396Sscottl 0, /* flags */ 1225153396Sscottl NULL, NULL, /* lockfunc, lockarg */ 1226153396Sscottl &sc->ti_jumbo_dmat) != 0) { 1227153396Sscottl device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1228153396Sscottl return (ENOBUFS); 1229153396Sscottl } 1230153396Sscottl 1231153396Sscottl return (0); 1232153396Sscottl} 1233153396Sscottl 123498849Sken#endif /* TI_PRIVATE_JUMBOS */ 123545386Swpaul 123645386Swpaul/* 123745386Swpaul * Intialize a standard receive ring descriptor. 123845386Swpaul */ 1239102336Salfredstatic int 1240102336Salfredti_newbuf_std(sc, i, m) 124145386Swpaul struct ti_softc *sc; 124245386Swpaul int i; 124345386Swpaul struct mbuf *m; 124445386Swpaul{ 1245153396Sscottl bus_dmamap_t map; 1246153396Sscottl bus_dma_segment_t segs; 124745386Swpaul struct mbuf *m_new = NULL; 124845386Swpaul struct ti_rx_desc *r; 1249153396Sscottl int nsegs; 125045386Swpaul 1251153396Sscottl nsegs = 0; 125249036Swpaul if (m == NULL) { 1253111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 125487846Sluigi if (m_new == NULL) 1255131654Sbms return (ENOBUFS); 125645386Swpaul 1257111119Simp MCLGET(m_new, M_DONTWAIT); 125845386Swpaul if (!(m_new->m_flags & M_EXT)) { 125945386Swpaul m_freem(m_new); 1260131654Sbms return (ENOBUFS); 126145386Swpaul } 126249036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 126349036Swpaul } else { 126449036Swpaul m_new = m; 126549036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 126649036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 126745386Swpaul } 126845386Swpaul 126948597Swpaul m_adj(m_new, ETHER_ALIGN); 127045386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = m_new; 127145386Swpaul r = &sc->ti_rdata->ti_rx_std_ring[i]; 1272153396Sscottl map = sc->ti_cdata.ti_rx_std_maps[i]; 1273153396Sscottl if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1274153396Sscottl &nsegs, 0)) 1275153396Sscottl return (ENOBUFS); 1276153396Sscottl if (nsegs != 1) 1277153396Sscottl return (ENOBUFS); 1278153396Sscottl ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1279153396Sscottl r->ti_len = segs.ds_len; 128045386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 128145386Swpaul r->ti_flags = 0; 1282147256Sbrooks if (sc->ti_ifp->if_hwassist) 128358698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 128445386Swpaul r->ti_idx = i; 128545386Swpaul 1286153396Sscottl bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1287131654Sbms return (0); 128845386Swpaul} 128945386Swpaul 129045386Swpaul/* 129145386Swpaul * Intialize a mini receive ring descriptor. This only applies to 129245386Swpaul * the Tigon 2. 129345386Swpaul */ 1294102336Salfredstatic int 1295102336Salfredti_newbuf_mini(sc, i, m) 129645386Swpaul struct ti_softc *sc; 129745386Swpaul int i; 129845386Swpaul struct mbuf *m; 129945386Swpaul{ 1300153396Sscottl bus_dma_segment_t segs; 1301153396Sscottl bus_dmamap_t map; 130245386Swpaul struct mbuf *m_new = NULL; 130345386Swpaul struct ti_rx_desc *r; 1304153396Sscottl int nsegs; 130545386Swpaul 1306153396Sscottl nsegs = 0; 130749036Swpaul if (m == NULL) { 1308111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 130945386Swpaul if (m_new == NULL) { 1310131654Sbms return (ENOBUFS); 131145386Swpaul } 131249036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 131349036Swpaul } else { 131449036Swpaul m_new = m; 131549036Swpaul m_new->m_data = m_new->m_pktdat; 131649036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 131745386Swpaul } 131849036Swpaul 131948597Swpaul m_adj(m_new, ETHER_ALIGN); 132045386Swpaul r = &sc->ti_rdata->ti_rx_mini_ring[i]; 132145386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1322153396Sscottl map = sc->ti_cdata.ti_rx_mini_maps[i]; 1323153396Sscottl if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1324153396Sscottl &nsegs, 0)) 1325153396Sscottl return (ENOBUFS); 1326153396Sscottl if (nsegs != 1) 1327153396Sscottl return (ENOBUFS); 1328153396Sscottl ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1329153396Sscottl r->ti_len = segs.ds_len; 133045386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 133145386Swpaul r->ti_flags = TI_BDFLAG_MINI_RING; 1332147256Sbrooks if (sc->ti_ifp->if_hwassist) 133358698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 133445386Swpaul r->ti_idx = i; 133545386Swpaul 1336153396Sscottl bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1337131654Sbms return (0); 133845386Swpaul} 133945386Swpaul 134098849Sken#ifdef TI_PRIVATE_JUMBOS 134198849Sken 134245386Swpaul/* 134345386Swpaul * Initialize a jumbo receive ring descriptor. This allocates 134445386Swpaul * a jumbo buffer from the pool managed internally by the driver. 134545386Swpaul */ 1346102336Salfredstatic int 1347102336Salfredti_newbuf_jumbo(sc, i, m) 134845386Swpaul struct ti_softc *sc; 134945386Swpaul int i; 135045386Swpaul struct mbuf *m; 135145386Swpaul{ 1352153396Sscottl bus_dmamap_t map; 135345386Swpaul struct mbuf *m_new = NULL; 135445386Swpaul struct ti_rx_desc *r; 1355153396Sscottl int nsegs; 1356153396Sscottl bus_dma_segment_t segs; 135745386Swpaul 135849036Swpaul if (m == NULL) { 135945386Swpaul caddr_t *buf = NULL; 136045386Swpaul 136145386Swpaul /* Allocate the mbuf. */ 1362111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 136345386Swpaul if (m_new == NULL) { 1364131654Sbms return (ENOBUFS); 136545386Swpaul } 136645386Swpaul 136745386Swpaul /* Allocate the jumbo buffer */ 136845386Swpaul buf = ti_jalloc(sc); 136945386Swpaul if (buf == NULL) { 137045386Swpaul m_freem(m_new); 1371162321Sglebius device_printf(sc->ti_dev, "jumbo allocation failed " 1372150719Sjhb "-- packet dropped!\n"); 1373131654Sbms return (ENOBUFS); 137445386Swpaul } 137545386Swpaul 137645386Swpaul /* Attach the buffer to the mbuf. */ 137764837Sdwmalone m_new->m_data = (void *) buf; 137864837Sdwmalone m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 137967405Sbmilekic MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 138068621Sbmilekic (struct ti_softc *)sc, 0, EXT_NET_DRV); 138149036Swpaul } else { 138249036Swpaul m_new = m; 138349036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 138449036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 138545386Swpaul } 138645386Swpaul 138749780Swpaul m_adj(m_new, ETHER_ALIGN); 138845386Swpaul /* Set up the descriptor. */ 138945386Swpaul r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 139045386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1391153396Sscottl map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1392153396Sscottl if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs, 1393153396Sscottl &nsegs, 0)) 1394153396Sscottl return (ENOBUFS); 1395153396Sscottl if (nsegs != 1) 1396153396Sscottl return (ENOBUFS); 1397153396Sscottl ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1398153396Sscottl r->ti_len = segs.ds_len; 139945386Swpaul r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 140045386Swpaul r->ti_flags = TI_BDFLAG_JUMBO_RING; 1401147256Sbrooks if (sc->ti_ifp->if_hwassist) 140258698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 140345386Swpaul r->ti_idx = i; 140445386Swpaul 1405153396Sscottl bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1406131654Sbms return (0); 140745386Swpaul} 140845386Swpaul 140998849Sken#else 141098849Sken 141198849Sken#if (PAGE_SIZE == 4096) 141298849Sken#define NPAYLOAD 2 141398849Sken#else 141498849Sken#define NPAYLOAD 1 1415131652Sbms#endif 141698849Sken 141798849Sken#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 141898849Sken#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 141998849Sken#define NFS_HDR_LEN (UDP_HDR_LEN) 1420104401Salfredstatic int HDR_LEN = TCP_HDR_LEN; 142198849Sken 142298849Sken 1423131655Sbms/* 1424131655Sbms * Initialize a jumbo receive ring descriptor. This allocates 1425131655Sbms * a jumbo buffer from the pool managed internally by the driver. 1426131655Sbms */ 142798849Skenstatic int 142898849Skenti_newbuf_jumbo(sc, idx, m_old) 1429131655Sbms struct ti_softc *sc; 1430131655Sbms int idx; 1431131655Sbms struct mbuf *m_old; 143298849Sken{ 1433153396Sscottl bus_dmamap_t map; 143498849Sken struct mbuf *cur, *m_new = NULL; 143598849Sken struct mbuf *m[3] = {NULL, NULL, NULL}; 143698849Sken struct ti_rx_desc_ext *r; 143798849Sken vm_page_t frame; 1438138424Salc static int color; 143998849Sken /* 1 extra buf to make nobufs easy*/ 1440138424Salc struct sf_buf *sf[3] = {NULL, NULL, NULL}; 144198849Sken int i; 1442153396Sscottl bus_dma_segment_t segs[4]; 1443153396Sscottl int nsegs; 144498849Sken 144598849Sken if (m_old != NULL) { 144698849Sken m_new = m_old; 144798849Sken cur = m_old->m_next; 144898849Sken for (i = 0; i <= NPAYLOAD; i++){ 144998849Sken m[i] = cur; 145098849Sken cur = cur->m_next; 145198849Sken } 145298849Sken } else { 145398849Sken /* Allocate the mbufs. */ 1454111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 145598849Sken if (m_new == NULL) { 1456162321Sglebius device_printf(sc->ti_dev, "mbuf allocation failed " 1457150719Sjhb "-- packet dropped!\n"); 145898849Sken goto nobufs; 145998849Sken } 1460111119Simp MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 146198849Sken if (m[NPAYLOAD] == NULL) { 1462162321Sglebius device_printf(sc->ti_dev, "cluster mbuf allocation " 1463162321Sglebius "failed -- packet dropped!\n"); 146498849Sken goto nobufs; 146598849Sken } 1466111119Simp MCLGET(m[NPAYLOAD], M_DONTWAIT); 146798849Sken if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1468162321Sglebius device_printf(sc->ti_dev, "mbuf allocation failed " 1469150719Sjhb "-- packet dropped!\n"); 147098849Sken goto nobufs; 147198849Sken } 147298849Sken m[NPAYLOAD]->m_len = MCLBYTES; 147398849Sken 147498849Sken for (i = 0; i < NPAYLOAD; i++){ 1475111119Simp MGET(m[i], M_DONTWAIT, MT_DATA); 147698849Sken if (m[i] == NULL) { 1477162321Sglebius device_printf(sc->ti_dev, "mbuf allocation " 1478162321Sglebius "failed -- packet dropped!\n"); 147998849Sken goto nobufs; 148098849Sken } 1481138424Salc frame = vm_page_alloc(NULL, color++, 1482138424Salc VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1483138424Salc VM_ALLOC_WIRED); 1484138424Salc if (frame == NULL) { 1485162321Sglebius device_printf(sc->ti_dev, "buffer allocation " 1486150719Sjhb "failed -- packet dropped!\n"); 148798849Sken printf(" index %d page %d\n", idx, i); 1488131655Sbms goto nobufs; 148998849Sken } 1490138424Salc sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1491138424Salc if (sf[i] == NULL) { 1492138424Salc vm_page_unwire(frame, 0); 1493138424Salc vm_page_free(frame); 1494162321Sglebius device_printf(sc->ti_dev, "buffer allocation " 1495150719Sjhb "failed -- packet dropped!\n"); 1496138424Salc printf(" index %d page %d\n", idx, i); 1497138424Salc goto nobufs; 1498138424Salc } 149998849Sken } 150098849Sken for (i = 0; i < NPAYLOAD; i++){ 1501131655Sbms /* Attach the buffer to the mbuf. */ 1502138424Salc m[i]->m_data = (void *)sf_buf_kva(sf[i]); 150398849Sken m[i]->m_len = PAGE_SIZE; 1504138424Salc MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1505175872Sphk sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i], 1506175872Sphk 0, EXT_DISPOSABLE); 150798849Sken m[i]->m_next = m[i+1]; 150898849Sken } 150998849Sken /* link the buffers to the header */ 151098849Sken m_new->m_next = m[0]; 151198849Sken m_new->m_data += ETHER_ALIGN; 151298849Sken if (sc->ti_hdrsplit) 151398849Sken m_new->m_len = MHLEN - ETHER_ALIGN; 151498849Sken else 1515131655Sbms m_new->m_len = HDR_LEN; 151698849Sken m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 151798849Sken } 151898849Sken 151998849Sken /* Set up the descriptor. */ 152098849Sken r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 152198849Sken sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1522153396Sscottl map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1523153396Sscottl if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs, 1524153396Sscottl &nsegs, 0)) 1525153396Sscottl return (ENOBUFS); 1526153396Sscottl if ((nsegs < 1) || (nsegs > 4)) 1527153396Sscottl return (ENOBUFS); 1528153396Sscottl ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 152998849Sken r->ti_len0 = m_new->m_len; 153098849Sken 1531153396Sscottl ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 153298849Sken r->ti_len1 = PAGE_SIZE; 153398849Sken 1534153396Sscottl ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 153598849Sken r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 153698849Sken 153798849Sken if (PAGE_SIZE == 4096) { 1538153396Sscottl ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 153998849Sken r->ti_len3 = MCLBYTES; 154098849Sken } else { 154198849Sken r->ti_len3 = 0; 154298849Sken } 1543131655Sbms r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 154498849Sken 1545131655Sbms r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 154698849Sken 1547147256Sbrooks if (sc->ti_ifp->if_hwassist) 154898849Sken r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 154998849Sken 1550131655Sbms r->ti_idx = idx; 155198849Sken 1552153396Sscottl bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1553131655Sbms return (0); 155498849Sken 1555131655Sbmsnobufs: 155698849Sken 155798849Sken /* 155898849Sken * Warning! : 155998849Sken * This can only be called before the mbufs are strung together. 1560131652Sbms * If the mbufs are strung together, m_freem() will free the chain, 156198849Sken * so that the later mbufs will be freed multiple times. 156298849Sken */ 1563131655Sbms if (m_new) 1564131655Sbms m_freem(m_new); 156598849Sken 1566131655Sbms for (i = 0; i < 3; i++) { 1567131655Sbms if (m[i]) 1568131655Sbms m_freem(m[i]); 1569138424Salc if (sf[i]) 1570138424Salc sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1571131655Sbms } 1572131655Sbms return (ENOBUFS); 157398849Sken} 157498849Sken#endif 157598849Sken 157698849Sken 157798849Sken 157845386Swpaul/* 157945386Swpaul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 158045386Swpaul * that's 1MB or memory, which is a lot. For now, we fill only the first 158145386Swpaul * 256 ring entries and hope that our CPU is fast enough to keep up with 158245386Swpaul * the NIC. 158345386Swpaul */ 1584102336Salfredstatic int 1585102336Salfredti_init_rx_ring_std(sc) 158645386Swpaul struct ti_softc *sc; 158745386Swpaul{ 1588153770Syongari int i; 158945386Swpaul struct ti_cmd_desc cmd; 159045386Swpaul 159145386Swpaul for (i = 0; i < TI_SSLOTS; i++) { 159245386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1593131654Sbms return (ENOBUFS); 159445386Swpaul }; 159545386Swpaul 159645386Swpaul TI_UPDATE_STDPROD(sc, i - 1); 159748597Swpaul sc->ti_std = i - 1; 159845386Swpaul 1599131654Sbms return (0); 160045386Swpaul} 160145386Swpaul 1602102336Salfredstatic void 1603102336Salfredti_free_rx_ring_std(sc) 160445386Swpaul struct ti_softc *sc; 160545386Swpaul{ 1606153770Syongari bus_dmamap_t map; 1607153770Syongari int i; 160845386Swpaul 160945386Swpaul for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 161045386Swpaul if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1611153770Syongari map = sc->ti_cdata.ti_rx_std_maps[i]; 1612153770Syongari bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1613153770Syongari BUS_DMASYNC_POSTREAD); 1614153770Syongari bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 161545386Swpaul m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 161645386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = NULL; 161745386Swpaul } 161845386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 161945386Swpaul sizeof(struct ti_rx_desc)); 162045386Swpaul } 162145386Swpaul} 162245386Swpaul 1623102336Salfredstatic int 1624102336Salfredti_init_rx_ring_jumbo(sc) 162545386Swpaul struct ti_softc *sc; 162645386Swpaul{ 1627153770Syongari int i; 162845386Swpaul struct ti_cmd_desc cmd; 162945386Swpaul 163063699Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 163145386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1632131654Sbms return (ENOBUFS); 163345386Swpaul }; 163445386Swpaul 163545386Swpaul TI_UPDATE_JUMBOPROD(sc, i - 1); 163648597Swpaul sc->ti_jumbo = i - 1; 163745386Swpaul 1638131654Sbms return (0); 163945386Swpaul} 164045386Swpaul 1641102336Salfredstatic void 1642102336Salfredti_free_rx_ring_jumbo(sc) 164345386Swpaul struct ti_softc *sc; 164445386Swpaul{ 1645153770Syongari bus_dmamap_t map; 1646153770Syongari int i; 164745386Swpaul 164845386Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 164945386Swpaul if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1650153770Syongari map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1651153770Syongari bus_dmamap_sync(sc->ti_jumbo_dmat, map, 1652153770Syongari BUS_DMASYNC_POSTREAD); 1653153770Syongari bus_dmamap_unload(sc->ti_jumbo_dmat, map); 165445386Swpaul m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 165545386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 165645386Swpaul } 165745386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 165845386Swpaul sizeof(struct ti_rx_desc)); 165945386Swpaul } 166045386Swpaul} 166145386Swpaul 1662102336Salfredstatic int 1663102336Salfredti_init_rx_ring_mini(sc) 166445386Swpaul struct ti_softc *sc; 166545386Swpaul{ 1666153770Syongari int i; 166745386Swpaul 166845386Swpaul for (i = 0; i < TI_MSLOTS; i++) { 166945386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1670131654Sbms return (ENOBUFS); 167145386Swpaul }; 167245386Swpaul 167345386Swpaul TI_UPDATE_MINIPROD(sc, i - 1); 167448597Swpaul sc->ti_mini = i - 1; 167545386Swpaul 1676131654Sbms return (0); 167745386Swpaul} 167845386Swpaul 1679102336Salfredstatic void 1680102336Salfredti_free_rx_ring_mini(sc) 168145386Swpaul struct ti_softc *sc; 168245386Swpaul{ 1683153770Syongari bus_dmamap_t map; 1684153770Syongari int i; 168545386Swpaul 168645386Swpaul for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 168745386Swpaul if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1688153770Syongari map = sc->ti_cdata.ti_rx_mini_maps[i]; 1689153770Syongari bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1690153770Syongari BUS_DMASYNC_POSTREAD); 1691153770Syongari bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 169245386Swpaul m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 169345386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 169445386Swpaul } 169545386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 169645386Swpaul sizeof(struct ti_rx_desc)); 169745386Swpaul } 169845386Swpaul} 169945386Swpaul 1700102336Salfredstatic void 1701102336Salfredti_free_tx_ring(sc) 170245386Swpaul struct ti_softc *sc; 170345386Swpaul{ 1704153982Syongari struct ti_txdesc *txd; 1705153770Syongari int i; 170645386Swpaul 170745386Swpaul if (sc->ti_rdata->ti_tx_ring == NULL) 170845386Swpaul return; 170945386Swpaul 171045386Swpaul for (i = 0; i < TI_TX_RING_CNT; i++) { 1711153982Syongari txd = &sc->ti_cdata.ti_txdesc[i]; 1712153982Syongari if (txd->tx_m != NULL) { 1713153982Syongari bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 1714153770Syongari BUS_DMASYNC_POSTWRITE); 1715153982Syongari bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 1716153982Syongari m_freem(txd->tx_m); 1717153982Syongari txd->tx_m = NULL; 171845386Swpaul } 171945386Swpaul bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 172045386Swpaul sizeof(struct ti_tx_desc)); 172145386Swpaul } 172245386Swpaul} 172345386Swpaul 1724102336Salfredstatic int 1725102336Salfredti_init_tx_ring(sc) 172645386Swpaul struct ti_softc *sc; 172745386Swpaul{ 1728153982Syongari struct ti_txdesc *txd; 1729153982Syongari int i; 1730153982Syongari 1731153982Syongari STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1732153982Syongari STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1733153982Syongari for (i = 0; i < TI_TX_RING_CNT; i++) { 1734153982Syongari txd = &sc->ti_cdata.ti_txdesc[i]; 1735153982Syongari STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1736153982Syongari } 173748011Swpaul sc->ti_txcnt = 0; 173845386Swpaul sc->ti_tx_saved_considx = 0; 1739153778Sscottl sc->ti_tx_saved_prodidx = 0; 174045386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1741131654Sbms return (0); 174245386Swpaul} 174345386Swpaul 174445386Swpaul/* 174545386Swpaul * The Tigon 2 firmware has a new way to add/delete multicast addresses, 174645386Swpaul * but we have to support the old way too so that Tigon 1 cards will 174745386Swpaul * work. 174845386Swpaul */ 1749105219Sphkstatic void 1750102336Salfredti_add_mcast(sc, addr) 175145386Swpaul struct ti_softc *sc; 175245386Swpaul struct ether_addr *addr; 175345386Swpaul{ 175445386Swpaul struct ti_cmd_desc cmd; 175545386Swpaul u_int16_t *m; 175645386Swpaul u_int32_t ext[2] = {0, 0}; 175745386Swpaul 175845386Swpaul m = (u_int16_t *)&addr->octet[0]; 175945386Swpaul 1760131654Sbms switch (sc->ti_hwrev) { 176145386Swpaul case TI_HWREV_TIGON: 176245386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 176345386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 176445386Swpaul TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 176545386Swpaul break; 176645386Swpaul case TI_HWREV_TIGON_II: 176745386Swpaul ext[0] = htons(m[0]); 176845386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 176945386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 177045386Swpaul break; 177145386Swpaul default: 1772162321Sglebius device_printf(sc->ti_dev, "unknown hwrev\n"); 177345386Swpaul break; 177445386Swpaul } 177545386Swpaul} 177645386Swpaul 1777105219Sphkstatic void 1778102336Salfredti_del_mcast(sc, addr) 177945386Swpaul struct ti_softc *sc; 178045386Swpaul struct ether_addr *addr; 178145386Swpaul{ 178245386Swpaul struct ti_cmd_desc cmd; 178345386Swpaul u_int16_t *m; 178445386Swpaul u_int32_t ext[2] = {0, 0}; 178545386Swpaul 178645386Swpaul m = (u_int16_t *)&addr->octet[0]; 178745386Swpaul 1788131654Sbms switch (sc->ti_hwrev) { 178945386Swpaul case TI_HWREV_TIGON: 179045386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 179145386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 179245386Swpaul TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 179345386Swpaul break; 179445386Swpaul case TI_HWREV_TIGON_II: 179545386Swpaul ext[0] = htons(m[0]); 179645386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 179745386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 179845386Swpaul break; 179945386Swpaul default: 1800162321Sglebius device_printf(sc->ti_dev, "unknown hwrev\n"); 180145386Swpaul break; 180245386Swpaul } 180345386Swpaul} 180445386Swpaul 180545386Swpaul/* 180645386Swpaul * Configure the Tigon's multicast address filter. 180745386Swpaul * 180845386Swpaul * The actual multicast table management is a bit of a pain, thanks to 180945386Swpaul * slight brain damage on the part of both Alteon and us. With our 181045386Swpaul * multicast code, we are only alerted when the multicast address table 181145386Swpaul * changes and at that point we only have the current list of addresses: 181245386Swpaul * we only know the current state, not the previous state, so we don't 181345386Swpaul * actually know what addresses were removed or added. The firmware has 181445386Swpaul * state, but we can't get our grubby mits on it, and there is no 'delete 181545386Swpaul * all multicast addresses' command. Hence, we have to maintain our own 181645386Swpaul * state so we know what addresses have been programmed into the NIC at 181745386Swpaul * any given time. 181845386Swpaul */ 1819102336Salfredstatic void 1820102336Salfredti_setmulti(sc) 182145386Swpaul struct ti_softc *sc; 182245386Swpaul{ 182345386Swpaul struct ifnet *ifp; 182445386Swpaul struct ifmultiaddr *ifma; 182545386Swpaul struct ti_cmd_desc cmd; 182645386Swpaul struct ti_mc_entry *mc; 182745386Swpaul u_int32_t intrs; 182845386Swpaul 1829153770Syongari TI_LOCK_ASSERT(sc); 1830153770Syongari 1831147256Sbrooks ifp = sc->ti_ifp; 183245386Swpaul 183345386Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 183445386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 183545386Swpaul return; 183645386Swpaul } else { 183745386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 183845386Swpaul } 183945386Swpaul 184045386Swpaul /* Disable interrupts. */ 184145386Swpaul intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 184245386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 184345386Swpaul 184445386Swpaul /* First, zot all the existing filters. */ 184571999Sphk while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 184671999Sphk mc = SLIST_FIRST(&sc->ti_mc_listhead); 184745386Swpaul ti_del_mcast(sc, &mc->mc_addr); 184845386Swpaul SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 184945386Swpaul free(mc, M_DEVBUF); 185045386Swpaul } 185145386Swpaul 185245386Swpaul /* Now program new ones. */ 1853195049Srwatson if_maddr_rlock(ifp); 185472084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 185545386Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 185645386Swpaul continue; 185745386Swpaul mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1858144165Ssam if (mc == NULL) { 1859162321Sglebius device_printf(sc->ti_dev, 1860162321Sglebius "no memory for mcast filter entry\n"); 1861144165Ssam continue; 1862144165Ssam } 186345386Swpaul bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 186445386Swpaul (char *)&mc->mc_addr, ETHER_ADDR_LEN); 186545386Swpaul SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 186645386Swpaul ti_add_mcast(sc, &mc->mc_addr); 186745386Swpaul } 1868195049Srwatson if_maddr_runlock(ifp); 186945386Swpaul 187045386Swpaul /* Re-enable interrupts. */ 187145386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 187245386Swpaul} 187345386Swpaul 187445386Swpaul/* 187545386Swpaul * Check to see if the BIOS has configured us for a 64 bit slot when 187645386Swpaul * we aren't actually in one. If we detect this condition, we can work 187745386Swpaul * around it on the Tigon 2 by setting a bit in the PCI state register, 187845386Swpaul * but for the Tigon 1 we must give up and abort the interface attach. 187945386Swpaul */ 188045386Swpaulstatic int ti_64bitslot_war(sc) 188145386Swpaul struct ti_softc *sc; 188245386Swpaul{ 188345386Swpaul if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 188445386Swpaul CSR_WRITE_4(sc, 0x600, 0); 188545386Swpaul CSR_WRITE_4(sc, 0x604, 0); 188645386Swpaul CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 188745386Swpaul if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 188845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 1889131654Sbms return (EINVAL); 189045386Swpaul else { 189145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, 189245386Swpaul TI_PCISTATE_32BIT_BUS); 1893131654Sbms return (0); 189445386Swpaul } 189545386Swpaul } 189645386Swpaul } 189745386Swpaul 1898131654Sbms return (0); 189945386Swpaul} 190045386Swpaul 190145386Swpaul/* 190245386Swpaul * Do endian, PCI and DMA initialization. Also check the on-board ROM 190345386Swpaul * self-test results. 190445386Swpaul */ 1905102336Salfredstatic int 1906102336Salfredti_chipinit(sc) 190745386Swpaul struct ti_softc *sc; 190845386Swpaul{ 190945386Swpaul u_int32_t cacheline; 191045386Swpaul u_int32_t pci_writemax = 0; 191198849Sken u_int32_t hdrsplit; 191245386Swpaul 191345386Swpaul /* Initialize link to down state. */ 191445386Swpaul sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 191545386Swpaul 1916147256Sbrooks if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM) 1917147256Sbrooks sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 191883630Sjlemon else 1919147256Sbrooks sc->ti_ifp->if_hwassist = 0; 192058698Sjlemon 192145386Swpaul /* Set endianness before we access any non-PCI registers. */ 1922153770Syongari#if 0 && BYTE_ORDER == BIG_ENDIAN 192345386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 192445386Swpaul TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 192545386Swpaul#else 192645386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 192745386Swpaul TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 192845386Swpaul#endif 192945386Swpaul 193045386Swpaul /* Check the ROM failed bit to see if self-tests passed. */ 193145386Swpaul if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1932162321Sglebius device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 1933131654Sbms return (ENODEV); 193445386Swpaul } 193545386Swpaul 193645386Swpaul /* Halt the CPU. */ 193745386Swpaul TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 193845386Swpaul 193945386Swpaul /* Figure out the hardware revision. */ 1940131654Sbms switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 194145386Swpaul case TI_REV_TIGON_I: 194245386Swpaul sc->ti_hwrev = TI_HWREV_TIGON; 194345386Swpaul break; 194445386Swpaul case TI_REV_TIGON_II: 194545386Swpaul sc->ti_hwrev = TI_HWREV_TIGON_II; 194645386Swpaul break; 194745386Swpaul default: 1948162321Sglebius device_printf(sc->ti_dev, "unsupported chip revision\n"); 1949131654Sbms return (ENODEV); 195045386Swpaul } 195145386Swpaul 195245386Swpaul /* Do special setup for Tigon 2. */ 195345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 195445386Swpaul TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 195576033Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 195645386Swpaul TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 195745386Swpaul } 195845386Swpaul 195998849Sken /* 196098849Sken * We don't have firmware source for the Tigon 1, so Tigon 1 boards 196198849Sken * can't do header splitting. 196298849Sken */ 196398849Sken#ifdef TI_JUMBO_HDRSPLIT 196498849Sken if (sc->ti_hwrev != TI_HWREV_TIGON) 196598849Sken sc->ti_hdrsplit = 1; 196698849Sken else 1967162321Sglebius device_printf(sc->ti_dev, 1968150719Sjhb "can't do header splitting on a Tigon I board\n"); 196998849Sken#endif /* TI_JUMBO_HDRSPLIT */ 197098849Sken 197145386Swpaul /* Set up the PCI state register. */ 197245386Swpaul CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 197345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 197445386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 197545386Swpaul } 197645386Swpaul 197745386Swpaul /* Clear the read/write max DMA parameters. */ 197845386Swpaul TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 197945386Swpaul TI_PCISTATE_READ_MAXDMA)); 198045386Swpaul 198145386Swpaul /* Get cache line size. */ 198245386Swpaul cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 198345386Swpaul 198445386Swpaul /* 198545386Swpaul * If the system has set enabled the PCI memory write 198645386Swpaul * and invalidate command in the command register, set 198745386Swpaul * the write max parameter accordingly. This is necessary 198845386Swpaul * to use MWI with the Tigon 2. 198945386Swpaul */ 199045386Swpaul if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1991131654Sbms switch (cacheline) { 199245386Swpaul case 1: 199345386Swpaul case 4: 199445386Swpaul case 8: 199545386Swpaul case 16: 199645386Swpaul case 32: 199745386Swpaul case 64: 199845386Swpaul break; 199945386Swpaul default: 200045386Swpaul /* Disable PCI memory write and invalidate. */ 200145386Swpaul if (bootverbose) 2002162321Sglebius device_printf(sc->ti_dev, "cache line size %d" 2003162321Sglebius " not supported; disabling PCI MWI\n", 2004150719Sjhb cacheline); 200545386Swpaul CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 200645386Swpaul TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 200745386Swpaul break; 200845386Swpaul } 200945386Swpaul } 201045386Swpaul 201145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 201245386Swpaul 201345386Swpaul /* This sets the min dma param all the way up (0xff). */ 201445386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 201545386Swpaul 201698849Sken if (sc->ti_hdrsplit) 201798849Sken hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 201898849Sken else 201998849Sken hdrsplit = 0; 202098849Sken 202145386Swpaul /* Configure DMA variables. */ 202245386Swpaul#if BYTE_ORDER == BIG_ENDIAN 202345386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 202445386Swpaul TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 202545386Swpaul TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 202698849Sken TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 202798849Sken#else /* BYTE_ORDER */ 202845386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 202945386Swpaul TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 203098849Sken TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 203198849Sken#endif /* BYTE_ORDER */ 203245386Swpaul 203345386Swpaul /* 203445386Swpaul * Only allow 1 DMA channel to be active at a time. 203545386Swpaul * I don't think this is a good idea, but without it 203645386Swpaul * the firmware racks up lots of nicDmaReadRingFull 203758698Sjlemon * errors. This is not compatible with hardware checksums. 203845386Swpaul */ 2039147256Sbrooks if (sc->ti_ifp->if_hwassist == 0) 204058698Sjlemon TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 204145386Swpaul 204245386Swpaul /* Recommended settings from Tigon manual. */ 204345386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 204445386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 204545386Swpaul 204645386Swpaul if (ti_64bitslot_war(sc)) { 2047162321Sglebius device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2048150719Sjhb "but we aren't"); 2049131654Sbms return (EINVAL); 205045386Swpaul } 205145386Swpaul 2052131654Sbms return (0); 205345386Swpaul} 205445386Swpaul 205545386Swpaul/* 205645386Swpaul * Initialize the general information block and firmware, and 205745386Swpaul * start the CPU(s) running. 205845386Swpaul */ 2059102336Salfredstatic int 2060102336Salfredti_gibinit(sc) 206145386Swpaul struct ti_softc *sc; 206245386Swpaul{ 206345386Swpaul struct ti_rcb *rcb; 206445386Swpaul int i; 206545386Swpaul struct ifnet *ifp; 2066143903Sscottl uint32_t rdphys; 206745386Swpaul 2068153770Syongari TI_LOCK_ASSERT(sc); 2069153770Syongari 2070147256Sbrooks ifp = sc->ti_ifp; 2071143903Sscottl rdphys = sc->ti_rdata_phys; 207245386Swpaul 207345386Swpaul /* Disable interrupts for now. */ 207445386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 207545386Swpaul 2076143903Sscottl /* 2077143903Sscottl * Tell the chip where to find the general information block. 2078143903Sscottl * While this struct could go into >4GB memory, we allocate it in a 2079143903Sscottl * single slab with the other descriptors, and those don't seem to 2080143903Sscottl * support being located in a 64-bit region. 2081143903Sscottl */ 208245386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 2083143903Sscottl CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 208445386Swpaul 208545386Swpaul /* Load the firmware into SRAM. */ 208645386Swpaul ti_loadfw(sc); 208745386Swpaul 208845386Swpaul /* Set up the contents of the general info and ring control blocks. */ 208945386Swpaul 209045386Swpaul /* Set up the event ring and producer pointer. */ 209145386Swpaul rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 209245386Swpaul 2093143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 209445386Swpaul rcb->ti_flags = 0; 209545386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 2096143903Sscottl rdphys + TI_RD_OFF(ti_ev_prodidx_r); 209745386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 209845386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 209945386Swpaul sc->ti_ev_saved_considx = 0; 210045386Swpaul 210145386Swpaul /* Set up the command ring and producer mailbox. */ 210245386Swpaul rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 210345386Swpaul 210445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 210545386Swpaul rcb->ti_flags = 0; 210645386Swpaul rcb->ti_max_len = 0; 210745386Swpaul for (i = 0; i < TI_CMD_RING_CNT; i++) { 210845386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 210945386Swpaul } 211045386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 211145386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 211245386Swpaul sc->ti_cmd_saved_prodidx = 0; 211345386Swpaul 211445386Swpaul /* 211545386Swpaul * Assign the address of the stats refresh buffer. 211645386Swpaul * We re-use the current stats buffer for this to 211745386Swpaul * conserve memory. 211845386Swpaul */ 211945386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 2120143903Sscottl rdphys + TI_RD_OFF(ti_info.ti_stats); 212145386Swpaul 212245386Swpaul /* Set up the standard receive ring. */ 212345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 2124143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 212545386Swpaul rcb->ti_max_len = TI_FRAMELEN; 212645386Swpaul rcb->ti_flags = 0; 2127147256Sbrooks if (sc->ti_ifp->if_hwassist) 212858698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 212958698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 213045386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 213145386Swpaul 213245386Swpaul /* Set up the jumbo receive ring. */ 213345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 2134143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 213598849Sken 213698849Sken#ifdef TI_PRIVATE_JUMBOS 213749036Swpaul rcb->ti_max_len = TI_JUMBO_FRAMELEN; 213845386Swpaul rcb->ti_flags = 0; 213998849Sken#else 214098849Sken rcb->ti_max_len = PAGE_SIZE; 214198849Sken rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 214298849Sken#endif 2143147256Sbrooks if (sc->ti_ifp->if_hwassist) 214458698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 214558698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 214645386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 214745386Swpaul 214845386Swpaul /* 214945386Swpaul * Set up the mini ring. Only activated on the 215045386Swpaul * Tigon 2 but the slot in the config block is 215145386Swpaul * still there on the Tigon 1. 215245386Swpaul */ 215345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 2154143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 215551352Swpaul rcb->ti_max_len = MHLEN - ETHER_ALIGN; 215645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 215745386Swpaul rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 215845386Swpaul else 215945386Swpaul rcb->ti_flags = 0; 2160147256Sbrooks if (sc->ti_ifp->if_hwassist) 216158698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 216258698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 216345386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 216445386Swpaul 216545386Swpaul /* 216645386Swpaul * Set up the receive return ring. 216745386Swpaul */ 216845386Swpaul rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 2169143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 217045386Swpaul rcb->ti_flags = 0; 217145386Swpaul rcb->ti_max_len = TI_RETURN_RING_CNT; 217245386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 2173143903Sscottl rdphys + TI_RD_OFF(ti_return_prodidx_r); 217445386Swpaul 217545386Swpaul /* 217645386Swpaul * Set up the tx ring. Note: for the Tigon 2, we have the option 217745386Swpaul * of putting the transmit ring in the host's address space and 217845386Swpaul * letting the chip DMA it instead of leaving the ring in the NIC's 217945386Swpaul * memory and accessing it through the shared memory region. We 218045386Swpaul * do this for the Tigon 2, but it doesn't work on the Tigon 1, 218145386Swpaul * so we have to revert to the shared memory scheme if we detect 218245386Swpaul * a Tigon 1 chip. 218345386Swpaul */ 218445386Swpaul CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 218545386Swpaul bzero((char *)sc->ti_rdata->ti_tx_ring, 218645386Swpaul TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 218745386Swpaul rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 218845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 218945386Swpaul rcb->ti_flags = 0; 219045386Swpaul else 219145386Swpaul rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 219245386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2193147256Sbrooks if (sc->ti_ifp->if_hwassist) 219458698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 219558698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 219645386Swpaul rcb->ti_max_len = TI_TX_RING_CNT; 219745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 219845386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 219945386Swpaul else 2200143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 220145386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2202143903Sscottl rdphys + TI_RD_OFF(ti_tx_considx_r); 220345386Swpaul 2204153770Syongari bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2205153770Syongari BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2206153770Syongari 220745386Swpaul /* Set up tuneables */ 220898849Sken#if 0 220945386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 221045386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 221145386Swpaul (sc->ti_rx_coal_ticks / 10)); 221245386Swpaul else 221398849Sken#endif 221445386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 221545386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 221645386Swpaul CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 221745386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 221845386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 221945386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 222045386Swpaul 222145386Swpaul /* Turn interrupts on. */ 222245386Swpaul CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 222345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 222445386Swpaul 222545386Swpaul /* Start CPU. */ 222645386Swpaul TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 222745386Swpaul 2228131654Sbms return (0); 222945386Swpaul} 223045386Swpaul 2231143903Sscottlstatic void 2232143903Sscottlti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2233143903Sscottl{ 2234143903Sscottl struct ti_softc *sc; 2235143903Sscottl 2236143903Sscottl sc = arg; 2237143903Sscottl if (error || nseg != 1) 2238143903Sscottl return; 2239143903Sscottl 2240143903Sscottl /* 2241143903Sscottl * All of the Tigon data structures need to live at <4GB. This 2242143903Sscottl * cast is fine since busdma was told about this constraint. 2243143903Sscottl */ 2244153770Syongari sc->ti_rdata_phys = segs[0].ds_addr; 2245143903Sscottl return; 2246143903Sscottl} 2247143903Sscottl 224845386Swpaul/* 224945386Swpaul * Probe for a Tigon chip. Check the PCI vendor and device IDs 225045386Swpaul * against our list and return its name if we find a match. 225145386Swpaul */ 2252102336Salfredstatic int 2253102336Salfredti_probe(dev) 225449011Swpaul device_t dev; 225545386Swpaul{ 2256219547Smarius const struct ti_type *t; 225745386Swpaul 225845386Swpaul t = ti_devs; 225945386Swpaul 2260131654Sbms while (t->ti_name != NULL) { 226149011Swpaul if ((pci_get_vendor(dev) == t->ti_vid) && 226249011Swpaul (pci_get_device(dev) == t->ti_did)) { 226349011Swpaul device_set_desc(dev, t->ti_name); 2264142398Simp return (BUS_PROBE_DEFAULT); 226549011Swpaul } 226645386Swpaul t++; 226745386Swpaul } 226845386Swpaul 2269131654Sbms return (ENXIO); 227045386Swpaul} 227145386Swpaul 227298849Skenstatic int 2273102336Salfredti_attach(dev) 227449011Swpaul device_t dev; 227545386Swpaul{ 227645386Swpaul struct ifnet *ifp; 227745386Swpaul struct ti_softc *sc; 2278150719Sjhb int error = 0, rid; 2279147256Sbrooks u_char eaddr[6]; 228045386Swpaul 228149011Swpaul sc = device_get_softc(dev); 2282150719Sjhb sc->ti_unit = device_get_unit(dev); 2283153396Sscottl sc->ti_dev = dev; 228445386Swpaul 228593818Sjhb mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2286153770Syongari MTX_DEF); 2287199559Sjhb callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2288113609Snjl ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2289147805Sscottl ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2290147805Sscottl if (ifp == NULL) { 2291150719Sjhb device_printf(dev, "can not if_alloc()\n"); 2292147805Sscottl error = ENOSPC; 2293147805Sscottl goto fail; 2294147805Sscottl } 2295147256Sbrooks sc->ti_ifp->if_capabilities = IFCAP_HWCSUM | 2296118454Ssimokawa IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2297147256Sbrooks sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 229869583Swpaul 229945386Swpaul /* 230045386Swpaul * Map control/status registers. 230145386Swpaul */ 230272813Swpaul pci_enable_busmaster(dev); 230345386Swpaul 230449011Swpaul rid = TI_PCI_LOMEM; 2305127135Snjl sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2306178588Smarius RF_ACTIVE); 230749011Swpaul 230849011Swpaul if (sc->ti_res == NULL) { 2309150719Sjhb device_printf(dev, "couldn't map memory\n"); 231049011Swpaul error = ENXIO; 231145386Swpaul goto fail; 231245386Swpaul } 231345386Swpaul 231449035Swpaul sc->ti_btag = rman_get_bustag(sc->ti_res); 231549035Swpaul sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 231649035Swpaul 231749011Swpaul /* Allocate interrupt */ 231849011Swpaul rid = 0; 2319131652Sbms 2320127135Snjl sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 232149011Swpaul RF_SHAREABLE | RF_ACTIVE); 232245386Swpaul 232349011Swpaul if (sc->ti_irq == NULL) { 2324150719Sjhb device_printf(dev, "couldn't map interrupt\n"); 232549011Swpaul error = ENXIO; 232645386Swpaul goto fail; 232745386Swpaul } 232845386Swpaul 232945386Swpaul if (ti_chipinit(sc)) { 2330150719Sjhb device_printf(dev, "chip initialization failed\n"); 233149011Swpaul error = ENXIO; 233245386Swpaul goto fail; 233345386Swpaul } 233445386Swpaul 233545386Swpaul /* Zero out the NIC's on-board SRAM. */ 2336153770Syongari ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 233745386Swpaul 233845386Swpaul /* Init again -- zeroing memory may have clobbered some registers. */ 233945386Swpaul if (ti_chipinit(sc)) { 2340150719Sjhb device_printf(dev, "chip initialization failed\n"); 234149011Swpaul error = ENXIO; 234245386Swpaul goto fail; 234345386Swpaul } 234445386Swpaul 234545386Swpaul /* 234645386Swpaul * Get station address from the EEPROM. Note: the manual states 234745386Swpaul * that the MAC address is at offset 0x8c, however the data is 234845386Swpaul * stored as two longwords (since that's how it's loaded into 234972645Sasmodai * the NIC). This means the MAC address is actually preceded 235045386Swpaul * by two zero bytes. We need to skip over those. 235145386Swpaul */ 2352147256Sbrooks if (ti_read_eeprom(sc, eaddr, 235345386Swpaul TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2354150719Sjhb device_printf(dev, "failed to read station address\n"); 235549011Swpaul error = ENXIO; 235645386Swpaul goto fail; 235745386Swpaul } 235845386Swpaul 235945386Swpaul /* Allocate the general information block and ring buffers. */ 2360166165Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 2361143903Sscottl 1, 0, /* algnmnt, boundary */ 2362143903Sscottl BUS_SPACE_MAXADDR, /* lowaddr */ 2363143903Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 2364143903Sscottl NULL, NULL, /* filter, filterarg */ 2365143903Sscottl BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2366143903Sscottl 0, /* nsegments */ 2367143903Sscottl BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2368143903Sscottl 0, /* flags */ 2369143903Sscottl NULL, NULL, /* lockfunc, lockarg */ 2370143903Sscottl &sc->ti_parent_dmat) != 0) { 2371150719Sjhb device_printf(dev, "Failed to allocate parent dmat\n"); 2372143903Sscottl error = ENOMEM; 2373143903Sscottl goto fail; 2374143903Sscottl } 237545386Swpaul 2376143903Sscottl if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2377143903Sscottl PAGE_SIZE, 0, /* algnmnt, boundary */ 2378143903Sscottl BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2379143903Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 2380143903Sscottl NULL, NULL, /* filter, filterarg */ 2381143903Sscottl sizeof(struct ti_ring_data), /* maxsize */ 2382143903Sscottl 1, /* nsegments */ 2383143903Sscottl sizeof(struct ti_ring_data), /* maxsegsize */ 2384143903Sscottl 0, /* flags */ 2385143903Sscottl NULL, NULL, /* lockfunc, lockarg */ 2386143903Sscottl &sc->ti_rdata_dmat) != 0) { 2387150719Sjhb device_printf(dev, "Failed to allocate rdata dmat\n"); 2388143903Sscottl error = ENOMEM; 238945386Swpaul goto fail; 239045386Swpaul } 239145386Swpaul 2392143903Sscottl if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2393219547Smarius BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 2394219547Smarius &sc->ti_rdata_dmamap) != 0) { 2395150719Sjhb device_printf(dev, "Failed to allocate rdata memory\n"); 2396143903Sscottl error = ENOMEM; 2397143903Sscottl goto fail; 2398143903Sscottl } 2399143903Sscottl 2400143903Sscottl if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2401143903Sscottl sc->ti_rdata, sizeof(struct ti_ring_data), 2402143903Sscottl ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2403150719Sjhb device_printf(dev, "Failed to load rdata segments\n"); 2404143903Sscottl error = ENOMEM; 2405143903Sscottl goto fail; 2406143903Sscottl } 2407143903Sscottl 240845386Swpaul bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 240945386Swpaul 241045386Swpaul /* Try to allocate memory for jumbo buffers. */ 241145386Swpaul if (ti_alloc_jumbo_mem(sc)) { 2412150719Sjhb device_printf(dev, "jumbo buffer allocation failed\n"); 241349011Swpaul error = ENXIO; 241445386Swpaul goto fail; 241545386Swpaul } 241645386Swpaul 2417153396Sscottl if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2418153396Sscottl 1, 0, /* algnmnt, boundary */ 2419153396Sscottl BUS_SPACE_MAXADDR, /* lowaddr */ 2420153396Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 2421153396Sscottl NULL, NULL, /* filter, filterarg */ 2422153396Sscottl MCLBYTES * TI_MAXTXSEGS,/* maxsize */ 2423153396Sscottl TI_MAXTXSEGS, /* nsegments */ 2424153396Sscottl MCLBYTES, /* maxsegsize */ 2425153396Sscottl 0, /* flags */ 2426153396Sscottl NULL, NULL, /* lockfunc, lockarg */ 2427153396Sscottl &sc->ti_mbuftx_dmat) != 0) { 2428153396Sscottl device_printf(dev, "Failed to allocate rdata dmat\n"); 2429153396Sscottl error = ENOMEM; 2430153396Sscottl goto fail; 2431153396Sscottl } 2432153396Sscottl 2433153396Sscottl if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2434153396Sscottl 1, 0, /* algnmnt, boundary */ 2435153396Sscottl BUS_SPACE_MAXADDR, /* lowaddr */ 2436153396Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 2437153396Sscottl NULL, NULL, /* filter, filterarg */ 2438153396Sscottl MCLBYTES, /* maxsize */ 2439153396Sscottl 1, /* nsegments */ 2440153396Sscottl MCLBYTES, /* maxsegsize */ 2441153396Sscottl 0, /* flags */ 2442153396Sscottl NULL, NULL, /* lockfunc, lockarg */ 2443153396Sscottl &sc->ti_mbufrx_dmat) != 0) { 2444153396Sscottl device_printf(dev, "Failed to allocate rdata dmat\n"); 2445153396Sscottl error = ENOMEM; 2446153396Sscottl goto fail; 2447153396Sscottl } 2448153396Sscottl 2449153396Sscottl if (ti_alloc_dmamaps(sc)) { 2450153396Sscottl device_printf(dev, "dma map creation failed\n"); 2451153396Sscottl error = ENXIO; 2452153396Sscottl goto fail; 2453153396Sscottl } 2454153396Sscottl 245563699Swpaul /* 245663699Swpaul * We really need a better way to tell a 1000baseTX card 245763699Swpaul * from a 1000baseSX one, since in theory there could be 245863699Swpaul * OEMed 1000baseTX cards from lame vendors who aren't 245963699Swpaul * clever enough to change the PCI ID. For the moment 246063699Swpaul * though, the AceNIC is the only copper card available. 246163699Swpaul */ 246263699Swpaul if (pci_get_vendor(dev) == ALT_VENDORID && 246363699Swpaul pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 246463699Swpaul sc->ti_copper = 1; 246564139Swpaul /* Ok, it's not the only copper card available. */ 246664139Swpaul if (pci_get_vendor(dev) == NG_VENDORID && 246764139Swpaul pci_get_device(dev) == NG_DEVICEID_GA620T) 246864139Swpaul sc->ti_copper = 1; 246963699Swpaul 247045386Swpaul /* Set default tuneable values. */ 247145386Swpaul sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 247298849Sken#if 0 247345386Swpaul sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 247498849Sken#endif 247598849Sken sc->ti_rx_coal_ticks = 170; 247645386Swpaul sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 247745386Swpaul sc->ti_rx_max_coal_bds = 64; 247898849Sken#if 0 247945386Swpaul sc->ti_tx_max_coal_bds = 128; 248098849Sken#endif 248198849Sken sc->ti_tx_max_coal_bds = 32; 248245386Swpaul sc->ti_tx_buf_ratio = 21; 248345386Swpaul 248445386Swpaul /* Set up ifnet structure */ 248545386Swpaul ifp->if_softc = sc; 2486121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2487153281Sscottl ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 248845386Swpaul ifp->if_ioctl = ti_ioctl; 248945386Swpaul ifp->if_start = ti_start; 249045386Swpaul ifp->if_init = ti_init; 2491176413Sremko ifp->if_baudrate = 1000000000; 249245386Swpaul ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 249345386Swpaul 249445386Swpaul /* Set up ifmedia support. */ 249563699Swpaul if (sc->ti_copper) { 249663699Swpaul /* 249763699Swpaul * Copper cards allow manual 10/100 mode selection, 249863699Swpaul * but not manual 1000baseTX mode selection. Why? 249963699Swpaul * Becuase currently there's no way to specify the 250063699Swpaul * master/slave setting through the firmware interface, 250163699Swpaul * so Alteon decided to just bag it and handle it 250263699Swpaul * via autonegotiation. 250363699Swpaul */ 250463699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 250563699Swpaul ifmedia_add(&sc->ifmedia, 250663699Swpaul IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 250763699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 250863699Swpaul ifmedia_add(&sc->ifmedia, 250963699Swpaul IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 251095673Sphk ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 251163699Swpaul ifmedia_add(&sc->ifmedia, 251295673Sphk IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 251363699Swpaul } else { 251463699Swpaul /* Fiber cards don't support 10/100 modes. */ 251563699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 251663699Swpaul ifmedia_add(&sc->ifmedia, 251763699Swpaul IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 251863699Swpaul } 251945386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 252045386Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 252145386Swpaul 252245386Swpaul /* 252398849Sken * We're assuming here that card initialization is a sequential 252498849Sken * thing. If it isn't, multiple cards probing at the same time 252598849Sken * could stomp on the list of softcs here. 252698849Sken */ 252798849Sken 252898849Sken /* Register the device */ 252998849Sken sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 253098849Sken 0600, "ti%d", sc->ti_unit); 2531120980Sphk sc->dev->si_drv1 = sc; 253298849Sken 253398849Sken /* 253463090Sarchie * Call MI attach routine. 253545386Swpaul */ 2536147256Sbrooks ether_ifattach(ifp, eaddr); 253745386Swpaul 2538113609Snjl /* Hook interrupt last to avoid having to lock softc */ 2539153281Sscottl error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2540166901Spiso NULL, ti_intr, sc, &sc->ti_intrhand); 2541112872Snjl 2542112872Snjl if (error) { 2543150719Sjhb device_printf(dev, "couldn't set up irq\n"); 2544112872Snjl goto fail; 2545112872Snjl } 2546112872Snjl 254745386Swpaulfail: 2548153770Syongari if (error) 2549112872Snjl ti_detach(dev); 2550112872Snjl 2551131654Sbms return (error); 255245386Swpaul} 255345386Swpaul 255498849Sken/* 2555113609Snjl * Shutdown hardware and free up resources. This can be called any 2556113609Snjl * time after the mutex has been initialized. It is called in both 2557113609Snjl * the error case in attach and the normal detach case so it needs 2558113609Snjl * to be careful about only freeing resources that have actually been 2559113609Snjl * allocated. 2560113609Snjl */ 2561102336Salfredstatic int 2562102336Salfredti_detach(dev) 256349011Swpaul device_t dev; 256449011Swpaul{ 256549011Swpaul struct ti_softc *sc; 256649011Swpaul struct ifnet *ifp; 256749011Swpaul 256849011Swpaul sc = device_get_softc(dev); 2569144407Sscottl if (sc->dev) 2570144407Sscottl destroy_dev(sc->dev); 2571112930Sphk KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2572147256Sbrooks ifp = sc->ti_ifp; 2573199559Sjhb if (device_is_attached(dev)) { 2574199559Sjhb ether_ifdetach(ifp); 2575199559Sjhb TI_LOCK(sc); 2576153770Syongari ti_stop(sc); 2577199559Sjhb TI_UNLOCK(sc); 2578199559Sjhb } 257949011Swpaul 2580113609Snjl /* These should only be active if attach succeeded */ 2581199559Sjhb callout_drain(&sc->ti_watchdog); 2582199559Sjhb bus_generic_detach(dev); 2583153770Syongari ti_free_dmamaps(sc); 2584113609Snjl ifmedia_removeall(&sc->ifmedia); 258549011Swpaul 2586153288Sscottl#ifdef TI_PRIVATE_JUMBOS 2587153288Sscottl if (sc->ti_cdata.ti_jumbo_buf) 2588153288Sscottl bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf, 2589153288Sscottl sc->ti_jumbo_dmamap); 2590153396Sscottl#endif 2591153288Sscottl if (sc->ti_jumbo_dmat) 2592153288Sscottl bus_dma_tag_destroy(sc->ti_jumbo_dmat); 2593153396Sscottl if (sc->ti_mbuftx_dmat) 2594153396Sscottl bus_dma_tag_destroy(sc->ti_mbuftx_dmat); 2595153396Sscottl if (sc->ti_mbufrx_dmat) 2596153396Sscottl bus_dma_tag_destroy(sc->ti_mbufrx_dmat); 2597143903Sscottl if (sc->ti_rdata) 2598143903Sscottl bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2599143903Sscottl sc->ti_rdata_dmamap); 2600143903Sscottl if (sc->ti_rdata_dmat) 2601143903Sscottl bus_dma_tag_destroy(sc->ti_rdata_dmat); 2602143903Sscottl if (sc->ti_parent_dmat) 2603143903Sscottl bus_dma_tag_destroy(sc->ti_parent_dmat); 2604112872Snjl if (sc->ti_intrhand) 2605112872Snjl bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2606112872Snjl if (sc->ti_irq) 2607112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2608112872Snjl if (sc->ti_res) { 2609112872Snjl bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2610112872Snjl sc->ti_res); 2611112872Snjl } 2612151297Sru if (ifp) 2613151297Sru if_free(ifp); 261449011Swpaul 261567087Swpaul mtx_destroy(&sc->ti_mtx); 261649011Swpaul 2617131654Sbms return (0); 261849011Swpaul} 261949011Swpaul 262098849Sken#ifdef TI_JUMBO_HDRSPLIT 262145386Swpaul/* 262298849Sken * If hdr_len is 0, that means that header splitting wasn't done on 262398849Sken * this packet for some reason. The two most likely reasons are that 262498849Sken * the protocol isn't a supported protocol for splitting, or this 262598849Sken * packet had a fragment offset that wasn't 0. 262698849Sken * 262798849Sken * The header length, if it is non-zero, will always be the length of 262898849Sken * the headers on the packet, but that length could be longer than the 262998849Sken * first mbuf. So we take the minimum of the two as the actual 2630131652Sbms * length. 263198849Sken */ 263298849Skenstatic __inline void 263398849Skenti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 263498849Sken{ 263598849Sken int i = 0; 263698849Sken int lengths[4] = {0, 0, 0, 0}; 263798849Sken struct mbuf *m, *mp; 263898849Sken 263998849Sken if (hdr_len != 0) 264098849Sken top->m_len = min(hdr_len, top->m_len); 264198849Sken pkt_len -= top->m_len; 264298849Sken lengths[i++] = top->m_len; 264398849Sken 264498849Sken mp = top; 264598849Sken for (m = top->m_next; m && pkt_len; m = m->m_next) { 264698849Sken m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 264798849Sken pkt_len -= m->m_len; 264898849Sken lengths[i++] = m->m_len; 264998849Sken mp = m; 265098849Sken } 265198849Sken 265298849Sken#if 0 265398849Sken if (hdr_len != 0) 265498849Sken printf("got split packet: "); 265598849Sken else 265698849Sken printf("got non-split packet: "); 2657131652Sbms 265898849Sken printf("%d,%d,%d,%d = %d\n", lengths[0], 265998849Sken lengths[1], lengths[2], lengths[3], 266098849Sken lengths[0] + lengths[1] + lengths[2] + 266198849Sken lengths[3]); 266298849Sken#endif 266398849Sken 266498849Sken if (pkt_len) 266598849Sken panic("header splitting didn't"); 2666131652Sbms 266798849Sken if (m) { 266898849Sken m_freem(m); 266998849Sken mp->m_next = NULL; 267098849Sken 267198849Sken } 267298849Sken if (mp->m_next != NULL) 267398849Sken panic("ti_hdr_split: last mbuf in chain should be null"); 267498849Sken} 267598849Sken#endif /* TI_JUMBO_HDRSPLIT */ 267698849Sken 267798849Sken/* 267845386Swpaul * Frame reception handling. This is called if there's a frame 267945386Swpaul * on the receive return list. 268045386Swpaul * 268145386Swpaul * Note: we have to be able to handle three possibilities here: 268245386Swpaul * 1) the frame is from the mini receive ring (can only happen) 268345386Swpaul * on Tigon 2 boards) 268445386Swpaul * 2) the frame is from the jumbo recieve ring 268545386Swpaul * 3) the frame is from the standard receive ring 268645386Swpaul */ 268745386Swpaul 2688102336Salfredstatic void 2689102336Salfredti_rxeof(sc) 269045386Swpaul struct ti_softc *sc; 269145386Swpaul{ 2692153396Sscottl bus_dmamap_t map; 269345386Swpaul struct ifnet *ifp; 269448597Swpaul struct ti_cmd_desc cmd; 269545386Swpaul 2696122689Ssam TI_LOCK_ASSERT(sc); 2697122689Ssam 2698147256Sbrooks ifp = sc->ti_ifp; 269945386Swpaul 2700131654Sbms while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 270145386Swpaul struct ti_rx_desc *cur_rx; 270245386Swpaul u_int32_t rxidx; 270345386Swpaul struct mbuf *m = NULL; 270445386Swpaul u_int16_t vlan_tag = 0; 270545386Swpaul int have_tag = 0; 270645386Swpaul 270745386Swpaul cur_rx = 270845386Swpaul &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 270945386Swpaul rxidx = cur_rx->ti_idx; 271045386Swpaul TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 271145386Swpaul 271245386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 271345386Swpaul have_tag = 1; 271477058Sphk vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 271545386Swpaul } 271645386Swpaul 271745386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 271898849Sken 271945386Swpaul TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 272045386Swpaul m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 272145386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2722153396Sscottl map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2723153396Sscottl bus_dmamap_sync(sc->ti_jumbo_dmat, map, 2724153396Sscottl BUS_DMASYNC_POSTREAD); 2725153396Sscottl bus_dmamap_unload(sc->ti_jumbo_dmat, map); 272645386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 272745386Swpaul ifp->if_ierrors++; 272845386Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 272945386Swpaul continue; 273045386Swpaul } 273148597Swpaul if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 273248597Swpaul ifp->if_ierrors++; 273348597Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 273448597Swpaul continue; 273548597Swpaul } 273698849Sken#ifdef TI_PRIVATE_JUMBOS 2737131655Sbms m->m_len = cur_rx->ti_len; 273898849Sken#else /* TI_PRIVATE_JUMBOS */ 273998849Sken#ifdef TI_JUMBO_HDRSPLIT 274098849Sken if (sc->ti_hdrsplit) 274198849Sken ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 274298849Sken cur_rx->ti_len, rxidx); 274398849Sken else 274498849Sken#endif /* TI_JUMBO_HDRSPLIT */ 2745131655Sbms m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 274698849Sken#endif /* TI_PRIVATE_JUMBOS */ 274745386Swpaul } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 274845386Swpaul TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 274945386Swpaul m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 275045386Swpaul sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2751153396Sscottl map = sc->ti_cdata.ti_rx_mini_maps[rxidx]; 2752153396Sscottl bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2753153396Sscottl BUS_DMASYNC_POSTREAD); 2754153396Sscottl bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 275545386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 275645386Swpaul ifp->if_ierrors++; 275745386Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 275845386Swpaul continue; 275945386Swpaul } 276048597Swpaul if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 276148597Swpaul ifp->if_ierrors++; 276248597Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 276348597Swpaul continue; 276448597Swpaul } 276598849Sken m->m_len = cur_rx->ti_len; 276645386Swpaul } else { 276745386Swpaul TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 276845386Swpaul m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 276945386Swpaul sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2770153396Sscottl map = sc->ti_cdata.ti_rx_std_maps[rxidx]; 2771153396Sscottl bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2772153396Sscottl BUS_DMASYNC_POSTREAD); 2773153396Sscottl bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 277445386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 277545386Swpaul ifp->if_ierrors++; 277645386Swpaul ti_newbuf_std(sc, sc->ti_std, m); 277745386Swpaul continue; 277845386Swpaul } 277948597Swpaul if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 278048597Swpaul ifp->if_ierrors++; 278148597Swpaul ti_newbuf_std(sc, sc->ti_std, m); 278248597Swpaul continue; 278348597Swpaul } 278498849Sken m->m_len = cur_rx->ti_len; 278545386Swpaul } 278645386Swpaul 278798849Sken m->m_pkthdr.len = cur_rx->ti_len; 278845386Swpaul ifp->if_ipackets++; 278945386Swpaul m->m_pkthdr.rcvif = ifp; 279045386Swpaul 279158698Sjlemon if (ifp->if_hwassist) { 279258698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 279358698Sjlemon CSUM_DATA_VALID; 279458698Sjlemon if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 279558698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 279658698Sjlemon m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 279758698Sjlemon } 279845386Swpaul 279945386Swpaul /* 2800106936Ssam * If we received a packet with a vlan tag, 2801106936Ssam * tag it before passing the packet upward. 280245386Swpaul */ 2803153512Sglebius if (have_tag) { 2804162375Sandre m->m_pkthdr.ether_vtag = vlan_tag; 2805162375Sandre m->m_flags |= M_VLANTAG; 2806153512Sglebius } 2807122689Ssam TI_UNLOCK(sc); 2808106936Ssam (*ifp->if_input)(ifp, m); 2809122689Ssam TI_LOCK(sc); 281045386Swpaul } 281145386Swpaul 281245386Swpaul /* Only necessary on the Tigon 1. */ 281345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 281445386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 281545386Swpaul sc->ti_rx_saved_considx); 281645386Swpaul 281748597Swpaul TI_UPDATE_STDPROD(sc, sc->ti_std); 281848597Swpaul TI_UPDATE_MINIPROD(sc, sc->ti_mini); 281948597Swpaul TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 282045386Swpaul} 282145386Swpaul 2822102336Salfredstatic void 2823102336Salfredti_txeof(sc) 282445386Swpaul struct ti_softc *sc; 282545386Swpaul{ 2826153982Syongari struct ti_txdesc *txd; 2827153982Syongari struct ti_tx_desc txdesc; 282845386Swpaul struct ti_tx_desc *cur_tx = NULL; 282945386Swpaul struct ifnet *ifp; 2830153982Syongari int idx; 283145386Swpaul 2832147256Sbrooks ifp = sc->ti_ifp; 283345386Swpaul 2834153982Syongari txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2835153982Syongari if (txd == NULL) 2836153982Syongari return; 283745386Swpaul /* 283845386Swpaul * Go through our tx ring and free mbufs for those 283945386Swpaul * frames that have been sent. 284045386Swpaul */ 2841153982Syongari for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2842153982Syongari TI_INC(idx, TI_TX_RING_CNT)) { 284345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 2844153770Syongari ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2845153770Syongari sizeof(txdesc), &txdesc); 2846153770Syongari cur_tx = &txdesc; 284745386Swpaul } else 284845386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 284948011Swpaul sc->ti_txcnt--; 2850153982Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2851153982Syongari if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2852153982Syongari continue; 2853153982Syongari bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2854153982Syongari BUS_DMASYNC_POSTWRITE); 2855153982Syongari bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2856153982Syongari 2857153982Syongari ifp->if_opackets++; 2858153982Syongari m_freem(txd->tx_m); 2859153982Syongari txd->tx_m = NULL; 2860153982Syongari STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2861153982Syongari STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2862153982Syongari txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 286345386Swpaul } 2864153982Syongari sc->ti_tx_saved_considx = idx; 286545386Swpaul 2866199559Sjhb sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0; 286745386Swpaul} 286845386Swpaul 2869102336Salfredstatic void 2870102336Salfredti_intr(xsc) 287145386Swpaul void *xsc; 287245386Swpaul{ 287345386Swpaul struct ti_softc *sc; 287445386Swpaul struct ifnet *ifp; 287545386Swpaul 287645386Swpaul sc = xsc; 287767087Swpaul TI_LOCK(sc); 2878147256Sbrooks ifp = sc->ti_ifp; 287945386Swpaul 288098849Sken/*#ifdef notdef*/ 288145386Swpaul /* Avoid this for now -- checking this register is expensive. */ 288245386Swpaul /* Make sure this is really our interrupt. */ 288367087Swpaul if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 288467087Swpaul TI_UNLOCK(sc); 288545386Swpaul return; 288667087Swpaul } 288798849Sken/*#endif*/ 288845386Swpaul 288945386Swpaul /* Ack interrupt and stop others from occuring. */ 289045386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 289145386Swpaul 2892148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 289345386Swpaul /* Check RX return ring producer/consumer */ 289445386Swpaul ti_rxeof(sc); 289545386Swpaul 289645386Swpaul /* Check TX ring producer/consumer */ 289745386Swpaul ti_txeof(sc); 289845386Swpaul } 289945386Swpaul 290045386Swpaul ti_handle_events(sc); 290145386Swpaul 290245386Swpaul /* Re-enable interrupts. */ 290345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 290445386Swpaul 2905148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2906148887Srwatson ifp->if_snd.ifq_head != NULL) 2907153770Syongari ti_start_locked(ifp); 290845386Swpaul 290967087Swpaul TI_UNLOCK(sc); 291045386Swpaul} 291145386Swpaul 2912102336Salfredstatic void 2913102336Salfredti_stats_update(sc) 291445386Swpaul struct ti_softc *sc; 291545386Swpaul{ 291645386Swpaul struct ifnet *ifp; 291745386Swpaul 2918147256Sbrooks ifp = sc->ti_ifp; 291945386Swpaul 2920153770Syongari bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2921153770Syongari BUS_DMASYNC_POSTREAD); 2922153770Syongari 292345386Swpaul ifp->if_collisions += 292445386Swpaul (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 292545386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 292645386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 292745386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 292845386Swpaul ifp->if_collisions; 2929153770Syongari 2930153770Syongari bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2931153770Syongari BUS_DMASYNC_PREREAD); 293245386Swpaul} 293345386Swpaul 2934153982Syongari/* 2935153982Syongari * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2936153982Syongari * pointers to descriptors. 2937153982Syongari */ 2938153982Syongaristatic int 2939153982Syongariti_encap(sc, m_head) 2940153982Syongari struct ti_softc *sc; 2941153982Syongari struct mbuf **m_head; 2942153396Sscottl{ 2943153982Syongari struct ti_txdesc *txd; 2944153982Syongari struct ti_tx_desc *f; 2945153770Syongari struct ti_tx_desc txdesc; 2946161236Syongari struct mbuf *m; 2947153982Syongari bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 2948153396Sscottl u_int16_t csum_flags; 2949153982Syongari int error, frag, i, nseg; 2950153396Sscottl 2951153982Syongari if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 2952153982Syongari return (ENOBUFS); 2953153396Sscottl 2954153982Syongari error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2955161236Syongari *m_head, txsegs, &nseg, 0); 2956153982Syongari if (error == EFBIG) { 2957161236Syongari m = m_defrag(*m_head, M_DONTWAIT); 2958161236Syongari if (m == NULL) { 2959161236Syongari m_freem(*m_head); 2960161236Syongari *m_head = NULL; 2961153982Syongari return (ENOMEM); 2962153982Syongari } 2963161236Syongari *m_head = m; 2964153982Syongari error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, 2965161236Syongari txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2966153982Syongari if (error) { 2967161236Syongari m_freem(*m_head); 2968161236Syongari *m_head = NULL; 2969153982Syongari return (error); 2970153982Syongari } 2971153982Syongari } else if (error != 0) 2972153982Syongari return (error); 2973153982Syongari if (nseg == 0) { 2974161236Syongari m_freem(*m_head); 2975161236Syongari *m_head = NULL; 2976153982Syongari return (EIO); 2977153776Sscottl } 2978153776Sscottl 2979153982Syongari if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 2980153982Syongari bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2981153982Syongari return (ENOBUFS); 2982153982Syongari } 2983153982Syongari 2984161236Syongari m = *m_head; 2985161236Syongari csum_flags = 0; 2986161236Syongari if (m->m_pkthdr.csum_flags) { 2987161236Syongari if (m->m_pkthdr.csum_flags & CSUM_IP) 2988161236Syongari csum_flags |= TI_BDFLAG_IP_CKSUM; 2989161236Syongari if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2990161236Syongari csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2991161236Syongari if (m->m_flags & M_LASTFRAG) 2992161236Syongari csum_flags |= TI_BDFLAG_IP_FRAG_END; 2993161236Syongari else if (m->m_flags & M_FRAG) 2994161236Syongari csum_flags |= TI_BDFLAG_IP_FRAG; 2995161236Syongari } 2996161236Syongari 2997153982Syongari bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2998153982Syongari BUS_DMASYNC_PREWRITE); 2999153982Syongari bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 3000153982Syongari BUS_DMASYNC_PREWRITE); 3001153982Syongari 3002153982Syongari frag = sc->ti_tx_saved_prodidx; 3003153982Syongari for (i = 0; i < nseg; i++) { 3004153396Sscottl if (sc->ti_hwrev == TI_HWREV_TIGON) { 3005153770Syongari bzero(&txdesc, sizeof(txdesc)); 3006153770Syongari f = &txdesc; 3007153396Sscottl } else 3008153396Sscottl f = &sc->ti_rdata->ti_tx_ring[frag]; 3009153982Syongari ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3010153982Syongari f->ti_len = txsegs[i].ds_len; 3011153396Sscottl f->ti_flags = csum_flags; 3012162375Sandre if (m->m_flags & M_VLANTAG) { 3013153396Sscottl f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3014162375Sandre f->ti_vlan_tag = m->m_pkthdr.ether_vtag & 0xfff; 3015153396Sscottl } else { 3016153396Sscottl f->ti_vlan_tag = 0; 3017153396Sscottl } 3018153396Sscottl 3019153770Syongari if (sc->ti_hwrev == TI_HWREV_TIGON) 3020153770Syongari ti_mem_write(sc, TI_TX_RING_BASE + frag * 3021153770Syongari sizeof(txdesc), sizeof(txdesc), &txdesc); 3022153396Sscottl TI_INC(frag, TI_TX_RING_CNT); 3023153396Sscottl } 3024153396Sscottl 3025153982Syongari sc->ti_tx_saved_prodidx = frag; 3026153982Syongari /* set TI_BDFLAG_END on the last descriptor */ 3027153982Syongari frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3028153770Syongari if (sc->ti_hwrev == TI_HWREV_TIGON) { 3029153770Syongari txdesc.ti_flags |= TI_BDFLAG_END; 3030153982Syongari ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3031153770Syongari sizeof(txdesc), &txdesc); 3032153770Syongari } else 3033153982Syongari sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3034153396Sscottl 3035153982Syongari STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3036153982Syongari STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3037153982Syongari txd->tx_m = m; 3038153982Syongari sc->ti_txcnt += nseg; 303945386Swpaul 3040131654Sbms return (0); 304145386Swpaul} 304245386Swpaul 3043153770Syongaristatic void 3044153770Syongariti_start(ifp) 3045153770Syongari struct ifnet *ifp; 3046153770Syongari{ 3047153770Syongari struct ti_softc *sc; 3048153770Syongari 3049153770Syongari sc = ifp->if_softc; 3050153770Syongari TI_LOCK(sc); 3051153770Syongari ti_start_locked(ifp); 3052153770Syongari TI_UNLOCK(sc); 3053153770Syongari} 3054153770Syongari 305545386Swpaul/* 305645386Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 305745386Swpaul * to the mbuf data regions directly in the transmit descriptors. 305845386Swpaul */ 3059102336Salfredstatic void 3060153770Syongariti_start_locked(ifp) 306145386Swpaul struct ifnet *ifp; 306245386Swpaul{ 306345386Swpaul struct ti_softc *sc; 306445386Swpaul struct mbuf *m_head = NULL; 3065153982Syongari int enq = 0; 306645386Swpaul 306745386Swpaul sc = ifp->if_softc; 306845386Swpaul 3069153982Syongari for (; ifp->if_snd.ifq_head != NULL && 3070153982Syongari sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 307145386Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 307245386Swpaul if (m_head == NULL) 307345386Swpaul break; 307445386Swpaul 307545386Swpaul /* 307658698Sjlemon * XXX 307758698Sjlemon * safety overkill. If this is a fragmented packet chain 307858698Sjlemon * with delayed TCP/UDP checksums, then only encapsulate 307958698Sjlemon * it if we have enough descriptors to handle the entire 308058698Sjlemon * chain at once. 308158698Sjlemon * (paranoia -- may not actually be needed) 308258698Sjlemon */ 308358698Sjlemon if (m_head->m_flags & M_FIRSTFRAG && 308458698Sjlemon m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 308558698Sjlemon if ((TI_TX_RING_CNT - sc->ti_txcnt) < 308658698Sjlemon m_head->m_pkthdr.csum_data + 16) { 308758698Sjlemon IF_PREPEND(&ifp->if_snd, m_head); 3088148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 308958698Sjlemon break; 309058698Sjlemon } 309158698Sjlemon } 309258698Sjlemon 309358698Sjlemon /* 309445386Swpaul * Pack the data into the transmit ring. If we 309545386Swpaul * don't have room, set the OACTIVE flag and wait 309645386Swpaul * for the NIC to drain the ring. 309745386Swpaul */ 3098153982Syongari if (ti_encap(sc, &m_head)) { 3099153982Syongari if (m_head == NULL) 3100153982Syongari break; 310145386Swpaul IF_PREPEND(&ifp->if_snd, m_head); 3102148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 310345386Swpaul break; 310445386Swpaul } 310545386Swpaul 3106153982Syongari enq++; 310745386Swpaul /* 310845386Swpaul * If there's a BPF listener, bounce a copy of this frame 310945386Swpaul * to him. 311045386Swpaul */ 3111167190Scsjp ETHER_BPF_MTAP(ifp, m_head); 311245386Swpaul } 311345386Swpaul 3114153982Syongari if (enq > 0) { 3115153982Syongari /* Transmit */ 3116153982Syongari CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 311745386Swpaul 3118153982Syongari /* 3119153982Syongari * Set a timeout in case the chip goes out to lunch. 3120153982Syongari */ 3121199559Sjhb sc->ti_timer = 5; 3122153982Syongari } 312345386Swpaul} 312445386Swpaul 3125102336Salfredstatic void 3126102336Salfredti_init(xsc) 312745386Swpaul void *xsc; 312845386Swpaul{ 3129153770Syongari struct ti_softc *sc; 3130153770Syongari 3131153770Syongari sc = xsc; 3132153770Syongari TI_LOCK(sc); 3133153770Syongari ti_init_locked(sc); 3134153770Syongari TI_UNLOCK(sc); 3135153770Syongari} 3136153770Syongari 3137153770Syongaristatic void 3138153770Syongariti_init_locked(xsc) 3139153770Syongari void *xsc; 3140153770Syongari{ 314145386Swpaul struct ti_softc *sc = xsc; 314245386Swpaul 314345386Swpaul /* Cancel pending I/O and flush buffers. */ 314445386Swpaul ti_stop(sc); 314545386Swpaul 314645386Swpaul /* Init the gen info block, ring control blocks and firmware. */ 314745386Swpaul if (ti_gibinit(sc)) { 3148162321Sglebius device_printf(sc->ti_dev, "initialization failure\n"); 314945386Swpaul return; 315045386Swpaul } 315145386Swpaul} 315245386Swpaul 315345386Swpaulstatic void ti_init2(sc) 315445386Swpaul struct ti_softc *sc; 315545386Swpaul{ 315645386Swpaul struct ti_cmd_desc cmd; 315745386Swpaul struct ifnet *ifp; 3158153770Syongari u_int8_t *ea; 315945386Swpaul struct ifmedia *ifm; 316045386Swpaul int tmp; 316145386Swpaul 3162153770Syongari TI_LOCK_ASSERT(sc); 3163153770Syongari 3164147256Sbrooks ifp = sc->ti_ifp; 316545386Swpaul 316645386Swpaul /* Specify MTU and interface index. */ 3167121816Sbrooks CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 316845386Swpaul CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3169118454Ssimokawa ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 317045386Swpaul TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 317145386Swpaul 317245386Swpaul /* Load our MAC address. */ 3173153770Syongari ea = IF_LLADDR(sc->ti_ifp); 3174153770Syongari CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3175153770Syongari CSR_WRITE_4(sc, TI_GCR_PAR1, 3176153770Syongari (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 317745386Swpaul TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 317845386Swpaul 317945386Swpaul /* Enable or disable promiscuous mode as needed. */ 318045386Swpaul if (ifp->if_flags & IFF_PROMISC) { 318145386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 318245386Swpaul } else { 318345386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 318445386Swpaul } 318545386Swpaul 318645386Swpaul /* Program multicast filter. */ 318745386Swpaul ti_setmulti(sc); 318845386Swpaul 318945386Swpaul /* 319045386Swpaul * If this is a Tigon 1, we should tell the 319145386Swpaul * firmware to use software packet filtering. 319245386Swpaul */ 319345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 319445386Swpaul TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 319545386Swpaul } 319645386Swpaul 319745386Swpaul /* Init RX ring. */ 319845386Swpaul ti_init_rx_ring_std(sc); 319945386Swpaul 320045386Swpaul /* Init jumbo RX ring. */ 320145386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 320245386Swpaul ti_init_rx_ring_jumbo(sc); 320345386Swpaul 320445386Swpaul /* 320545386Swpaul * If this is a Tigon 2, we can also configure the 320645386Swpaul * mini ring. 320745386Swpaul */ 320845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) 320945386Swpaul ti_init_rx_ring_mini(sc); 321045386Swpaul 321145386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 321245386Swpaul sc->ti_rx_saved_considx = 0; 321345386Swpaul 321445386Swpaul /* Init TX ring. */ 321545386Swpaul ti_init_tx_ring(sc); 321645386Swpaul 321745386Swpaul /* Tell firmware we're alive. */ 321845386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 321945386Swpaul 322045386Swpaul /* Enable host interrupts. */ 322145386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 322245386Swpaul 3223148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 3224148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3225199559Sjhb callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 322645386Swpaul 322745386Swpaul /* 322845386Swpaul * Make sure to set media properly. We have to do this 322945386Swpaul * here since we have to issue commands in order to set 323045386Swpaul * the link negotiation and we can't issue commands until 323145386Swpaul * the firmware is running. 323245386Swpaul */ 323345386Swpaul ifm = &sc->ifmedia; 323445386Swpaul tmp = ifm->ifm_media; 323545386Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 323645386Swpaul ti_ifmedia_upd(ifp); 323745386Swpaul ifm->ifm_media = tmp; 323845386Swpaul} 323945386Swpaul 324045386Swpaul/* 324145386Swpaul * Set media options. 324245386Swpaul */ 3243102336Salfredstatic int 3244102336Salfredti_ifmedia_upd(ifp) 324545386Swpaul struct ifnet *ifp; 324645386Swpaul{ 324745386Swpaul struct ti_softc *sc; 324845386Swpaul struct ifmedia *ifm; 324945386Swpaul struct ti_cmd_desc cmd; 325098849Sken u_int32_t flowctl; 325145386Swpaul 325245386Swpaul sc = ifp->if_softc; 325345386Swpaul ifm = &sc->ifmedia; 325445386Swpaul 325545386Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3256131654Sbms return (EINVAL); 325745386Swpaul 325898849Sken flowctl = 0; 325998849Sken 3260131654Sbms switch (IFM_SUBTYPE(ifm->ifm_media)) { 326145386Swpaul case IFM_AUTO: 326298849Sken /* 326398849Sken * Transmit flow control doesn't work on the Tigon 1. 326498849Sken */ 326598849Sken flowctl = TI_GLNK_RX_FLOWCTL_Y; 326698849Sken 326798849Sken /* 326898849Sken * Transmit flow control can also cause problems on the 326998849Sken * Tigon 2, apparantly with both the copper and fiber 327098849Sken * boards. The symptom is that the interface will just 327198849Sken * hang. This was reproduced with Alteon 180 switches. 327298849Sken */ 327398849Sken#if 0 327498849Sken if (sc->ti_hwrev != TI_HWREV_TIGON) 3275131652Sbms flowctl |= TI_GLNK_TX_FLOWCTL_Y; 327698849Sken#endif 327798849Sken 327845386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 327998849Sken TI_GLNK_FULL_DUPLEX| flowctl | 328045386Swpaul TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 328198849Sken 328298849Sken flowctl = TI_LNK_RX_FLOWCTL_Y; 328398849Sken#if 0 328498849Sken if (sc->ti_hwrev != TI_HWREV_TIGON) 328598849Sken flowctl |= TI_LNK_TX_FLOWCTL_Y; 328698849Sken#endif 328798849Sken 328845386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 328998849Sken TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 329045386Swpaul TI_LNK_AUTONEGENB|TI_LNK_ENB); 329145386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 329245386Swpaul TI_CMD_CODE_NEGOTIATE_BOTH, 0); 329345386Swpaul break; 329445386Swpaul case IFM_1000_SX: 329595673Sphk case IFM_1000_T: 329698849Sken flowctl = TI_GLNK_RX_FLOWCTL_Y; 329798849Sken#if 0 329898849Sken if (sc->ti_hwrev != TI_HWREV_TIGON) 3299131652Sbms flowctl |= TI_GLNK_TX_FLOWCTL_Y; 330098849Sken#endif 330198849Sken 330245386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 330398849Sken flowctl |TI_GLNK_ENB); 330445386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, 0); 330563699Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 330663699Swpaul TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 330763699Swpaul } 330845386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 330945386Swpaul TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 331045386Swpaul break; 331145386Swpaul case IFM_100_FX: 331245386Swpaul case IFM_10_FL: 331363699Swpaul case IFM_100_TX: 331463699Swpaul case IFM_10_T: 331598849Sken flowctl = TI_LNK_RX_FLOWCTL_Y; 331698849Sken#if 0 331798849Sken if (sc->ti_hwrev != TI_HWREV_TIGON) 331898849Sken flowctl |= TI_LNK_TX_FLOWCTL_Y; 331998849Sken#endif 332098849Sken 332145386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 332298849Sken CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 332363699Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 332463699Swpaul IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 332545386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 332645386Swpaul } else { 332745386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 332845386Swpaul } 332945386Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 333045386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 333145386Swpaul } else { 333245386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 333345386Swpaul } 333445386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 333545386Swpaul TI_CMD_CODE_NEGOTIATE_10_100, 0); 333645386Swpaul break; 333745386Swpaul } 333845386Swpaul 3339131654Sbms return (0); 334045386Swpaul} 334145386Swpaul 334245386Swpaul/* 334345386Swpaul * Report current media status. 334445386Swpaul */ 3345102336Salfredstatic void 3346102336Salfredti_ifmedia_sts(ifp, ifmr) 334745386Swpaul struct ifnet *ifp; 334845386Swpaul struct ifmediareq *ifmr; 334945386Swpaul{ 335045386Swpaul struct ti_softc *sc; 335163699Swpaul u_int32_t media = 0; 335245386Swpaul 335345386Swpaul sc = ifp->if_softc; 335445386Swpaul 335545386Swpaul ifmr->ifm_status = IFM_AVALID; 335645386Swpaul ifmr->ifm_active = IFM_ETHER; 335745386Swpaul 335845386Swpaul if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 335945386Swpaul return; 336045386Swpaul 336145386Swpaul ifmr->ifm_status |= IFM_ACTIVE; 336245386Swpaul 336363699Swpaul if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 336463699Swpaul media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 336563699Swpaul if (sc->ti_copper) 336695673Sphk ifmr->ifm_active |= IFM_1000_T; 336763699Swpaul else 336863699Swpaul ifmr->ifm_active |= IFM_1000_SX; 336963699Swpaul if (media & TI_GLNK_FULL_DUPLEX) 337063699Swpaul ifmr->ifm_active |= IFM_FDX; 337163699Swpaul else 337263699Swpaul ifmr->ifm_active |= IFM_HDX; 337363699Swpaul } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 337445386Swpaul media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 337563699Swpaul if (sc->ti_copper) { 337663699Swpaul if (media & TI_LNK_100MB) 337763699Swpaul ifmr->ifm_active |= IFM_100_TX; 337863699Swpaul if (media & TI_LNK_10MB) 337963699Swpaul ifmr->ifm_active |= IFM_10_T; 338063699Swpaul } else { 338163699Swpaul if (media & TI_LNK_100MB) 338263699Swpaul ifmr->ifm_active |= IFM_100_FX; 338363699Swpaul if (media & TI_LNK_10MB) 338463699Swpaul ifmr->ifm_active |= IFM_10_FL; 338563699Swpaul } 338645386Swpaul if (media & TI_LNK_FULL_DUPLEX) 338745386Swpaul ifmr->ifm_active |= IFM_FDX; 338845386Swpaul if (media & TI_LNK_HALF_DUPLEX) 338945386Swpaul ifmr->ifm_active |= IFM_HDX; 339045386Swpaul } 339145386Swpaul} 339245386Swpaul 3393102336Salfredstatic int 3394102336Salfredti_ioctl(ifp, command, data) 339545386Swpaul struct ifnet *ifp; 339645386Swpaul u_long command; 339745386Swpaul caddr_t data; 339845386Swpaul{ 339945386Swpaul struct ti_softc *sc = ifp->if_softc; 340045386Swpaul struct ifreq *ifr = (struct ifreq *) data; 340183630Sjlemon int mask, error = 0; 340245386Swpaul struct ti_cmd_desc cmd; 340345386Swpaul 3404131654Sbms switch (command) { 340545386Swpaul case SIOCSIFMTU: 3406153770Syongari TI_LOCK(sc); 340745386Swpaul if (ifr->ifr_mtu > TI_JUMBO_MTU) 340845386Swpaul error = EINVAL; 340945386Swpaul else { 341045386Swpaul ifp->if_mtu = ifr->ifr_mtu; 3411153770Syongari ti_init_locked(sc); 341245386Swpaul } 3413153770Syongari TI_UNLOCK(sc); 341445386Swpaul break; 341545386Swpaul case SIOCSIFFLAGS: 3416153770Syongari TI_LOCK(sc); 341745386Swpaul if (ifp->if_flags & IFF_UP) { 341845386Swpaul /* 341945386Swpaul * If only the state of the PROMISC flag changed, 342045386Swpaul * then just use the 'set promisc mode' command 342145386Swpaul * instead of reinitializing the entire NIC. Doing 342245386Swpaul * a full re-init means reloading the firmware and 342345386Swpaul * waiting for it to start up, which may take a 342445386Swpaul * second or two. 342545386Swpaul */ 3426148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 342745386Swpaul ifp->if_flags & IFF_PROMISC && 342845386Swpaul !(sc->ti_if_flags & IFF_PROMISC)) { 342945386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 343045386Swpaul TI_CMD_CODE_PROMISC_ENB, 0); 3431148887Srwatson } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 343245386Swpaul !(ifp->if_flags & IFF_PROMISC) && 343345386Swpaul sc->ti_if_flags & IFF_PROMISC) { 343445386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 343545386Swpaul TI_CMD_CODE_PROMISC_DIS, 0); 343645386Swpaul } else 3437153770Syongari ti_init_locked(sc); 343845386Swpaul } else { 3439148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 344045386Swpaul ti_stop(sc); 344145386Swpaul } 344245386Swpaul } 344345386Swpaul sc->ti_if_flags = ifp->if_flags; 3444153770Syongari TI_UNLOCK(sc); 344545386Swpaul break; 344645386Swpaul case SIOCADDMULTI: 344745386Swpaul case SIOCDELMULTI: 3448153770Syongari TI_LOCK(sc); 3449153770Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) 345045386Swpaul ti_setmulti(sc); 3451153770Syongari TI_UNLOCK(sc); 345245386Swpaul break; 345345386Swpaul case SIOCSIFMEDIA: 345445386Swpaul case SIOCGIFMEDIA: 345545386Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 345645386Swpaul break; 345783630Sjlemon case SIOCSIFCAP: 3458153770Syongari TI_LOCK(sc); 345983630Sjlemon mask = ifr->ifr_reqcap ^ ifp->if_capenable; 346083630Sjlemon if (mask & IFCAP_HWCSUM) { 346183630Sjlemon if (IFCAP_HWCSUM & ifp->if_capenable) 346283630Sjlemon ifp->if_capenable &= ~IFCAP_HWCSUM; 3463131655Sbms else 3464131655Sbms ifp->if_capenable |= IFCAP_HWCSUM; 3465148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3466153770Syongari ti_init_locked(sc); 3467131655Sbms } 3468153770Syongari TI_UNLOCK(sc); 346983630Sjlemon break; 347045386Swpaul default: 3471106936Ssam error = ether_ioctl(ifp, command, data); 347245386Swpaul break; 347345386Swpaul } 347445386Swpaul 3475131654Sbms return (error); 347645386Swpaul} 347745386Swpaul 347898849Skenstatic int 3479130585Sphkti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 348098849Sken{ 348198849Sken struct ti_softc *sc; 348298849Sken 3483120980Sphk sc = dev->si_drv1; 348498849Sken if (sc == NULL) 3485131654Sbms return (ENODEV); 348698849Sken 348798849Sken TI_LOCK(sc); 348898849Sken sc->ti_flags |= TI_FLAG_DEBUGING; 348998849Sken TI_UNLOCK(sc); 349098849Sken 3491131654Sbms return (0); 349298849Sken} 349398849Sken 349498849Skenstatic int 3495130585Sphkti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 349698849Sken{ 349798849Sken struct ti_softc *sc; 349898849Sken 3499120980Sphk sc = dev->si_drv1; 350098849Sken if (sc == NULL) 3501131654Sbms return (ENODEV); 350298849Sken 350398849Sken TI_LOCK(sc); 350498849Sken sc->ti_flags &= ~TI_FLAG_DEBUGING; 350598849Sken TI_UNLOCK(sc); 350698849Sken 3507131654Sbms return (0); 350898849Sken} 350998849Sken 351098849Sken/* 351198849Sken * This ioctl routine goes along with the Tigon character device. 351298849Sken */ 3513131652Sbmsstatic int 3514150719Sjhbti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3515150719Sjhb struct thread *td) 351698849Sken{ 3517120980Sphk int error; 351898849Sken struct ti_softc *sc; 351998849Sken 3520120980Sphk sc = dev->si_drv1; 352198849Sken if (sc == NULL) 3522131654Sbms return (ENODEV); 352398849Sken 352498849Sken error = 0; 352598849Sken 3526131654Sbms switch (cmd) { 352798849Sken case TIIOCGETSTATS: 352898849Sken { 352998849Sken struct ti_stats *outstats; 353098849Sken 353198849Sken outstats = (struct ti_stats *)addr; 353298849Sken 3533153281Sscottl TI_LOCK(sc); 353498849Sken bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 353598849Sken sizeof(struct ti_stats)); 3536153281Sscottl TI_UNLOCK(sc); 353798849Sken break; 353898849Sken } 353998849Sken case TIIOCGETPARAMS: 354098849Sken { 354198849Sken struct ti_params *params; 354298849Sken 354398849Sken params = (struct ti_params *)addr; 354498849Sken 3545153281Sscottl TI_LOCK(sc); 354698849Sken params->ti_stat_ticks = sc->ti_stat_ticks; 354798849Sken params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 354898849Sken params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 354998849Sken params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 355098849Sken params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 355198849Sken params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 355298849Sken params->param_mask = TI_PARAM_ALL; 3553153281Sscottl TI_UNLOCK(sc); 355498849Sken 355598849Sken error = 0; 355698849Sken 355798849Sken break; 355898849Sken } 355998849Sken case TIIOCSETPARAMS: 356098849Sken { 356198849Sken struct ti_params *params; 356298849Sken 356398849Sken params = (struct ti_params *)addr; 356498849Sken 3565153281Sscottl TI_LOCK(sc); 356698849Sken if (params->param_mask & TI_PARAM_STAT_TICKS) { 356798849Sken sc->ti_stat_ticks = params->ti_stat_ticks; 356898849Sken CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 356998849Sken } 357098849Sken 357198849Sken if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 357298849Sken sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 357398849Sken CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 357498849Sken sc->ti_rx_coal_ticks); 357598849Sken } 357698849Sken 357798849Sken if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 357898849Sken sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 357998849Sken CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 358098849Sken sc->ti_tx_coal_ticks); 358198849Sken } 358298849Sken 358398849Sken if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 358498849Sken sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 358598849Sken CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 358698849Sken sc->ti_rx_max_coal_bds); 358798849Sken } 358898849Sken 358998849Sken if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 359098849Sken sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 359198849Sken CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 359298849Sken sc->ti_tx_max_coal_bds); 359398849Sken } 359498849Sken 359598849Sken if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 359698849Sken sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 359798849Sken CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 359898849Sken sc->ti_tx_buf_ratio); 359998849Sken } 3600153281Sscottl TI_UNLOCK(sc); 360198849Sken 360298849Sken error = 0; 360398849Sken 360498849Sken break; 360598849Sken } 360698849Sken case TIIOCSETTRACE: { 360798849Sken ti_trace_type trace_type; 360898849Sken 360998849Sken trace_type = *(ti_trace_type *)addr; 361098849Sken 361198849Sken /* 361298849Sken * Set tracing to whatever the user asked for. Setting 361398849Sken * this register to 0 should have the effect of disabling 361498849Sken * tracing. 361598849Sken */ 361698849Sken CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 361798849Sken 361898849Sken error = 0; 361998849Sken 362098849Sken break; 362198849Sken } 362298849Sken case TIIOCGETTRACE: { 362398849Sken struct ti_trace_buf *trace_buf; 362498849Sken u_int32_t trace_start, cur_trace_ptr, trace_len; 362598849Sken 362698849Sken trace_buf = (struct ti_trace_buf *)addr; 362798849Sken 3628153281Sscottl TI_LOCK(sc); 362998849Sken trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 363098849Sken cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 363198849Sken trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 363298849Sken 363398849Sken#if 0 3634150719Sjhb if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3635150719Sjhb "trace_len = %d\n", trace_start, 363698849Sken cur_trace_ptr, trace_len); 3637150719Sjhb if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 363898849Sken trace_buf->buf_len); 363998849Sken#endif 364098849Sken 364198849Sken error = ti_copy_mem(sc, trace_start, min(trace_len, 364298849Sken trace_buf->buf_len), 364398849Sken (caddr_t)trace_buf->buf, 1, 1); 364498849Sken 364598849Sken if (error == 0) { 364698849Sken trace_buf->fill_len = min(trace_len, 364798849Sken trace_buf->buf_len); 364898849Sken if (cur_trace_ptr < trace_start) 364998849Sken trace_buf->cur_trace_ptr = 365098849Sken trace_start - cur_trace_ptr; 365198849Sken else 365298849Sken trace_buf->cur_trace_ptr = 365398849Sken cur_trace_ptr - trace_start; 365498849Sken } else 365598849Sken trace_buf->fill_len = 0; 3656153281Sscottl TI_UNLOCK(sc); 365798849Sken 365898849Sken break; 365998849Sken } 366098849Sken 366198849Sken /* 366298849Sken * For debugging, five ioctls are needed: 366398849Sken * ALT_ATTACH 366498849Sken * ALT_READ_TG_REG 366598849Sken * ALT_WRITE_TG_REG 366698849Sken * ALT_READ_TG_MEM 366798849Sken * ALT_WRITE_TG_MEM 366898849Sken */ 366998849Sken case ALT_ATTACH: 367098849Sken /* 3671131652Sbms * From what I can tell, Alteon's Solaris Tigon driver 367298849Sken * only has one character device, so you have to attach 367398849Sken * to the Tigon board you're interested in. This seems 367498849Sken * like a not-so-good way to do things, since unless you 367598849Sken * subsequently specify the unit number of the device 3676177626Sbrueffer * you're interested in every ioctl, you'll only be 367798849Sken * able to debug one board at a time. 367898849Sken */ 367998849Sken error = 0; 368098849Sken break; 368198849Sken case ALT_READ_TG_MEM: 368298849Sken case ALT_WRITE_TG_MEM: 368398849Sken { 368498849Sken struct tg_mem *mem_param; 368598849Sken u_int32_t sram_end, scratch_end; 368698849Sken 368798849Sken mem_param = (struct tg_mem *)addr; 368898849Sken 368998849Sken if (sc->ti_hwrev == TI_HWREV_TIGON) { 369098849Sken sram_end = TI_END_SRAM_I; 369198849Sken scratch_end = TI_END_SCRATCH_I; 369298849Sken } else { 369398849Sken sram_end = TI_END_SRAM_II; 369498849Sken scratch_end = TI_END_SCRATCH_II; 369598849Sken } 369698849Sken 369798849Sken /* 369898849Sken * For now, we'll only handle accessing regular SRAM, 369998849Sken * nothing else. 370098849Sken */ 3701153281Sscottl TI_LOCK(sc); 370298849Sken if ((mem_param->tgAddr >= TI_BEG_SRAM) 370398849Sken && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 370498849Sken /* 370598849Sken * In this instance, we always copy to/from user 370698849Sken * space, so the user space argument is set to 1. 370798849Sken */ 370898849Sken error = ti_copy_mem(sc, mem_param->tgAddr, 370998849Sken mem_param->len, 371098849Sken mem_param->userAddr, 1, 371198849Sken (cmd == ALT_READ_TG_MEM) ? 1 : 0); 371298849Sken } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 371398849Sken && (mem_param->tgAddr <= scratch_end)) { 371498849Sken error = ti_copy_scratch(sc, mem_param->tgAddr, 371598849Sken mem_param->len, 371698849Sken mem_param->userAddr, 1, 371798849Sken (cmd == ALT_READ_TG_MEM) ? 371898849Sken 1 : 0, TI_PROCESSOR_A); 371998849Sken } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 372098849Sken && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 372198849Sken if (sc->ti_hwrev == TI_HWREV_TIGON) { 3722150719Sjhb if_printf(sc->ti_ifp, 3723150719Sjhb "invalid memory range for Tigon I\n"); 372498849Sken error = EINVAL; 372598849Sken break; 372698849Sken } 3727131652Sbms error = ti_copy_scratch(sc, mem_param->tgAddr - 372898849Sken TI_SCRATCH_DEBUG_OFF, 372998849Sken mem_param->len, 373098849Sken mem_param->userAddr, 1, 373198849Sken (cmd == ALT_READ_TG_MEM) ? 373298849Sken 1 : 0, TI_PROCESSOR_B); 373398849Sken } else { 3734150719Sjhb if_printf(sc->ti_ifp, "memory address %#x len %d is " 3735150719Sjhb "out of supported range\n", 373698849Sken mem_param->tgAddr, mem_param->len); 373798849Sken error = EINVAL; 373898849Sken } 3739153281Sscottl TI_UNLOCK(sc); 374098849Sken 374198849Sken break; 374298849Sken } 374398849Sken case ALT_READ_TG_REG: 374498849Sken case ALT_WRITE_TG_REG: 374598849Sken { 374698849Sken struct tg_reg *regs; 374798849Sken u_int32_t tmpval; 374898849Sken 374998849Sken regs = (struct tg_reg *)addr; 375098849Sken 375198849Sken /* 375298849Sken * Make sure the address in question isn't out of range. 375398849Sken */ 375498849Sken if (regs->addr > TI_REG_MAX) { 375598849Sken error = EINVAL; 375698849Sken break; 375798849Sken } 3758153281Sscottl TI_LOCK(sc); 375998849Sken if (cmd == ALT_READ_TG_REG) { 376098849Sken bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 376198849Sken regs->addr, &tmpval, 1); 376298849Sken regs->data = ntohl(tmpval); 376398849Sken#if 0 376498849Sken if ((regs->addr == TI_CPU_STATE) 376598849Sken || (regs->addr == TI_CPU_CTL_B)) { 3766150719Sjhb if_printf(sc->ti_ifp, "register %#x = %#x\n", 3767150719Sjhb regs->addr, tmpval); 376898849Sken } 376998849Sken#endif 377098849Sken } else { 377198849Sken tmpval = htonl(regs->data); 377298849Sken bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 377398849Sken regs->addr, &tmpval, 1); 377498849Sken } 3775153281Sscottl TI_UNLOCK(sc); 377698849Sken 377798849Sken break; 377898849Sken } 377998849Sken default: 378098849Sken error = ENOTTY; 378198849Sken break; 378298849Sken } 3783131654Sbms return (error); 378498849Sken} 378598849Sken 3786102336Salfredstatic void 3787199559Sjhbti_watchdog(void *arg) 378845386Swpaul{ 378945386Swpaul struct ti_softc *sc; 3790199559Sjhb struct ifnet *ifp; 379145386Swpaul 3792199559Sjhb sc = arg; 3793199559Sjhb TI_LOCK_ASSERT(sc); 3794199559Sjhb callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3795199559Sjhb if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3796199559Sjhb return; 379745386Swpaul 379898849Sken /* 379998849Sken * When we're debugging, the chip is often stopped for long periods 380098849Sken * of time, and that would normally cause the watchdog timer to fire. 380198849Sken * Since that impedes debugging, we don't want to do that. 380298849Sken */ 3803199559Sjhb if (sc->ti_flags & TI_FLAG_DEBUGING) 380498849Sken return; 380598849Sken 3806199559Sjhb ifp = sc->ti_ifp; 3807150719Sjhb if_printf(ifp, "watchdog timeout -- resetting\n"); 380845386Swpaul ti_stop(sc); 3809153770Syongari ti_init_locked(sc); 381045386Swpaul 381145386Swpaul ifp->if_oerrors++; 381245386Swpaul} 381345386Swpaul 381445386Swpaul/* 381545386Swpaul * Stop the adapter and free any mbufs allocated to the 381645386Swpaul * RX and TX lists. 381745386Swpaul */ 3818102336Salfredstatic void 3819102336Salfredti_stop(sc) 382045386Swpaul struct ti_softc *sc; 382145386Swpaul{ 382245386Swpaul struct ifnet *ifp; 382345386Swpaul struct ti_cmd_desc cmd; 382445386Swpaul 3825153770Syongari TI_LOCK_ASSERT(sc); 382667087Swpaul 3827147256Sbrooks ifp = sc->ti_ifp; 382845386Swpaul 382945386Swpaul /* Disable host interrupts. */ 383045386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 383145386Swpaul /* 383245386Swpaul * Tell firmware we're shutting down. 383345386Swpaul */ 383445386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 383545386Swpaul 383645386Swpaul /* Halt and reinitialize. */ 3837153770Syongari if (ti_chipinit(sc) != 0) 3838153770Syongari return; 3839153770Syongari ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3840153770Syongari if (ti_chipinit(sc) != 0) 3841153770Syongari return; 384245386Swpaul 384345386Swpaul /* Free the RX lists. */ 384445386Swpaul ti_free_rx_ring_std(sc); 384545386Swpaul 384645386Swpaul /* Free jumbo RX list. */ 384745386Swpaul ti_free_rx_ring_jumbo(sc); 384845386Swpaul 384945386Swpaul /* Free mini RX list. */ 385045386Swpaul ti_free_rx_ring_mini(sc); 385145386Swpaul 385245386Swpaul /* Free TX buffers. */ 385345386Swpaul ti_free_tx_ring(sc); 385445386Swpaul 385545386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 385645386Swpaul sc->ti_return_prodidx.ti_idx = 0; 385745386Swpaul sc->ti_tx_considx.ti_idx = 0; 385845386Swpaul sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 385945386Swpaul 3860148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3861199559Sjhb callout_stop(&sc->ti_watchdog); 386245386Swpaul} 386345386Swpaul 386445386Swpaul/* 386545386Swpaul * Stop all chip I/O so that the kernel's probe routines don't 386645386Swpaul * get confused by errant DMAs when rebooting. 386745386Swpaul */ 3868173839Syongaristatic int 3869102336Salfredti_shutdown(dev) 387049011Swpaul device_t dev; 387145386Swpaul{ 387245386Swpaul struct ti_softc *sc; 387345386Swpaul 387449011Swpaul sc = device_get_softc(dev); 387567087Swpaul TI_LOCK(sc); 387645386Swpaul ti_chipinit(sc); 387767087Swpaul TI_UNLOCK(sc); 3878173839Syongari 3879173839Syongari return (0); 388045386Swpaul} 3881