if_ti.c revision 219547
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 219547 2011-03-11 22:32:17Z marius $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94#include <sys/sf_buf.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103 104#include <net/bpf.h> 105 106#include <netinet/in_systm.h> 107#include <netinet/in.h> 108#include <netinet/ip.h> 109 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115/* #define TI_PRIVATE_JUMBOS */ 116#ifndef TI_PRIVATE_JUMBOS 117#include <vm/vm.h> 118#include <vm/vm_page.h> 119#endif 120 121#include <dev/pci/pcireg.h> 122#include <dev/pci/pcivar.h> 123 124#include <sys/tiio.h> 125#include <dev/ti/if_tireg.h> 126#include <dev/ti/ti_fw.h> 127#include <dev/ti/ti_fw2.h> 128 129#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 130/* 131 * We can only turn on header splitting if we're using extended receive 132 * BDs. 133 */ 134#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 135#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 136#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 137 138typedef enum { 139 TI_SWAP_HTON, 140 TI_SWAP_NTOH 141} ti_swap_type; 142 143 144/* 145 * Various supported device vendors/types and their names. 146 */ 147 148static const struct ti_type const ti_devs[] = { 149 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 152 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 153 { TC_VENDORID, TC_DEVICEID_3C985, 154 "3Com 3c985-SX Gigabit Ethernet" }, 155 { NG_VENDORID, NG_DEVICEID_GA620, 156 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 157 { NG_VENDORID, NG_DEVICEID_GA620T, 158 "Netgear GA620 1000baseT Gigabit Ethernet" }, 159 { SGI_VENDORID, SGI_DEVICEID_TIGON, 160 "Silicon Graphics Gigabit Ethernet" }, 161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 162 "Farallon PN9000SX Gigabit Ethernet" }, 163 { 0, 0, NULL } 164}; 165 166 167static d_open_t ti_open; 168static d_close_t ti_close; 169static d_ioctl_t ti_ioctl2; 170 171static struct cdevsw ti_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = ti_open, 175 .d_close = ti_close, 176 .d_ioctl = ti_ioctl2, 177 .d_name = "ti", 178}; 179 180static int ti_probe(device_t); 181static int ti_attach(device_t); 182static int ti_detach(device_t); 183static void ti_txeof(struct ti_softc *); 184static void ti_rxeof(struct ti_softc *); 185 186static void ti_stats_update(struct ti_softc *); 187static int ti_encap(struct ti_softc *, struct mbuf **); 188 189static void ti_intr(void *); 190static void ti_start(struct ifnet *); 191static void ti_start_locked(struct ifnet *); 192static int ti_ioctl(struct ifnet *, u_long, caddr_t); 193static void ti_init(void *); 194static void ti_init_locked(void *); 195static void ti_init2(struct ti_softc *); 196static void ti_stop(struct ti_softc *); 197static void ti_watchdog(void *); 198static int ti_shutdown(device_t); 199static int ti_ifmedia_upd(struct ifnet *); 200static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 201 202static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 203static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 204static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 205 206static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 207static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 208static void ti_setmulti(struct ti_softc *); 209 210static void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *); 211static void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, void *); 212static void ti_mem_zero(struct ti_softc *, u_int32_t, u_int32_t); 213static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int); 214static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, 215 int, int, int); 216static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 217static void ti_loadfw(struct ti_softc *); 218static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 219static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 220static void ti_handle_events(struct ti_softc *); 221static int ti_alloc_dmamaps(struct ti_softc *); 222static void ti_free_dmamaps(struct ti_softc *); 223static int ti_alloc_jumbo_mem(struct ti_softc *); 224#ifdef TI_PRIVATE_JUMBOS 225static void *ti_jalloc(struct ti_softc *); 226static void ti_jfree(void *, void *); 227#endif /* TI_PRIVATE_JUMBOS */ 228static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 229static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 230static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 231static int ti_init_rx_ring_std(struct ti_softc *); 232static void ti_free_rx_ring_std(struct ti_softc *); 233static int ti_init_rx_ring_jumbo(struct ti_softc *); 234static void ti_free_rx_ring_jumbo(struct ti_softc *); 235static int ti_init_rx_ring_mini(struct ti_softc *); 236static void ti_free_rx_ring_mini(struct ti_softc *); 237static void ti_free_tx_ring(struct ti_softc *); 238static int ti_init_tx_ring(struct ti_softc *); 239 240static int ti_64bitslot_war(struct ti_softc *); 241static int ti_chipinit(struct ti_softc *); 242static int ti_gibinit(struct ti_softc *); 243 244#ifdef TI_JUMBO_HDRSPLIT 245static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 246 int pkt_len, int idx); 247#endif /* TI_JUMBO_HDRSPLIT */ 248 249static device_method_t ti_methods[] = { 250 /* Device interface */ 251 DEVMETHOD(device_probe, ti_probe), 252 DEVMETHOD(device_attach, ti_attach), 253 DEVMETHOD(device_detach, ti_detach), 254 DEVMETHOD(device_shutdown, ti_shutdown), 255 { 0, 0 } 256}; 257 258static driver_t ti_driver = { 259 "ti", 260 ti_methods, 261 sizeof(struct ti_softc) 262}; 263 264static devclass_t ti_devclass; 265 266DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 267MODULE_DEPEND(ti, pci, 1, 1, 1); 268MODULE_DEPEND(ti, ether, 1, 1, 1); 269 270/* 271 * Send an instruction or address to the EEPROM, check for ACK. 272 */ 273static u_int32_t ti_eeprom_putbyte(sc, byte) 274 struct ti_softc *sc; 275 int byte; 276{ 277 int i, ack = 0; 278 279 /* 280 * Make sure we're in TX mode. 281 */ 282 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 283 284 /* 285 * Feed in each bit and stobe the clock. 286 */ 287 for (i = 0x80; i; i >>= 1) { 288 if (byte & i) { 289 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 290 } else { 291 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 292 } 293 DELAY(1); 294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 295 DELAY(1); 296 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 297 } 298 299 /* 300 * Turn off TX mode. 301 */ 302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 303 304 /* 305 * Check for ack. 306 */ 307 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 308 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 311 return (ack); 312} 313 314/* 315 * Read a byte of data stored in the EEPROM at address 'addr.' 316 * We have to send two address bytes since the EEPROM can hold 317 * more than 256 bytes of data. 318 */ 319static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 320 struct ti_softc *sc; 321 int addr; 322 u_int8_t *dest; 323{ 324 int i; 325 u_int8_t byte = 0; 326 327 EEPROM_START; 328 329 /* 330 * Send write control code to EEPROM. 331 */ 332 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 333 device_printf(sc->ti_dev, 334 "failed to send write command, status: %x\n", 335 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 336 return (1); 337 } 338 339 /* 340 * Send first byte of address of byte we want to read. 341 */ 342 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 343 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 344 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 345 return (1); 346 } 347 /* 348 * Send second byte address of byte we want to read. 349 */ 350 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 351 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 352 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 353 return (1); 354 } 355 356 EEPROM_STOP; 357 EEPROM_START; 358 /* 359 * Send read control code to EEPROM. 360 */ 361 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 362 device_printf(sc->ti_dev, 363 "failed to send read command, status: %x\n", 364 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 365 return (1); 366 } 367 368 /* 369 * Start reading bits from EEPROM. 370 */ 371 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 372 for (i = 0x80; i; i >>= 1) { 373 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 374 DELAY(1); 375 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 376 byte |= i; 377 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 378 DELAY(1); 379 } 380 381 EEPROM_STOP; 382 383 /* 384 * No ACK generated for read, so just return byte. 385 */ 386 387 *dest = byte; 388 389 return (0); 390} 391 392/* 393 * Read a sequence of bytes from the EEPROM. 394 */ 395static int 396ti_read_eeprom(sc, dest, off, cnt) 397 struct ti_softc *sc; 398 caddr_t dest; 399 int off; 400 int cnt; 401{ 402 int err = 0, i; 403 u_int8_t byte = 0; 404 405 for (i = 0; i < cnt; i++) { 406 err = ti_eeprom_getbyte(sc, off + i, &byte); 407 if (err) 408 break; 409 *(dest + i) = byte; 410 } 411 412 return (err ? 1 : 0); 413} 414 415/* 416 * NIC memory read function. 417 * Can be used to copy data from NIC local memory. 418 */ 419static void 420ti_mem_read(sc, addr, len, buf) 421 struct ti_softc *sc; 422 u_int32_t addr, len; 423 void *buf; 424{ 425 int segptr, segsize, cnt; 426 char *ptr; 427 428 segptr = addr; 429 cnt = len; 430 ptr = buf; 431 432 while (cnt) { 433 if (cnt < TI_WINLEN) 434 segsize = cnt; 435 else 436 segsize = TI_WINLEN - (segptr % TI_WINLEN); 437 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 438 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 439 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 440 segsize / 4); 441 ptr += segsize; 442 segptr += segsize; 443 cnt -= segsize; 444 } 445} 446 447 448/* 449 * NIC memory write function. 450 * Can be used to copy data into NIC local memory. 451 */ 452static void 453ti_mem_write(sc, addr, len, buf) 454 struct ti_softc *sc; 455 u_int32_t addr, len; 456 void *buf; 457{ 458 int segptr, segsize, cnt; 459 char *ptr; 460 461 segptr = addr; 462 cnt = len; 463 ptr = buf; 464 465 while (cnt) { 466 if (cnt < TI_WINLEN) 467 segsize = cnt; 468 else 469 segsize = TI_WINLEN - (segptr % TI_WINLEN); 470 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 471 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 472 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 473 segsize / 4); 474 ptr += segsize; 475 segptr += segsize; 476 cnt -= segsize; 477 } 478} 479 480/* 481 * NIC memory read function. 482 * Can be used to clear a section of NIC local memory. 483 */ 484static void 485ti_mem_zero(sc, addr, len) 486 struct ti_softc *sc; 487 u_int32_t addr, len; 488{ 489 int segptr, segsize, cnt; 490 491 segptr = addr; 492 cnt = len; 493 494 while (cnt) { 495 if (cnt < TI_WINLEN) 496 segsize = cnt; 497 else 498 segsize = TI_WINLEN - (segptr % TI_WINLEN); 499 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 500 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 501 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 502 segptr += segsize; 503 cnt -= segsize; 504 } 505} 506 507static int 508ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 509 struct ti_softc *sc; 510 u_int32_t tigon_addr, len; 511 caddr_t buf; 512 int useraddr, readdata; 513{ 514 int segptr, segsize, cnt; 515 caddr_t ptr; 516 u_int32_t origwin; 517 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 518 int resid, segresid; 519 int first_pass; 520 521 TI_LOCK_ASSERT(sc); 522 523 /* 524 * At the moment, we don't handle non-aligned cases, we just bail. 525 * If this proves to be a problem, it will be fixed. 526 */ 527 if ((readdata == 0) 528 && (tigon_addr & 0x3)) { 529 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 530 "word-aligned\n", __func__, tigon_addr); 531 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 532 "yet supported\n", __func__); 533 return (EINVAL); 534 } 535 536 segptr = tigon_addr & ~0x3; 537 segresid = tigon_addr - segptr; 538 539 /* 540 * This is the non-aligned amount left over that we'll need to 541 * copy. 542 */ 543 resid = len & 0x3; 544 545 /* Add in the left over amount at the front of the buffer */ 546 resid += segresid; 547 548 cnt = len & ~0x3; 549 /* 550 * If resid + segresid is >= 4, add multiples of 4 to the count and 551 * decrease the residual by that much. 552 */ 553 cnt += resid & ~0x3; 554 resid -= resid & ~0x3; 555 556 ptr = buf; 557 558 first_pass = 1; 559 560 /* 561 * Save the old window base value. 562 */ 563 origwin = CSR_READ_4(sc, TI_WINBASE); 564 565 while (cnt) { 566 bus_size_t ti_offset; 567 568 if (cnt < TI_WINLEN) 569 segsize = cnt; 570 else 571 segsize = TI_WINLEN - (segptr % TI_WINLEN); 572 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 573 574 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 575 576 if (readdata) { 577 578 bus_space_read_region_4(sc->ti_btag, 579 sc->ti_bhandle, ti_offset, 580 (u_int32_t *)tmparray, 581 segsize >> 2); 582 if (useraddr) { 583 /* 584 * Yeah, this is a little on the kludgy 585 * side, but at least this code is only 586 * used for debugging. 587 */ 588 ti_bcopy_swap(tmparray, tmparray2, segsize, 589 TI_SWAP_NTOH); 590 591 TI_UNLOCK(sc); 592 if (first_pass) { 593 copyout(&tmparray2[segresid], ptr, 594 segsize - segresid); 595 first_pass = 0; 596 } else 597 copyout(tmparray2, ptr, segsize); 598 TI_LOCK(sc); 599 } else { 600 if (first_pass) { 601 602 ti_bcopy_swap(tmparray, tmparray2, 603 segsize, TI_SWAP_NTOH); 604 TI_UNLOCK(sc); 605 bcopy(&tmparray2[segresid], ptr, 606 segsize - segresid); 607 TI_LOCK(sc); 608 first_pass = 0; 609 } else 610 ti_bcopy_swap(tmparray, ptr, segsize, 611 TI_SWAP_NTOH); 612 } 613 614 } else { 615 if (useraddr) { 616 TI_UNLOCK(sc); 617 copyin(ptr, tmparray2, segsize); 618 TI_LOCK(sc); 619 ti_bcopy_swap(tmparray2, tmparray, segsize, 620 TI_SWAP_HTON); 621 } else 622 ti_bcopy_swap(ptr, tmparray, segsize, 623 TI_SWAP_HTON); 624 625 bus_space_write_region_4(sc->ti_btag, 626 sc->ti_bhandle, ti_offset, 627 (u_int32_t *)tmparray, 628 segsize >> 2); 629 } 630 segptr += segsize; 631 ptr += segsize; 632 cnt -= segsize; 633 } 634 635 /* 636 * Handle leftover, non-word-aligned bytes. 637 */ 638 if (resid != 0) { 639 u_int32_t tmpval, tmpval2; 640 bus_size_t ti_offset; 641 642 /* 643 * Set the segment pointer. 644 */ 645 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 646 647 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 648 649 /* 650 * First, grab whatever is in our source/destination. 651 * We'll obviously need this for reads, but also for 652 * writes, since we'll be doing read/modify/write. 653 */ 654 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 655 ti_offset, &tmpval, 1); 656 657 /* 658 * Next, translate this from little-endian to big-endian 659 * (at least on i386 boxes). 660 */ 661 tmpval2 = ntohl(tmpval); 662 663 if (readdata) { 664 /* 665 * If we're reading, just copy the leftover number 666 * of bytes from the host byte order buffer to 667 * the user's buffer. 668 */ 669 if (useraddr) { 670 TI_UNLOCK(sc); 671 copyout(&tmpval2, ptr, resid); 672 TI_LOCK(sc); 673 } else 674 bcopy(&tmpval2, ptr, resid); 675 } else { 676 /* 677 * If we're writing, first copy the bytes to be 678 * written into the network byte order buffer, 679 * leaving the rest of the buffer with whatever was 680 * originally in there. Then, swap the bytes 681 * around into host order and write them out. 682 * 683 * XXX KDM the read side of this has been verified 684 * to work, but the write side of it has not been 685 * verified. So user beware. 686 */ 687 if (useraddr) { 688 TI_UNLOCK(sc); 689 copyin(ptr, &tmpval2, resid); 690 TI_LOCK(sc); 691 } else 692 bcopy(ptr, &tmpval2, resid); 693 694 tmpval = htonl(tmpval2); 695 696 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 697 ti_offset, &tmpval, 1); 698 } 699 } 700 701 CSR_WRITE_4(sc, TI_WINBASE, origwin); 702 703 return (0); 704} 705 706static int 707ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 708 struct ti_softc *sc; 709 u_int32_t tigon_addr, len; 710 caddr_t buf; 711 int useraddr, readdata; 712 int cpu; 713{ 714 u_int32_t segptr; 715 int cnt; 716 u_int32_t tmpval, tmpval2; 717 caddr_t ptr; 718 719 TI_LOCK_ASSERT(sc); 720 721 /* 722 * At the moment, we don't handle non-aligned cases, we just bail. 723 * If this proves to be a problem, it will be fixed. 724 */ 725 if (tigon_addr & 0x3) { 726 device_printf(sc->ti_dev, "%s: tigon address %#x " 727 "isn't word-aligned\n", __func__, tigon_addr); 728 return (EINVAL); 729 } 730 731 if (len & 0x3) { 732 device_printf(sc->ti_dev, "%s: transfer length %d " 733 "isn't word-aligned\n", __func__, len); 734 return (EINVAL); 735 } 736 737 segptr = tigon_addr; 738 cnt = len; 739 ptr = buf; 740 741 while (cnt) { 742 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 743 744 if (readdata) { 745 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 746 747 tmpval = ntohl(tmpval2); 748 749 /* 750 * Note: I've used this debugging interface 751 * extensively with Alteon's 12.3.15 firmware, 752 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 753 * 754 * When you compile the firmware without 755 * optimization, which is necessary sometimes in 756 * order to properly step through it, you sometimes 757 * read out a bogus value of 0xc0017c instead of 758 * whatever was supposed to be in that scratchpad 759 * location. That value is on the stack somewhere, 760 * but I've never been able to figure out what was 761 * causing the problem. 762 * 763 * The address seems to pop up in random places, 764 * often not in the same place on two subsequent 765 * reads. 766 * 767 * In any case, the underlying data doesn't seem 768 * to be affected, just the value read out. 769 * 770 * KDM, 3/7/2000 771 */ 772 773 if (tmpval2 == 0xc0017c) 774 device_printf(sc->ti_dev, "found 0xc0017c at " 775 "%#x (tmpval2)\n", segptr); 776 777 if (tmpval == 0xc0017c) 778 device_printf(sc->ti_dev, "found 0xc0017c at " 779 "%#x (tmpval)\n", segptr); 780 781 if (useraddr) 782 copyout(&tmpval, ptr, 4); 783 else 784 bcopy(&tmpval, ptr, 4); 785 } else { 786 if (useraddr) 787 copyin(ptr, &tmpval2, 4); 788 else 789 bcopy(ptr, &tmpval2, 4); 790 791 tmpval = htonl(tmpval2); 792 793 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 794 } 795 796 cnt -= 4; 797 segptr += 4; 798 ptr += 4; 799 } 800 801 return (0); 802} 803 804static int 805ti_bcopy_swap(src, dst, len, swap_type) 806 const void *src; 807 void *dst; 808 size_t len; 809 ti_swap_type swap_type; 810{ 811 const u_int8_t *tmpsrc; 812 u_int8_t *tmpdst; 813 size_t tmplen; 814 815 if (len & 0x3) { 816 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 817 len); 818 return (-1); 819 } 820 821 tmpsrc = src; 822 tmpdst = dst; 823 tmplen = len; 824 825 while (tmplen) { 826 if (swap_type == TI_SWAP_NTOH) 827 *(u_int32_t *)tmpdst = 828 ntohl(*(const u_int32_t *)tmpsrc); 829 else 830 *(u_int32_t *)tmpdst = 831 htonl(*(const u_int32_t *)tmpsrc); 832 833 tmpsrc += 4; 834 tmpdst += 4; 835 tmplen -= 4; 836 } 837 838 return (0); 839} 840 841/* 842 * Load firmware image into the NIC. Check that the firmware revision 843 * is acceptable and see if we want the firmware for the Tigon 1 or 844 * Tigon 2. 845 */ 846static void 847ti_loadfw(sc) 848 struct ti_softc *sc; 849{ 850 851 TI_LOCK_ASSERT(sc); 852 853 switch (sc->ti_hwrev) { 854 case TI_HWREV_TIGON: 855 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 856 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 857 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 858 device_printf(sc->ti_dev, "firmware revision mismatch; " 859 "want %d.%d.%d, got %d.%d.%d\n", 860 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 861 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 862 tigonFwReleaseMinor, tigonFwReleaseFix); 863 return; 864 } 865 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 866 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 867 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 868 tigonFwRodata); 869 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 870 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 871 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 872 break; 873 case TI_HWREV_TIGON_II: 874 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 875 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 876 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 877 device_printf(sc->ti_dev, "firmware revision mismatch; " 878 "want %d.%d.%d, got %d.%d.%d\n", 879 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 880 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 881 tigon2FwReleaseMinor, tigon2FwReleaseFix); 882 return; 883 } 884 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 885 tigon2FwText); 886 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 887 tigon2FwData); 888 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 889 tigon2FwRodata); 890 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 891 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 892 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 893 break; 894 default: 895 device_printf(sc->ti_dev, 896 "can't load firmware: unknown hardware rev\n"); 897 break; 898 } 899} 900 901/* 902 * Send the NIC a command via the command ring. 903 */ 904static void 905ti_cmd(sc, cmd) 906 struct ti_softc *sc; 907 struct ti_cmd_desc *cmd; 908{ 909 int index; 910 911 index = sc->ti_cmd_saved_prodidx; 912 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 913 TI_INC(index, TI_CMD_RING_CNT); 914 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 915 sc->ti_cmd_saved_prodidx = index; 916} 917 918/* 919 * Send the NIC an extended command. The 'len' parameter specifies the 920 * number of command slots to include after the initial command. 921 */ 922static void 923ti_cmd_ext(sc, cmd, arg, len) 924 struct ti_softc *sc; 925 struct ti_cmd_desc *cmd; 926 caddr_t arg; 927 int len; 928{ 929 int index; 930 int i; 931 932 index = sc->ti_cmd_saved_prodidx; 933 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 934 TI_INC(index, TI_CMD_RING_CNT); 935 for (i = 0; i < len; i++) { 936 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 937 *(u_int32_t *)(&arg[i * 4])); 938 TI_INC(index, TI_CMD_RING_CNT); 939 } 940 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 941 sc->ti_cmd_saved_prodidx = index; 942} 943 944/* 945 * Handle events that have triggered interrupts. 946 */ 947static void 948ti_handle_events(sc) 949 struct ti_softc *sc; 950{ 951 struct ti_event_desc *e; 952 953 if (sc->ti_rdata->ti_event_ring == NULL) 954 return; 955 956 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 957 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 958 switch (TI_EVENT_EVENT(e)) { 959 case TI_EV_LINKSTAT_CHANGED: 960 sc->ti_linkstat = TI_EVENT_CODE(e); 961 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 962 device_printf(sc->ti_dev, "10/100 link up\n"); 963 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 964 device_printf(sc->ti_dev, "gigabit link up\n"); 965 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 966 device_printf(sc->ti_dev, "link down\n"); 967 break; 968 case TI_EV_ERROR: 969 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 970 device_printf(sc->ti_dev, "invalid command\n"); 971 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 972 device_printf(sc->ti_dev, "unknown command\n"); 973 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 974 device_printf(sc->ti_dev, "bad config data\n"); 975 break; 976 case TI_EV_FIRMWARE_UP: 977 ti_init2(sc); 978 break; 979 case TI_EV_STATS_UPDATED: 980 ti_stats_update(sc); 981 break; 982 case TI_EV_RESET_JUMBO_RING: 983 case TI_EV_MCAST_UPDATED: 984 /* Who cares. */ 985 break; 986 default: 987 device_printf(sc->ti_dev, "unknown event: %d\n", 988 TI_EVENT_EVENT(e)); 989 break; 990 } 991 /* Advance the consumer index. */ 992 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 993 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 994 } 995} 996 997static int 998ti_alloc_dmamaps(struct ti_softc *sc) 999{ 1000 int i; 1001 1002 for (i = 0; i < TI_TX_RING_CNT; i++) { 1003 sc->ti_cdata.ti_txdesc[i].tx_m = NULL; 1004 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1005 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0, 1006 &sc->ti_cdata.ti_txdesc[i].tx_dmamap)) 1007 return (ENOBUFS); 1008 } 1009 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1010 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1011 &sc->ti_cdata.ti_rx_std_maps[i])) 1012 return (ENOBUFS); 1013 } 1014 1015 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1016 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 1017 &sc->ti_cdata.ti_rx_jumbo_maps[i])) 1018 return (ENOBUFS); 1019 } 1020 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1021 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1022 &sc->ti_cdata.ti_rx_mini_maps[i])) 1023 return (ENOBUFS); 1024 } 1025 1026 return (0); 1027} 1028 1029static void 1030ti_free_dmamaps(struct ti_softc *sc) 1031{ 1032 int i; 1033 1034 if (sc->ti_mbuftx_dmat) 1035 for (i = 0; i < TI_TX_RING_CNT; i++) 1036 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1037 bus_dmamap_destroy(sc->ti_mbuftx_dmat, 1038 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1039 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1040 } 1041 1042 if (sc->ti_mbufrx_dmat) 1043 for (i = 0; i < TI_STD_RX_RING_CNT; i++) 1044 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1045 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1046 sc->ti_cdata.ti_rx_std_maps[i]); 1047 sc->ti_cdata.ti_rx_std_maps[i] = 0; 1048 } 1049 1050 if (sc->ti_jumbo_dmat) 1051 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) 1052 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1053 bus_dmamap_destroy(sc->ti_jumbo_dmat, 1054 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1055 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0; 1056 } 1057 if (sc->ti_mbufrx_dmat) 1058 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) 1059 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1060 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1061 sc->ti_cdata.ti_rx_mini_maps[i]); 1062 sc->ti_cdata.ti_rx_mini_maps[i] = 0; 1063 } 1064} 1065 1066#ifdef TI_PRIVATE_JUMBOS 1067 1068/* 1069 * Memory management for the jumbo receive ring is a pain in the 1070 * butt. We need to allocate at least 9018 bytes of space per frame, 1071 * _and_ it has to be contiguous (unless you use the extended 1072 * jumbo descriptor format). Using malloc() all the time won't 1073 * work: malloc() allocates memory in powers of two, which means we 1074 * would end up wasting a considerable amount of space by allocating 1075 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 1076 * to do our own memory management. 1077 * 1078 * The driver needs to allocate a contiguous chunk of memory at boot 1079 * time. We then chop this up ourselves into 9K pieces and use them 1080 * as external mbuf storage. 1081 * 1082 * One issue here is how much memory to allocate. The jumbo ring has 1083 * 256 slots in it, but at 9K per slot than can consume over 2MB of 1084 * RAM. This is a bit much, especially considering we also need 1085 * RAM for the standard ring and mini ring (on the Tigon 2). To 1086 * save space, we only actually allocate enough memory for 64 slots 1087 * by default, which works out to between 500 and 600K. This can 1088 * be tuned by changing a #define in if_tireg.h. 1089 */ 1090 1091static int 1092ti_alloc_jumbo_mem(sc) 1093 struct ti_softc *sc; 1094{ 1095 caddr_t ptr; 1096 int i; 1097 struct ti_jpool_entry *entry; 1098 1099 /* 1100 * Grab a big chunk o' storage. Since we are chopping this pool up 1101 * into ~9k chunks, there doesn't appear to be a need to use page 1102 * alignment. 1103 */ 1104 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1105 1, 0, /* algnmnt, boundary */ 1106 BUS_SPACE_MAXADDR, /* lowaddr */ 1107 BUS_SPACE_MAXADDR, /* highaddr */ 1108 NULL, NULL, /* filter, filterarg */ 1109 TI_JMEM, /* maxsize */ 1110 1, /* nsegments */ 1111 TI_JMEM, /* maxsegsize */ 1112 0, /* flags */ 1113 NULL, NULL, /* lockfunc, lockarg */ 1114 &sc->ti_jumbo_dmat) != 0) { 1115 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1116 return (ENOBUFS); 1117 } 1118 1119 if (bus_dmamem_alloc(sc->ti_jumbo_dmat, 1120 (void**)&sc->ti_cdata.ti_jumbo_buf, 1121 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 1122 &sc->ti_jumbo_dmamap) != 0) { 1123 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n"); 1124 return (ENOBUFS); 1125 } 1126 1127 SLIST_INIT(&sc->ti_jfree_listhead); 1128 SLIST_INIT(&sc->ti_jinuse_listhead); 1129 1130 /* 1131 * Now divide it up into 9K pieces and save the addresses 1132 * in an array. 1133 */ 1134 ptr = sc->ti_cdata.ti_jumbo_buf; 1135 for (i = 0; i < TI_JSLOTS; i++) { 1136 sc->ti_cdata.ti_jslots[i] = ptr; 1137 ptr += TI_JLEN; 1138 entry = malloc(sizeof(struct ti_jpool_entry), 1139 M_DEVBUF, M_NOWAIT); 1140 if (entry == NULL) { 1141 device_printf(sc->ti_dev, "no memory for jumbo " 1142 "buffer queue!\n"); 1143 return (ENOBUFS); 1144 } 1145 entry->slot = i; 1146 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1147 } 1148 1149 return (0); 1150} 1151 1152/* 1153 * Allocate a jumbo buffer. 1154 */ 1155static void *ti_jalloc(sc) 1156 struct ti_softc *sc; 1157{ 1158 struct ti_jpool_entry *entry; 1159 1160 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1161 1162 if (entry == NULL) { 1163 device_printf(sc->ti_dev, "no free jumbo buffers\n"); 1164 return (NULL); 1165 } 1166 1167 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1168 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1169 return (sc->ti_cdata.ti_jslots[entry->slot]); 1170} 1171 1172/* 1173 * Release a jumbo buffer. 1174 */ 1175static void 1176ti_jfree(buf, args) 1177 void *buf; 1178 void *args; 1179{ 1180 struct ti_softc *sc; 1181 int i; 1182 struct ti_jpool_entry *entry; 1183 1184 /* Extract the softc struct pointer. */ 1185 sc = (struct ti_softc *)args; 1186 1187 if (sc == NULL) 1188 panic("ti_jfree: didn't get softc pointer!"); 1189 1190 /* calculate the slot this buffer belongs to */ 1191 i = ((vm_offset_t)buf 1192 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1193 1194 if ((i < 0) || (i >= TI_JSLOTS)) 1195 panic("ti_jfree: asked to free buffer that we don't manage!"); 1196 1197 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1198 if (entry == NULL) 1199 panic("ti_jfree: buffer not in use!"); 1200 entry->slot = i; 1201 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1202 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1203} 1204 1205#else 1206 1207static int 1208ti_alloc_jumbo_mem(sc) 1209 struct ti_softc *sc; 1210{ 1211 1212 /* 1213 * The VM system will take care of providing aligned pages. Alignment 1214 * is set to 1 here so that busdma resources won't be wasted. 1215 */ 1216 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1217 1, 0, /* algnmnt, boundary */ 1218 BUS_SPACE_MAXADDR, /* lowaddr */ 1219 BUS_SPACE_MAXADDR, /* highaddr */ 1220 NULL, NULL, /* filter, filterarg */ 1221 PAGE_SIZE * 4 /*XXX*/, /* maxsize */ 1222 4, /* nsegments */ 1223 PAGE_SIZE, /* maxsegsize */ 1224 0, /* flags */ 1225 NULL, NULL, /* lockfunc, lockarg */ 1226 &sc->ti_jumbo_dmat) != 0) { 1227 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1228 return (ENOBUFS); 1229 } 1230 1231 return (0); 1232} 1233 1234#endif /* TI_PRIVATE_JUMBOS */ 1235 1236/* 1237 * Intialize a standard receive ring descriptor. 1238 */ 1239static int 1240ti_newbuf_std(sc, i, m) 1241 struct ti_softc *sc; 1242 int i; 1243 struct mbuf *m; 1244{ 1245 bus_dmamap_t map; 1246 bus_dma_segment_t segs; 1247 struct mbuf *m_new = NULL; 1248 struct ti_rx_desc *r; 1249 int nsegs; 1250 1251 nsegs = 0; 1252 if (m == NULL) { 1253 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1254 if (m_new == NULL) 1255 return (ENOBUFS); 1256 1257 MCLGET(m_new, M_DONTWAIT); 1258 if (!(m_new->m_flags & M_EXT)) { 1259 m_freem(m_new); 1260 return (ENOBUFS); 1261 } 1262 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1263 } else { 1264 m_new = m; 1265 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1266 m_new->m_data = m_new->m_ext.ext_buf; 1267 } 1268 1269 m_adj(m_new, ETHER_ALIGN); 1270 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1271 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1272 map = sc->ti_cdata.ti_rx_std_maps[i]; 1273 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1274 &nsegs, 0)) 1275 return (ENOBUFS); 1276 if (nsegs != 1) 1277 return (ENOBUFS); 1278 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1279 r->ti_len = segs.ds_len; 1280 r->ti_type = TI_BDTYPE_RECV_BD; 1281 r->ti_flags = 0; 1282 if (sc->ti_ifp->if_hwassist) 1283 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1284 r->ti_idx = i; 1285 1286 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1287 return (0); 1288} 1289 1290/* 1291 * Intialize a mini receive ring descriptor. This only applies to 1292 * the Tigon 2. 1293 */ 1294static int 1295ti_newbuf_mini(sc, i, m) 1296 struct ti_softc *sc; 1297 int i; 1298 struct mbuf *m; 1299{ 1300 bus_dma_segment_t segs; 1301 bus_dmamap_t map; 1302 struct mbuf *m_new = NULL; 1303 struct ti_rx_desc *r; 1304 int nsegs; 1305 1306 nsegs = 0; 1307 if (m == NULL) { 1308 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1309 if (m_new == NULL) { 1310 return (ENOBUFS); 1311 } 1312 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1313 } else { 1314 m_new = m; 1315 m_new->m_data = m_new->m_pktdat; 1316 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1317 } 1318 1319 m_adj(m_new, ETHER_ALIGN); 1320 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1321 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1322 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1323 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1324 &nsegs, 0)) 1325 return (ENOBUFS); 1326 if (nsegs != 1) 1327 return (ENOBUFS); 1328 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1329 r->ti_len = segs.ds_len; 1330 r->ti_type = TI_BDTYPE_RECV_BD; 1331 r->ti_flags = TI_BDFLAG_MINI_RING; 1332 if (sc->ti_ifp->if_hwassist) 1333 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1334 r->ti_idx = i; 1335 1336 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1337 return (0); 1338} 1339 1340#ifdef TI_PRIVATE_JUMBOS 1341 1342/* 1343 * Initialize a jumbo receive ring descriptor. This allocates 1344 * a jumbo buffer from the pool managed internally by the driver. 1345 */ 1346static int 1347ti_newbuf_jumbo(sc, i, m) 1348 struct ti_softc *sc; 1349 int i; 1350 struct mbuf *m; 1351{ 1352 bus_dmamap_t map; 1353 struct mbuf *m_new = NULL; 1354 struct ti_rx_desc *r; 1355 int nsegs; 1356 bus_dma_segment_t segs; 1357 1358 if (m == NULL) { 1359 caddr_t *buf = NULL; 1360 1361 /* Allocate the mbuf. */ 1362 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1363 if (m_new == NULL) { 1364 return (ENOBUFS); 1365 } 1366 1367 /* Allocate the jumbo buffer */ 1368 buf = ti_jalloc(sc); 1369 if (buf == NULL) { 1370 m_freem(m_new); 1371 device_printf(sc->ti_dev, "jumbo allocation failed " 1372 "-- packet dropped!\n"); 1373 return (ENOBUFS); 1374 } 1375 1376 /* Attach the buffer to the mbuf. */ 1377 m_new->m_data = (void *) buf; 1378 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1379 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1380 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1381 } else { 1382 m_new = m; 1383 m_new->m_data = m_new->m_ext.ext_buf; 1384 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1385 } 1386 1387 m_adj(m_new, ETHER_ALIGN); 1388 /* Set up the descriptor. */ 1389 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1390 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1391 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1392 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs, 1393 &nsegs, 0)) 1394 return (ENOBUFS); 1395 if (nsegs != 1) 1396 return (ENOBUFS); 1397 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1398 r->ti_len = segs.ds_len; 1399 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1400 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1401 if (sc->ti_ifp->if_hwassist) 1402 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1403 r->ti_idx = i; 1404 1405 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1406 return (0); 1407} 1408 1409#else 1410 1411#if (PAGE_SIZE == 4096) 1412#define NPAYLOAD 2 1413#else 1414#define NPAYLOAD 1 1415#endif 1416 1417#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1418#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1419#define NFS_HDR_LEN (UDP_HDR_LEN) 1420static int HDR_LEN = TCP_HDR_LEN; 1421 1422 1423/* 1424 * Initialize a jumbo receive ring descriptor. This allocates 1425 * a jumbo buffer from the pool managed internally by the driver. 1426 */ 1427static int 1428ti_newbuf_jumbo(sc, idx, m_old) 1429 struct ti_softc *sc; 1430 int idx; 1431 struct mbuf *m_old; 1432{ 1433 bus_dmamap_t map; 1434 struct mbuf *cur, *m_new = NULL; 1435 struct mbuf *m[3] = {NULL, NULL, NULL}; 1436 struct ti_rx_desc_ext *r; 1437 vm_page_t frame; 1438 static int color; 1439 /* 1 extra buf to make nobufs easy*/ 1440 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1441 int i; 1442 bus_dma_segment_t segs[4]; 1443 int nsegs; 1444 1445 if (m_old != NULL) { 1446 m_new = m_old; 1447 cur = m_old->m_next; 1448 for (i = 0; i <= NPAYLOAD; i++){ 1449 m[i] = cur; 1450 cur = cur->m_next; 1451 } 1452 } else { 1453 /* Allocate the mbufs. */ 1454 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1455 if (m_new == NULL) { 1456 device_printf(sc->ti_dev, "mbuf allocation failed " 1457 "-- packet dropped!\n"); 1458 goto nobufs; 1459 } 1460 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1461 if (m[NPAYLOAD] == NULL) { 1462 device_printf(sc->ti_dev, "cluster mbuf allocation " 1463 "failed -- packet dropped!\n"); 1464 goto nobufs; 1465 } 1466 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1467 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1468 device_printf(sc->ti_dev, "mbuf allocation failed " 1469 "-- packet dropped!\n"); 1470 goto nobufs; 1471 } 1472 m[NPAYLOAD]->m_len = MCLBYTES; 1473 1474 for (i = 0; i < NPAYLOAD; i++){ 1475 MGET(m[i], M_DONTWAIT, MT_DATA); 1476 if (m[i] == NULL) { 1477 device_printf(sc->ti_dev, "mbuf allocation " 1478 "failed -- packet dropped!\n"); 1479 goto nobufs; 1480 } 1481 frame = vm_page_alloc(NULL, color++, 1482 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1483 VM_ALLOC_WIRED); 1484 if (frame == NULL) { 1485 device_printf(sc->ti_dev, "buffer allocation " 1486 "failed -- packet dropped!\n"); 1487 printf(" index %d page %d\n", idx, i); 1488 goto nobufs; 1489 } 1490 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1491 if (sf[i] == NULL) { 1492 vm_page_unwire(frame, 0); 1493 vm_page_free(frame); 1494 device_printf(sc->ti_dev, "buffer allocation " 1495 "failed -- packet dropped!\n"); 1496 printf(" index %d page %d\n", idx, i); 1497 goto nobufs; 1498 } 1499 } 1500 for (i = 0; i < NPAYLOAD; i++){ 1501 /* Attach the buffer to the mbuf. */ 1502 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1503 m[i]->m_len = PAGE_SIZE; 1504 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1505 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i], 1506 0, EXT_DISPOSABLE); 1507 m[i]->m_next = m[i+1]; 1508 } 1509 /* link the buffers to the header */ 1510 m_new->m_next = m[0]; 1511 m_new->m_data += ETHER_ALIGN; 1512 if (sc->ti_hdrsplit) 1513 m_new->m_len = MHLEN - ETHER_ALIGN; 1514 else 1515 m_new->m_len = HDR_LEN; 1516 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1517 } 1518 1519 /* Set up the descriptor. */ 1520 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1521 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1522 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1523 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs, 1524 &nsegs, 0)) 1525 return (ENOBUFS); 1526 if ((nsegs < 1) || (nsegs > 4)) 1527 return (ENOBUFS); 1528 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1529 r->ti_len0 = m_new->m_len; 1530 1531 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1532 r->ti_len1 = PAGE_SIZE; 1533 1534 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1535 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1536 1537 if (PAGE_SIZE == 4096) { 1538 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1539 r->ti_len3 = MCLBYTES; 1540 } else { 1541 r->ti_len3 = 0; 1542 } 1543 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1544 1545 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1546 1547 if (sc->ti_ifp->if_hwassist) 1548 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1549 1550 r->ti_idx = idx; 1551 1552 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1553 return (0); 1554 1555nobufs: 1556 1557 /* 1558 * Warning! : 1559 * This can only be called before the mbufs are strung together. 1560 * If the mbufs are strung together, m_freem() will free the chain, 1561 * so that the later mbufs will be freed multiple times. 1562 */ 1563 if (m_new) 1564 m_freem(m_new); 1565 1566 for (i = 0; i < 3; i++) { 1567 if (m[i]) 1568 m_freem(m[i]); 1569 if (sf[i]) 1570 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1571 } 1572 return (ENOBUFS); 1573} 1574#endif 1575 1576 1577 1578/* 1579 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1580 * that's 1MB or memory, which is a lot. For now, we fill only the first 1581 * 256 ring entries and hope that our CPU is fast enough to keep up with 1582 * the NIC. 1583 */ 1584static int 1585ti_init_rx_ring_std(sc) 1586 struct ti_softc *sc; 1587{ 1588 int i; 1589 struct ti_cmd_desc cmd; 1590 1591 for (i = 0; i < TI_SSLOTS; i++) { 1592 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1593 return (ENOBUFS); 1594 }; 1595 1596 TI_UPDATE_STDPROD(sc, i - 1); 1597 sc->ti_std = i - 1; 1598 1599 return (0); 1600} 1601 1602static void 1603ti_free_rx_ring_std(sc) 1604 struct ti_softc *sc; 1605{ 1606 bus_dmamap_t map; 1607 int i; 1608 1609 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1610 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1611 map = sc->ti_cdata.ti_rx_std_maps[i]; 1612 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1613 BUS_DMASYNC_POSTREAD); 1614 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1615 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1616 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1617 } 1618 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1619 sizeof(struct ti_rx_desc)); 1620 } 1621} 1622 1623static int 1624ti_init_rx_ring_jumbo(sc) 1625 struct ti_softc *sc; 1626{ 1627 int i; 1628 struct ti_cmd_desc cmd; 1629 1630 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1631 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1632 return (ENOBUFS); 1633 }; 1634 1635 TI_UPDATE_JUMBOPROD(sc, i - 1); 1636 sc->ti_jumbo = i - 1; 1637 1638 return (0); 1639} 1640 1641static void 1642ti_free_rx_ring_jumbo(sc) 1643 struct ti_softc *sc; 1644{ 1645 bus_dmamap_t map; 1646 int i; 1647 1648 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1649 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1650 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1651 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 1652 BUS_DMASYNC_POSTREAD); 1653 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 1654 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1655 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1656 } 1657 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1658 sizeof(struct ti_rx_desc)); 1659 } 1660} 1661 1662static int 1663ti_init_rx_ring_mini(sc) 1664 struct ti_softc *sc; 1665{ 1666 int i; 1667 1668 for (i = 0; i < TI_MSLOTS; i++) { 1669 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1670 return (ENOBUFS); 1671 }; 1672 1673 TI_UPDATE_MINIPROD(sc, i - 1); 1674 sc->ti_mini = i - 1; 1675 1676 return (0); 1677} 1678 1679static void 1680ti_free_rx_ring_mini(sc) 1681 struct ti_softc *sc; 1682{ 1683 bus_dmamap_t map; 1684 int i; 1685 1686 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1687 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1688 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1689 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1690 BUS_DMASYNC_POSTREAD); 1691 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1692 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1693 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1694 } 1695 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1696 sizeof(struct ti_rx_desc)); 1697 } 1698} 1699 1700static void 1701ti_free_tx_ring(sc) 1702 struct ti_softc *sc; 1703{ 1704 struct ti_txdesc *txd; 1705 int i; 1706 1707 if (sc->ti_rdata->ti_tx_ring == NULL) 1708 return; 1709 1710 for (i = 0; i < TI_TX_RING_CNT; i++) { 1711 txd = &sc->ti_cdata.ti_txdesc[i]; 1712 if (txd->tx_m != NULL) { 1713 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 1714 BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 1716 m_freem(txd->tx_m); 1717 txd->tx_m = NULL; 1718 } 1719 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1720 sizeof(struct ti_tx_desc)); 1721 } 1722} 1723 1724static int 1725ti_init_tx_ring(sc) 1726 struct ti_softc *sc; 1727{ 1728 struct ti_txdesc *txd; 1729 int i; 1730 1731 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1732 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1733 for (i = 0; i < TI_TX_RING_CNT; i++) { 1734 txd = &sc->ti_cdata.ti_txdesc[i]; 1735 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1736 } 1737 sc->ti_txcnt = 0; 1738 sc->ti_tx_saved_considx = 0; 1739 sc->ti_tx_saved_prodidx = 0; 1740 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1741 return (0); 1742} 1743 1744/* 1745 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1746 * but we have to support the old way too so that Tigon 1 cards will 1747 * work. 1748 */ 1749static void 1750ti_add_mcast(sc, addr) 1751 struct ti_softc *sc; 1752 struct ether_addr *addr; 1753{ 1754 struct ti_cmd_desc cmd; 1755 u_int16_t *m; 1756 u_int32_t ext[2] = {0, 0}; 1757 1758 m = (u_int16_t *)&addr->octet[0]; 1759 1760 switch (sc->ti_hwrev) { 1761 case TI_HWREV_TIGON: 1762 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1763 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1764 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1765 break; 1766 case TI_HWREV_TIGON_II: 1767 ext[0] = htons(m[0]); 1768 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1769 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1770 break; 1771 default: 1772 device_printf(sc->ti_dev, "unknown hwrev\n"); 1773 break; 1774 } 1775} 1776 1777static void 1778ti_del_mcast(sc, addr) 1779 struct ti_softc *sc; 1780 struct ether_addr *addr; 1781{ 1782 struct ti_cmd_desc cmd; 1783 u_int16_t *m; 1784 u_int32_t ext[2] = {0, 0}; 1785 1786 m = (u_int16_t *)&addr->octet[0]; 1787 1788 switch (sc->ti_hwrev) { 1789 case TI_HWREV_TIGON: 1790 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1791 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1792 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1793 break; 1794 case TI_HWREV_TIGON_II: 1795 ext[0] = htons(m[0]); 1796 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1797 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1798 break; 1799 default: 1800 device_printf(sc->ti_dev, "unknown hwrev\n"); 1801 break; 1802 } 1803} 1804 1805/* 1806 * Configure the Tigon's multicast address filter. 1807 * 1808 * The actual multicast table management is a bit of a pain, thanks to 1809 * slight brain damage on the part of both Alteon and us. With our 1810 * multicast code, we are only alerted when the multicast address table 1811 * changes and at that point we only have the current list of addresses: 1812 * we only know the current state, not the previous state, so we don't 1813 * actually know what addresses were removed or added. The firmware has 1814 * state, but we can't get our grubby mits on it, and there is no 'delete 1815 * all multicast addresses' command. Hence, we have to maintain our own 1816 * state so we know what addresses have been programmed into the NIC at 1817 * any given time. 1818 */ 1819static void 1820ti_setmulti(sc) 1821 struct ti_softc *sc; 1822{ 1823 struct ifnet *ifp; 1824 struct ifmultiaddr *ifma; 1825 struct ti_cmd_desc cmd; 1826 struct ti_mc_entry *mc; 1827 u_int32_t intrs; 1828 1829 TI_LOCK_ASSERT(sc); 1830 1831 ifp = sc->ti_ifp; 1832 1833 if (ifp->if_flags & IFF_ALLMULTI) { 1834 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1835 return; 1836 } else { 1837 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1838 } 1839 1840 /* Disable interrupts. */ 1841 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1842 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1843 1844 /* First, zot all the existing filters. */ 1845 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1846 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1847 ti_del_mcast(sc, &mc->mc_addr); 1848 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1849 free(mc, M_DEVBUF); 1850 } 1851 1852 /* Now program new ones. */ 1853 if_maddr_rlock(ifp); 1854 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1855 if (ifma->ifma_addr->sa_family != AF_LINK) 1856 continue; 1857 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1858 if (mc == NULL) { 1859 device_printf(sc->ti_dev, 1860 "no memory for mcast filter entry\n"); 1861 continue; 1862 } 1863 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1864 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1865 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1866 ti_add_mcast(sc, &mc->mc_addr); 1867 } 1868 if_maddr_runlock(ifp); 1869 1870 /* Re-enable interrupts. */ 1871 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1872} 1873 1874/* 1875 * Check to see if the BIOS has configured us for a 64 bit slot when 1876 * we aren't actually in one. If we detect this condition, we can work 1877 * around it on the Tigon 2 by setting a bit in the PCI state register, 1878 * but for the Tigon 1 we must give up and abort the interface attach. 1879 */ 1880static int ti_64bitslot_war(sc) 1881 struct ti_softc *sc; 1882{ 1883 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1884 CSR_WRITE_4(sc, 0x600, 0); 1885 CSR_WRITE_4(sc, 0x604, 0); 1886 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1887 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1888 if (sc->ti_hwrev == TI_HWREV_TIGON) 1889 return (EINVAL); 1890 else { 1891 TI_SETBIT(sc, TI_PCI_STATE, 1892 TI_PCISTATE_32BIT_BUS); 1893 return (0); 1894 } 1895 } 1896 } 1897 1898 return (0); 1899} 1900 1901/* 1902 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1903 * self-test results. 1904 */ 1905static int 1906ti_chipinit(sc) 1907 struct ti_softc *sc; 1908{ 1909 u_int32_t cacheline; 1910 u_int32_t pci_writemax = 0; 1911 u_int32_t hdrsplit; 1912 1913 /* Initialize link to down state. */ 1914 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1915 1916 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM) 1917 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 1918 else 1919 sc->ti_ifp->if_hwassist = 0; 1920 1921 /* Set endianness before we access any non-PCI registers. */ 1922#if 0 && BYTE_ORDER == BIG_ENDIAN 1923 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1924 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1925#else 1926 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1927 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1928#endif 1929 1930 /* Check the ROM failed bit to see if self-tests passed. */ 1931 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1932 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 1933 return (ENODEV); 1934 } 1935 1936 /* Halt the CPU. */ 1937 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1938 1939 /* Figure out the hardware revision. */ 1940 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1941 case TI_REV_TIGON_I: 1942 sc->ti_hwrev = TI_HWREV_TIGON; 1943 break; 1944 case TI_REV_TIGON_II: 1945 sc->ti_hwrev = TI_HWREV_TIGON_II; 1946 break; 1947 default: 1948 device_printf(sc->ti_dev, "unsupported chip revision\n"); 1949 return (ENODEV); 1950 } 1951 1952 /* Do special setup for Tigon 2. */ 1953 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1954 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1955 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1956 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1957 } 1958 1959 /* 1960 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1961 * can't do header splitting. 1962 */ 1963#ifdef TI_JUMBO_HDRSPLIT 1964 if (sc->ti_hwrev != TI_HWREV_TIGON) 1965 sc->ti_hdrsplit = 1; 1966 else 1967 device_printf(sc->ti_dev, 1968 "can't do header splitting on a Tigon I board\n"); 1969#endif /* TI_JUMBO_HDRSPLIT */ 1970 1971 /* Set up the PCI state register. */ 1972 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1973 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1974 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1975 } 1976 1977 /* Clear the read/write max DMA parameters. */ 1978 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1979 TI_PCISTATE_READ_MAXDMA)); 1980 1981 /* Get cache line size. */ 1982 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1983 1984 /* 1985 * If the system has set enabled the PCI memory write 1986 * and invalidate command in the command register, set 1987 * the write max parameter accordingly. This is necessary 1988 * to use MWI with the Tigon 2. 1989 */ 1990 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1991 switch (cacheline) { 1992 case 1: 1993 case 4: 1994 case 8: 1995 case 16: 1996 case 32: 1997 case 64: 1998 break; 1999 default: 2000 /* Disable PCI memory write and invalidate. */ 2001 if (bootverbose) 2002 device_printf(sc->ti_dev, "cache line size %d" 2003 " not supported; disabling PCI MWI\n", 2004 cacheline); 2005 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2006 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2007 break; 2008 } 2009 } 2010 2011 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2012 2013 /* This sets the min dma param all the way up (0xff). */ 2014 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2015 2016 if (sc->ti_hdrsplit) 2017 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2018 else 2019 hdrsplit = 0; 2020 2021 /* Configure DMA variables. */ 2022#if BYTE_ORDER == BIG_ENDIAN 2023 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2024 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2025 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2026 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2027#else /* BYTE_ORDER */ 2028 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2029 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2030 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2031#endif /* BYTE_ORDER */ 2032 2033 /* 2034 * Only allow 1 DMA channel to be active at a time. 2035 * I don't think this is a good idea, but without it 2036 * the firmware racks up lots of nicDmaReadRingFull 2037 * errors. This is not compatible with hardware checksums. 2038 */ 2039 if (sc->ti_ifp->if_hwassist == 0) 2040 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2041 2042 /* Recommended settings from Tigon manual. */ 2043 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2044 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2045 2046 if (ti_64bitslot_war(sc)) { 2047 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2048 "but we aren't"); 2049 return (EINVAL); 2050 } 2051 2052 return (0); 2053} 2054 2055/* 2056 * Initialize the general information block and firmware, and 2057 * start the CPU(s) running. 2058 */ 2059static int 2060ti_gibinit(sc) 2061 struct ti_softc *sc; 2062{ 2063 struct ti_rcb *rcb; 2064 int i; 2065 struct ifnet *ifp; 2066 uint32_t rdphys; 2067 2068 TI_LOCK_ASSERT(sc); 2069 2070 ifp = sc->ti_ifp; 2071 rdphys = sc->ti_rdata_phys; 2072 2073 /* Disable interrupts for now. */ 2074 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2075 2076 /* 2077 * Tell the chip where to find the general information block. 2078 * While this struct could go into >4GB memory, we allocate it in a 2079 * single slab with the other descriptors, and those don't seem to 2080 * support being located in a 64-bit region. 2081 */ 2082 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 2083 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 2084 2085 /* Load the firmware into SRAM. */ 2086 ti_loadfw(sc); 2087 2088 /* Set up the contents of the general info and ring control blocks. */ 2089 2090 /* Set up the event ring and producer pointer. */ 2091 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 2092 2093 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 2094 rcb->ti_flags = 0; 2095 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 2096 rdphys + TI_RD_OFF(ti_ev_prodidx_r); 2097 sc->ti_ev_prodidx.ti_idx = 0; 2098 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2099 sc->ti_ev_saved_considx = 0; 2100 2101 /* Set up the command ring and producer mailbox. */ 2102 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 2103 2104 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 2105 rcb->ti_flags = 0; 2106 rcb->ti_max_len = 0; 2107 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2108 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2109 } 2110 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2111 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2112 sc->ti_cmd_saved_prodidx = 0; 2113 2114 /* 2115 * Assign the address of the stats refresh buffer. 2116 * We re-use the current stats buffer for this to 2117 * conserve memory. 2118 */ 2119 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 2120 rdphys + TI_RD_OFF(ti_info.ti_stats); 2121 2122 /* Set up the standard receive ring. */ 2123 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 2124 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 2125 rcb->ti_max_len = TI_FRAMELEN; 2126 rcb->ti_flags = 0; 2127 if (sc->ti_ifp->if_hwassist) 2128 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2129 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2130 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2131 2132 /* Set up the jumbo receive ring. */ 2133 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 2134 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 2135 2136#ifdef TI_PRIVATE_JUMBOS 2137 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 2138 rcb->ti_flags = 0; 2139#else 2140 rcb->ti_max_len = PAGE_SIZE; 2141 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2142#endif 2143 if (sc->ti_ifp->if_hwassist) 2144 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2145 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2146 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2147 2148 /* 2149 * Set up the mini ring. Only activated on the 2150 * Tigon 2 but the slot in the config block is 2151 * still there on the Tigon 1. 2152 */ 2153 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 2154 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 2155 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2156 if (sc->ti_hwrev == TI_HWREV_TIGON) 2157 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2158 else 2159 rcb->ti_flags = 0; 2160 if (sc->ti_ifp->if_hwassist) 2161 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2162 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2163 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2164 2165 /* 2166 * Set up the receive return ring. 2167 */ 2168 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 2169 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 2170 rcb->ti_flags = 0; 2171 rcb->ti_max_len = TI_RETURN_RING_CNT; 2172 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 2173 rdphys + TI_RD_OFF(ti_return_prodidx_r); 2174 2175 /* 2176 * Set up the tx ring. Note: for the Tigon 2, we have the option 2177 * of putting the transmit ring in the host's address space and 2178 * letting the chip DMA it instead of leaving the ring in the NIC's 2179 * memory and accessing it through the shared memory region. We 2180 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2181 * so we have to revert to the shared memory scheme if we detect 2182 * a Tigon 1 chip. 2183 */ 2184 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2185 bzero((char *)sc->ti_rdata->ti_tx_ring, 2186 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 2187 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 2188 if (sc->ti_hwrev == TI_HWREV_TIGON) 2189 rcb->ti_flags = 0; 2190 else 2191 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2192 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2193 if (sc->ti_ifp->if_hwassist) 2194 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2195 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2196 rcb->ti_max_len = TI_TX_RING_CNT; 2197 if (sc->ti_hwrev == TI_HWREV_TIGON) 2198 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2199 else 2200 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 2201 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2202 rdphys + TI_RD_OFF(ti_tx_considx_r); 2203 2204 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2205 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2206 2207 /* Set up tuneables */ 2208#if 0 2209 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2210 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2211 (sc->ti_rx_coal_ticks / 10)); 2212 else 2213#endif 2214 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2215 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2216 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2217 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2218 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2219 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2220 2221 /* Turn interrupts on. */ 2222 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2223 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2224 2225 /* Start CPU. */ 2226 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2227 2228 return (0); 2229} 2230 2231static void 2232ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2233{ 2234 struct ti_softc *sc; 2235 2236 sc = arg; 2237 if (error || nseg != 1) 2238 return; 2239 2240 /* 2241 * All of the Tigon data structures need to live at <4GB. This 2242 * cast is fine since busdma was told about this constraint. 2243 */ 2244 sc->ti_rdata_phys = segs[0].ds_addr; 2245 return; 2246} 2247 2248/* 2249 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2250 * against our list and return its name if we find a match. 2251 */ 2252static int 2253ti_probe(dev) 2254 device_t dev; 2255{ 2256 const struct ti_type *t; 2257 2258 t = ti_devs; 2259 2260 while (t->ti_name != NULL) { 2261 if ((pci_get_vendor(dev) == t->ti_vid) && 2262 (pci_get_device(dev) == t->ti_did)) { 2263 device_set_desc(dev, t->ti_name); 2264 return (BUS_PROBE_DEFAULT); 2265 } 2266 t++; 2267 } 2268 2269 return (ENXIO); 2270} 2271 2272static int 2273ti_attach(dev) 2274 device_t dev; 2275{ 2276 struct ifnet *ifp; 2277 struct ti_softc *sc; 2278 int error = 0, rid; 2279 u_char eaddr[6]; 2280 2281 sc = device_get_softc(dev); 2282 sc->ti_unit = device_get_unit(dev); 2283 sc->ti_dev = dev; 2284 2285 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2286 MTX_DEF); 2287 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2288 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2289 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2290 if (ifp == NULL) { 2291 device_printf(dev, "can not if_alloc()\n"); 2292 error = ENOSPC; 2293 goto fail; 2294 } 2295 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM | 2296 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2297 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2298 2299 /* 2300 * Map control/status registers. 2301 */ 2302 pci_enable_busmaster(dev); 2303 2304 rid = TI_PCI_LOMEM; 2305 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2306 RF_ACTIVE); 2307 2308 if (sc->ti_res == NULL) { 2309 device_printf(dev, "couldn't map memory\n"); 2310 error = ENXIO; 2311 goto fail; 2312 } 2313 2314 sc->ti_btag = rman_get_bustag(sc->ti_res); 2315 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2316 2317 /* Allocate interrupt */ 2318 rid = 0; 2319 2320 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2321 RF_SHAREABLE | RF_ACTIVE); 2322 2323 if (sc->ti_irq == NULL) { 2324 device_printf(dev, "couldn't map interrupt\n"); 2325 error = ENXIO; 2326 goto fail; 2327 } 2328 2329 if (ti_chipinit(sc)) { 2330 device_printf(dev, "chip initialization failed\n"); 2331 error = ENXIO; 2332 goto fail; 2333 } 2334 2335 /* Zero out the NIC's on-board SRAM. */ 2336 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2337 2338 /* Init again -- zeroing memory may have clobbered some registers. */ 2339 if (ti_chipinit(sc)) { 2340 device_printf(dev, "chip initialization failed\n"); 2341 error = ENXIO; 2342 goto fail; 2343 } 2344 2345 /* 2346 * Get station address from the EEPROM. Note: the manual states 2347 * that the MAC address is at offset 0x8c, however the data is 2348 * stored as two longwords (since that's how it's loaded into 2349 * the NIC). This means the MAC address is actually preceded 2350 * by two zero bytes. We need to skip over those. 2351 */ 2352 if (ti_read_eeprom(sc, eaddr, 2353 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2354 device_printf(dev, "failed to read station address\n"); 2355 error = ENXIO; 2356 goto fail; 2357 } 2358 2359 /* Allocate the general information block and ring buffers. */ 2360 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 2361 1, 0, /* algnmnt, boundary */ 2362 BUS_SPACE_MAXADDR, /* lowaddr */ 2363 BUS_SPACE_MAXADDR, /* highaddr */ 2364 NULL, NULL, /* filter, filterarg */ 2365 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2366 0, /* nsegments */ 2367 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2368 0, /* flags */ 2369 NULL, NULL, /* lockfunc, lockarg */ 2370 &sc->ti_parent_dmat) != 0) { 2371 device_printf(dev, "Failed to allocate parent dmat\n"); 2372 error = ENOMEM; 2373 goto fail; 2374 } 2375 2376 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2377 PAGE_SIZE, 0, /* algnmnt, boundary */ 2378 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2379 BUS_SPACE_MAXADDR, /* highaddr */ 2380 NULL, NULL, /* filter, filterarg */ 2381 sizeof(struct ti_ring_data), /* maxsize */ 2382 1, /* nsegments */ 2383 sizeof(struct ti_ring_data), /* maxsegsize */ 2384 0, /* flags */ 2385 NULL, NULL, /* lockfunc, lockarg */ 2386 &sc->ti_rdata_dmat) != 0) { 2387 device_printf(dev, "Failed to allocate rdata dmat\n"); 2388 error = ENOMEM; 2389 goto fail; 2390 } 2391 2392 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2393 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 2394 &sc->ti_rdata_dmamap) != 0) { 2395 device_printf(dev, "Failed to allocate rdata memory\n"); 2396 error = ENOMEM; 2397 goto fail; 2398 } 2399 2400 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2401 sc->ti_rdata, sizeof(struct ti_ring_data), 2402 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2403 device_printf(dev, "Failed to load rdata segments\n"); 2404 error = ENOMEM; 2405 goto fail; 2406 } 2407 2408 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2409 2410 /* Try to allocate memory for jumbo buffers. */ 2411 if (ti_alloc_jumbo_mem(sc)) { 2412 device_printf(dev, "jumbo buffer allocation failed\n"); 2413 error = ENXIO; 2414 goto fail; 2415 } 2416 2417 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2418 1, 0, /* algnmnt, boundary */ 2419 BUS_SPACE_MAXADDR, /* lowaddr */ 2420 BUS_SPACE_MAXADDR, /* highaddr */ 2421 NULL, NULL, /* filter, filterarg */ 2422 MCLBYTES * TI_MAXTXSEGS,/* maxsize */ 2423 TI_MAXTXSEGS, /* nsegments */ 2424 MCLBYTES, /* maxsegsize */ 2425 0, /* flags */ 2426 NULL, NULL, /* lockfunc, lockarg */ 2427 &sc->ti_mbuftx_dmat) != 0) { 2428 device_printf(dev, "Failed to allocate rdata dmat\n"); 2429 error = ENOMEM; 2430 goto fail; 2431 } 2432 2433 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2434 1, 0, /* algnmnt, boundary */ 2435 BUS_SPACE_MAXADDR, /* lowaddr */ 2436 BUS_SPACE_MAXADDR, /* highaddr */ 2437 NULL, NULL, /* filter, filterarg */ 2438 MCLBYTES, /* maxsize */ 2439 1, /* nsegments */ 2440 MCLBYTES, /* maxsegsize */ 2441 0, /* flags */ 2442 NULL, NULL, /* lockfunc, lockarg */ 2443 &sc->ti_mbufrx_dmat) != 0) { 2444 device_printf(dev, "Failed to allocate rdata dmat\n"); 2445 error = ENOMEM; 2446 goto fail; 2447 } 2448 2449 if (ti_alloc_dmamaps(sc)) { 2450 device_printf(dev, "dma map creation failed\n"); 2451 error = ENXIO; 2452 goto fail; 2453 } 2454 2455 /* 2456 * We really need a better way to tell a 1000baseTX card 2457 * from a 1000baseSX one, since in theory there could be 2458 * OEMed 1000baseTX cards from lame vendors who aren't 2459 * clever enough to change the PCI ID. For the moment 2460 * though, the AceNIC is the only copper card available. 2461 */ 2462 if (pci_get_vendor(dev) == ALT_VENDORID && 2463 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2464 sc->ti_copper = 1; 2465 /* Ok, it's not the only copper card available. */ 2466 if (pci_get_vendor(dev) == NG_VENDORID && 2467 pci_get_device(dev) == NG_DEVICEID_GA620T) 2468 sc->ti_copper = 1; 2469 2470 /* Set default tuneable values. */ 2471 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2472#if 0 2473 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2474#endif 2475 sc->ti_rx_coal_ticks = 170; 2476 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2477 sc->ti_rx_max_coal_bds = 64; 2478#if 0 2479 sc->ti_tx_max_coal_bds = 128; 2480#endif 2481 sc->ti_tx_max_coal_bds = 32; 2482 sc->ti_tx_buf_ratio = 21; 2483 2484 /* Set up ifnet structure */ 2485 ifp->if_softc = sc; 2486 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2487 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2488 ifp->if_ioctl = ti_ioctl; 2489 ifp->if_start = ti_start; 2490 ifp->if_init = ti_init; 2491 ifp->if_baudrate = 1000000000; 2492 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2493 2494 /* Set up ifmedia support. */ 2495 if (sc->ti_copper) { 2496 /* 2497 * Copper cards allow manual 10/100 mode selection, 2498 * but not manual 1000baseTX mode selection. Why? 2499 * Becuase currently there's no way to specify the 2500 * master/slave setting through the firmware interface, 2501 * so Alteon decided to just bag it and handle it 2502 * via autonegotiation. 2503 */ 2504 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2505 ifmedia_add(&sc->ifmedia, 2506 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2507 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2508 ifmedia_add(&sc->ifmedia, 2509 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2510 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2511 ifmedia_add(&sc->ifmedia, 2512 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2513 } else { 2514 /* Fiber cards don't support 10/100 modes. */ 2515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2516 ifmedia_add(&sc->ifmedia, 2517 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2518 } 2519 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2520 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2521 2522 /* 2523 * We're assuming here that card initialization is a sequential 2524 * thing. If it isn't, multiple cards probing at the same time 2525 * could stomp on the list of softcs here. 2526 */ 2527 2528 /* Register the device */ 2529 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2530 0600, "ti%d", sc->ti_unit); 2531 sc->dev->si_drv1 = sc; 2532 2533 /* 2534 * Call MI attach routine. 2535 */ 2536 ether_ifattach(ifp, eaddr); 2537 2538 /* Hook interrupt last to avoid having to lock softc */ 2539 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2540 NULL, ti_intr, sc, &sc->ti_intrhand); 2541 2542 if (error) { 2543 device_printf(dev, "couldn't set up irq\n"); 2544 goto fail; 2545 } 2546 2547fail: 2548 if (error) 2549 ti_detach(dev); 2550 2551 return (error); 2552} 2553 2554/* 2555 * Shutdown hardware and free up resources. This can be called any 2556 * time after the mutex has been initialized. It is called in both 2557 * the error case in attach and the normal detach case so it needs 2558 * to be careful about only freeing resources that have actually been 2559 * allocated. 2560 */ 2561static int 2562ti_detach(dev) 2563 device_t dev; 2564{ 2565 struct ti_softc *sc; 2566 struct ifnet *ifp; 2567 2568 sc = device_get_softc(dev); 2569 if (sc->dev) 2570 destroy_dev(sc->dev); 2571 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2572 ifp = sc->ti_ifp; 2573 if (device_is_attached(dev)) { 2574 ether_ifdetach(ifp); 2575 TI_LOCK(sc); 2576 ti_stop(sc); 2577 TI_UNLOCK(sc); 2578 } 2579 2580 /* These should only be active if attach succeeded */ 2581 callout_drain(&sc->ti_watchdog); 2582 bus_generic_detach(dev); 2583 ti_free_dmamaps(sc); 2584 ifmedia_removeall(&sc->ifmedia); 2585 2586#ifdef TI_PRIVATE_JUMBOS 2587 if (sc->ti_cdata.ti_jumbo_buf) 2588 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf, 2589 sc->ti_jumbo_dmamap); 2590#endif 2591 if (sc->ti_jumbo_dmat) 2592 bus_dma_tag_destroy(sc->ti_jumbo_dmat); 2593 if (sc->ti_mbuftx_dmat) 2594 bus_dma_tag_destroy(sc->ti_mbuftx_dmat); 2595 if (sc->ti_mbufrx_dmat) 2596 bus_dma_tag_destroy(sc->ti_mbufrx_dmat); 2597 if (sc->ti_rdata) 2598 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2599 sc->ti_rdata_dmamap); 2600 if (sc->ti_rdata_dmat) 2601 bus_dma_tag_destroy(sc->ti_rdata_dmat); 2602 if (sc->ti_parent_dmat) 2603 bus_dma_tag_destroy(sc->ti_parent_dmat); 2604 if (sc->ti_intrhand) 2605 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2606 if (sc->ti_irq) 2607 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2608 if (sc->ti_res) { 2609 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2610 sc->ti_res); 2611 } 2612 if (ifp) 2613 if_free(ifp); 2614 2615 mtx_destroy(&sc->ti_mtx); 2616 2617 return (0); 2618} 2619 2620#ifdef TI_JUMBO_HDRSPLIT 2621/* 2622 * If hdr_len is 0, that means that header splitting wasn't done on 2623 * this packet for some reason. The two most likely reasons are that 2624 * the protocol isn't a supported protocol for splitting, or this 2625 * packet had a fragment offset that wasn't 0. 2626 * 2627 * The header length, if it is non-zero, will always be the length of 2628 * the headers on the packet, but that length could be longer than the 2629 * first mbuf. So we take the minimum of the two as the actual 2630 * length. 2631 */ 2632static __inline void 2633ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2634{ 2635 int i = 0; 2636 int lengths[4] = {0, 0, 0, 0}; 2637 struct mbuf *m, *mp; 2638 2639 if (hdr_len != 0) 2640 top->m_len = min(hdr_len, top->m_len); 2641 pkt_len -= top->m_len; 2642 lengths[i++] = top->m_len; 2643 2644 mp = top; 2645 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2646 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2647 pkt_len -= m->m_len; 2648 lengths[i++] = m->m_len; 2649 mp = m; 2650 } 2651 2652#if 0 2653 if (hdr_len != 0) 2654 printf("got split packet: "); 2655 else 2656 printf("got non-split packet: "); 2657 2658 printf("%d,%d,%d,%d = %d\n", lengths[0], 2659 lengths[1], lengths[2], lengths[3], 2660 lengths[0] + lengths[1] + lengths[2] + 2661 lengths[3]); 2662#endif 2663 2664 if (pkt_len) 2665 panic("header splitting didn't"); 2666 2667 if (m) { 2668 m_freem(m); 2669 mp->m_next = NULL; 2670 2671 } 2672 if (mp->m_next != NULL) 2673 panic("ti_hdr_split: last mbuf in chain should be null"); 2674} 2675#endif /* TI_JUMBO_HDRSPLIT */ 2676 2677/* 2678 * Frame reception handling. This is called if there's a frame 2679 * on the receive return list. 2680 * 2681 * Note: we have to be able to handle three possibilities here: 2682 * 1) the frame is from the mini receive ring (can only happen) 2683 * on Tigon 2 boards) 2684 * 2) the frame is from the jumbo recieve ring 2685 * 3) the frame is from the standard receive ring 2686 */ 2687 2688static void 2689ti_rxeof(sc) 2690 struct ti_softc *sc; 2691{ 2692 bus_dmamap_t map; 2693 struct ifnet *ifp; 2694 struct ti_cmd_desc cmd; 2695 2696 TI_LOCK_ASSERT(sc); 2697 2698 ifp = sc->ti_ifp; 2699 2700 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2701 struct ti_rx_desc *cur_rx; 2702 u_int32_t rxidx; 2703 struct mbuf *m = NULL; 2704 u_int16_t vlan_tag = 0; 2705 int have_tag = 0; 2706 2707 cur_rx = 2708 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2709 rxidx = cur_rx->ti_idx; 2710 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2711 2712 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2713 have_tag = 1; 2714 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2715 } 2716 2717 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2718 2719 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2720 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2721 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2722 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2723 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 2724 BUS_DMASYNC_POSTREAD); 2725 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 2726 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2727 ifp->if_ierrors++; 2728 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2729 continue; 2730 } 2731 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2732 ifp->if_ierrors++; 2733 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2734 continue; 2735 } 2736#ifdef TI_PRIVATE_JUMBOS 2737 m->m_len = cur_rx->ti_len; 2738#else /* TI_PRIVATE_JUMBOS */ 2739#ifdef TI_JUMBO_HDRSPLIT 2740 if (sc->ti_hdrsplit) 2741 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2742 cur_rx->ti_len, rxidx); 2743 else 2744#endif /* TI_JUMBO_HDRSPLIT */ 2745 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2746#endif /* TI_PRIVATE_JUMBOS */ 2747 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2748 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2749 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2750 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2751 map = sc->ti_cdata.ti_rx_mini_maps[rxidx]; 2752 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2753 BUS_DMASYNC_POSTREAD); 2754 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2755 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2756 ifp->if_ierrors++; 2757 ti_newbuf_mini(sc, sc->ti_mini, m); 2758 continue; 2759 } 2760 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2761 ifp->if_ierrors++; 2762 ti_newbuf_mini(sc, sc->ti_mini, m); 2763 continue; 2764 } 2765 m->m_len = cur_rx->ti_len; 2766 } else { 2767 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2768 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2769 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2770 map = sc->ti_cdata.ti_rx_std_maps[rxidx]; 2771 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2772 BUS_DMASYNC_POSTREAD); 2773 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2774 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2775 ifp->if_ierrors++; 2776 ti_newbuf_std(sc, sc->ti_std, m); 2777 continue; 2778 } 2779 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2780 ifp->if_ierrors++; 2781 ti_newbuf_std(sc, sc->ti_std, m); 2782 continue; 2783 } 2784 m->m_len = cur_rx->ti_len; 2785 } 2786 2787 m->m_pkthdr.len = cur_rx->ti_len; 2788 ifp->if_ipackets++; 2789 m->m_pkthdr.rcvif = ifp; 2790 2791 if (ifp->if_hwassist) { 2792 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2793 CSUM_DATA_VALID; 2794 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2795 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2796 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2797 } 2798 2799 /* 2800 * If we received a packet with a vlan tag, 2801 * tag it before passing the packet upward. 2802 */ 2803 if (have_tag) { 2804 m->m_pkthdr.ether_vtag = vlan_tag; 2805 m->m_flags |= M_VLANTAG; 2806 } 2807 TI_UNLOCK(sc); 2808 (*ifp->if_input)(ifp, m); 2809 TI_LOCK(sc); 2810 } 2811 2812 /* Only necessary on the Tigon 1. */ 2813 if (sc->ti_hwrev == TI_HWREV_TIGON) 2814 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2815 sc->ti_rx_saved_considx); 2816 2817 TI_UPDATE_STDPROD(sc, sc->ti_std); 2818 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2819 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2820} 2821 2822static void 2823ti_txeof(sc) 2824 struct ti_softc *sc; 2825{ 2826 struct ti_txdesc *txd; 2827 struct ti_tx_desc txdesc; 2828 struct ti_tx_desc *cur_tx = NULL; 2829 struct ifnet *ifp; 2830 int idx; 2831 2832 ifp = sc->ti_ifp; 2833 2834 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2835 if (txd == NULL) 2836 return; 2837 /* 2838 * Go through our tx ring and free mbufs for those 2839 * frames that have been sent. 2840 */ 2841 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2842 TI_INC(idx, TI_TX_RING_CNT)) { 2843 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2844 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2845 sizeof(txdesc), &txdesc); 2846 cur_tx = &txdesc; 2847 } else 2848 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2849 sc->ti_txcnt--; 2850 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2851 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2852 continue; 2853 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2854 BUS_DMASYNC_POSTWRITE); 2855 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2856 2857 ifp->if_opackets++; 2858 m_freem(txd->tx_m); 2859 txd->tx_m = NULL; 2860 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2861 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2862 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2863 } 2864 sc->ti_tx_saved_considx = idx; 2865 2866 sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0; 2867} 2868 2869static void 2870ti_intr(xsc) 2871 void *xsc; 2872{ 2873 struct ti_softc *sc; 2874 struct ifnet *ifp; 2875 2876 sc = xsc; 2877 TI_LOCK(sc); 2878 ifp = sc->ti_ifp; 2879 2880/*#ifdef notdef*/ 2881 /* Avoid this for now -- checking this register is expensive. */ 2882 /* Make sure this is really our interrupt. */ 2883 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2884 TI_UNLOCK(sc); 2885 return; 2886 } 2887/*#endif*/ 2888 2889 /* Ack interrupt and stop others from occuring. */ 2890 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2891 2892 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2893 /* Check RX return ring producer/consumer */ 2894 ti_rxeof(sc); 2895 2896 /* Check TX ring producer/consumer */ 2897 ti_txeof(sc); 2898 } 2899 2900 ti_handle_events(sc); 2901 2902 /* Re-enable interrupts. */ 2903 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2904 2905 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2906 ifp->if_snd.ifq_head != NULL) 2907 ti_start_locked(ifp); 2908 2909 TI_UNLOCK(sc); 2910} 2911 2912static void 2913ti_stats_update(sc) 2914 struct ti_softc *sc; 2915{ 2916 struct ifnet *ifp; 2917 2918 ifp = sc->ti_ifp; 2919 2920 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2921 BUS_DMASYNC_POSTREAD); 2922 2923 ifp->if_collisions += 2924 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2925 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2926 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2927 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2928 ifp->if_collisions; 2929 2930 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2931 BUS_DMASYNC_PREREAD); 2932} 2933 2934/* 2935 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2936 * pointers to descriptors. 2937 */ 2938static int 2939ti_encap(sc, m_head) 2940 struct ti_softc *sc; 2941 struct mbuf **m_head; 2942{ 2943 struct ti_txdesc *txd; 2944 struct ti_tx_desc *f; 2945 struct ti_tx_desc txdesc; 2946 struct mbuf *m; 2947 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 2948 u_int16_t csum_flags; 2949 int error, frag, i, nseg; 2950 2951 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 2952 return (ENOBUFS); 2953 2954 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2955 *m_head, txsegs, &nseg, 0); 2956 if (error == EFBIG) { 2957 m = m_defrag(*m_head, M_DONTWAIT); 2958 if (m == NULL) { 2959 m_freem(*m_head); 2960 *m_head = NULL; 2961 return (ENOMEM); 2962 } 2963 *m_head = m; 2964 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, 2965 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2966 if (error) { 2967 m_freem(*m_head); 2968 *m_head = NULL; 2969 return (error); 2970 } 2971 } else if (error != 0) 2972 return (error); 2973 if (nseg == 0) { 2974 m_freem(*m_head); 2975 *m_head = NULL; 2976 return (EIO); 2977 } 2978 2979 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 2980 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2981 return (ENOBUFS); 2982 } 2983 2984 m = *m_head; 2985 csum_flags = 0; 2986 if (m->m_pkthdr.csum_flags) { 2987 if (m->m_pkthdr.csum_flags & CSUM_IP) 2988 csum_flags |= TI_BDFLAG_IP_CKSUM; 2989 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2990 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2991 if (m->m_flags & M_LASTFRAG) 2992 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2993 else if (m->m_flags & M_FRAG) 2994 csum_flags |= TI_BDFLAG_IP_FRAG; 2995 } 2996 2997 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2998 BUS_DMASYNC_PREWRITE); 2999 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 3000 BUS_DMASYNC_PREWRITE); 3001 3002 frag = sc->ti_tx_saved_prodidx; 3003 for (i = 0; i < nseg; i++) { 3004 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3005 bzero(&txdesc, sizeof(txdesc)); 3006 f = &txdesc; 3007 } else 3008 f = &sc->ti_rdata->ti_tx_ring[frag]; 3009 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3010 f->ti_len = txsegs[i].ds_len; 3011 f->ti_flags = csum_flags; 3012 if (m->m_flags & M_VLANTAG) { 3013 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3014 f->ti_vlan_tag = m->m_pkthdr.ether_vtag & 0xfff; 3015 } else { 3016 f->ti_vlan_tag = 0; 3017 } 3018 3019 if (sc->ti_hwrev == TI_HWREV_TIGON) 3020 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3021 sizeof(txdesc), sizeof(txdesc), &txdesc); 3022 TI_INC(frag, TI_TX_RING_CNT); 3023 } 3024 3025 sc->ti_tx_saved_prodidx = frag; 3026 /* set TI_BDFLAG_END on the last descriptor */ 3027 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3028 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3029 txdesc.ti_flags |= TI_BDFLAG_END; 3030 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3031 sizeof(txdesc), &txdesc); 3032 } else 3033 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3034 3035 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3036 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3037 txd->tx_m = m; 3038 sc->ti_txcnt += nseg; 3039 3040 return (0); 3041} 3042 3043static void 3044ti_start(ifp) 3045 struct ifnet *ifp; 3046{ 3047 struct ti_softc *sc; 3048 3049 sc = ifp->if_softc; 3050 TI_LOCK(sc); 3051 ti_start_locked(ifp); 3052 TI_UNLOCK(sc); 3053} 3054 3055/* 3056 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3057 * to the mbuf data regions directly in the transmit descriptors. 3058 */ 3059static void 3060ti_start_locked(ifp) 3061 struct ifnet *ifp; 3062{ 3063 struct ti_softc *sc; 3064 struct mbuf *m_head = NULL; 3065 int enq = 0; 3066 3067 sc = ifp->if_softc; 3068 3069 for (; ifp->if_snd.ifq_head != NULL && 3070 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3071 IF_DEQUEUE(&ifp->if_snd, m_head); 3072 if (m_head == NULL) 3073 break; 3074 3075 /* 3076 * XXX 3077 * safety overkill. If this is a fragmented packet chain 3078 * with delayed TCP/UDP checksums, then only encapsulate 3079 * it if we have enough descriptors to handle the entire 3080 * chain at once. 3081 * (paranoia -- may not actually be needed) 3082 */ 3083 if (m_head->m_flags & M_FIRSTFRAG && 3084 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3085 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3086 m_head->m_pkthdr.csum_data + 16) { 3087 IF_PREPEND(&ifp->if_snd, m_head); 3088 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3089 break; 3090 } 3091 } 3092 3093 /* 3094 * Pack the data into the transmit ring. If we 3095 * don't have room, set the OACTIVE flag and wait 3096 * for the NIC to drain the ring. 3097 */ 3098 if (ti_encap(sc, &m_head)) { 3099 if (m_head == NULL) 3100 break; 3101 IF_PREPEND(&ifp->if_snd, m_head); 3102 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3103 break; 3104 } 3105 3106 enq++; 3107 /* 3108 * If there's a BPF listener, bounce a copy of this frame 3109 * to him. 3110 */ 3111 ETHER_BPF_MTAP(ifp, m_head); 3112 } 3113 3114 if (enq > 0) { 3115 /* Transmit */ 3116 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3117 3118 /* 3119 * Set a timeout in case the chip goes out to lunch. 3120 */ 3121 sc->ti_timer = 5; 3122 } 3123} 3124 3125static void 3126ti_init(xsc) 3127 void *xsc; 3128{ 3129 struct ti_softc *sc; 3130 3131 sc = xsc; 3132 TI_LOCK(sc); 3133 ti_init_locked(sc); 3134 TI_UNLOCK(sc); 3135} 3136 3137static void 3138ti_init_locked(xsc) 3139 void *xsc; 3140{ 3141 struct ti_softc *sc = xsc; 3142 3143 /* Cancel pending I/O and flush buffers. */ 3144 ti_stop(sc); 3145 3146 /* Init the gen info block, ring control blocks and firmware. */ 3147 if (ti_gibinit(sc)) { 3148 device_printf(sc->ti_dev, "initialization failure\n"); 3149 return; 3150 } 3151} 3152 3153static void ti_init2(sc) 3154 struct ti_softc *sc; 3155{ 3156 struct ti_cmd_desc cmd; 3157 struct ifnet *ifp; 3158 u_int8_t *ea; 3159 struct ifmedia *ifm; 3160 int tmp; 3161 3162 TI_LOCK_ASSERT(sc); 3163 3164 ifp = sc->ti_ifp; 3165 3166 /* Specify MTU and interface index. */ 3167 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 3168 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3169 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3170 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3171 3172 /* Load our MAC address. */ 3173 ea = IF_LLADDR(sc->ti_ifp); 3174 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3175 CSR_WRITE_4(sc, TI_GCR_PAR1, 3176 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3177 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3178 3179 /* Enable or disable promiscuous mode as needed. */ 3180 if (ifp->if_flags & IFF_PROMISC) { 3181 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3182 } else { 3183 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3184 } 3185 3186 /* Program multicast filter. */ 3187 ti_setmulti(sc); 3188 3189 /* 3190 * If this is a Tigon 1, we should tell the 3191 * firmware to use software packet filtering. 3192 */ 3193 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3194 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3195 } 3196 3197 /* Init RX ring. */ 3198 ti_init_rx_ring_std(sc); 3199 3200 /* Init jumbo RX ring. */ 3201 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3202 ti_init_rx_ring_jumbo(sc); 3203 3204 /* 3205 * If this is a Tigon 2, we can also configure the 3206 * mini ring. 3207 */ 3208 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 3209 ti_init_rx_ring_mini(sc); 3210 3211 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3212 sc->ti_rx_saved_considx = 0; 3213 3214 /* Init TX ring. */ 3215 ti_init_tx_ring(sc); 3216 3217 /* Tell firmware we're alive. */ 3218 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3219 3220 /* Enable host interrupts. */ 3221 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3222 3223 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3224 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3225 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3226 3227 /* 3228 * Make sure to set media properly. We have to do this 3229 * here since we have to issue commands in order to set 3230 * the link negotiation and we can't issue commands until 3231 * the firmware is running. 3232 */ 3233 ifm = &sc->ifmedia; 3234 tmp = ifm->ifm_media; 3235 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3236 ti_ifmedia_upd(ifp); 3237 ifm->ifm_media = tmp; 3238} 3239 3240/* 3241 * Set media options. 3242 */ 3243static int 3244ti_ifmedia_upd(ifp) 3245 struct ifnet *ifp; 3246{ 3247 struct ti_softc *sc; 3248 struct ifmedia *ifm; 3249 struct ti_cmd_desc cmd; 3250 u_int32_t flowctl; 3251 3252 sc = ifp->if_softc; 3253 ifm = &sc->ifmedia; 3254 3255 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3256 return (EINVAL); 3257 3258 flowctl = 0; 3259 3260 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3261 case IFM_AUTO: 3262 /* 3263 * Transmit flow control doesn't work on the Tigon 1. 3264 */ 3265 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3266 3267 /* 3268 * Transmit flow control can also cause problems on the 3269 * Tigon 2, apparantly with both the copper and fiber 3270 * boards. The symptom is that the interface will just 3271 * hang. This was reproduced with Alteon 180 switches. 3272 */ 3273#if 0 3274 if (sc->ti_hwrev != TI_HWREV_TIGON) 3275 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3276#endif 3277 3278 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3279 TI_GLNK_FULL_DUPLEX| flowctl | 3280 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3281 3282 flowctl = TI_LNK_RX_FLOWCTL_Y; 3283#if 0 3284 if (sc->ti_hwrev != TI_HWREV_TIGON) 3285 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3286#endif 3287 3288 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3289 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3290 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3291 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3292 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3293 break; 3294 case IFM_1000_SX: 3295 case IFM_1000_T: 3296 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3297#if 0 3298 if (sc->ti_hwrev != TI_HWREV_TIGON) 3299 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3300#endif 3301 3302 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3303 flowctl |TI_GLNK_ENB); 3304 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3305 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3306 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3307 } 3308 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3309 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3310 break; 3311 case IFM_100_FX: 3312 case IFM_10_FL: 3313 case IFM_100_TX: 3314 case IFM_10_T: 3315 flowctl = TI_LNK_RX_FLOWCTL_Y; 3316#if 0 3317 if (sc->ti_hwrev != TI_HWREV_TIGON) 3318 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3319#endif 3320 3321 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3322 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3323 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3324 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3325 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3326 } else { 3327 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3328 } 3329 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3330 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3331 } else { 3332 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3333 } 3334 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3335 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3336 break; 3337 } 3338 3339 return (0); 3340} 3341 3342/* 3343 * Report current media status. 3344 */ 3345static void 3346ti_ifmedia_sts(ifp, ifmr) 3347 struct ifnet *ifp; 3348 struct ifmediareq *ifmr; 3349{ 3350 struct ti_softc *sc; 3351 u_int32_t media = 0; 3352 3353 sc = ifp->if_softc; 3354 3355 ifmr->ifm_status = IFM_AVALID; 3356 ifmr->ifm_active = IFM_ETHER; 3357 3358 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3359 return; 3360 3361 ifmr->ifm_status |= IFM_ACTIVE; 3362 3363 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3364 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3365 if (sc->ti_copper) 3366 ifmr->ifm_active |= IFM_1000_T; 3367 else 3368 ifmr->ifm_active |= IFM_1000_SX; 3369 if (media & TI_GLNK_FULL_DUPLEX) 3370 ifmr->ifm_active |= IFM_FDX; 3371 else 3372 ifmr->ifm_active |= IFM_HDX; 3373 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3374 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3375 if (sc->ti_copper) { 3376 if (media & TI_LNK_100MB) 3377 ifmr->ifm_active |= IFM_100_TX; 3378 if (media & TI_LNK_10MB) 3379 ifmr->ifm_active |= IFM_10_T; 3380 } else { 3381 if (media & TI_LNK_100MB) 3382 ifmr->ifm_active |= IFM_100_FX; 3383 if (media & TI_LNK_10MB) 3384 ifmr->ifm_active |= IFM_10_FL; 3385 } 3386 if (media & TI_LNK_FULL_DUPLEX) 3387 ifmr->ifm_active |= IFM_FDX; 3388 if (media & TI_LNK_HALF_DUPLEX) 3389 ifmr->ifm_active |= IFM_HDX; 3390 } 3391} 3392 3393static int 3394ti_ioctl(ifp, command, data) 3395 struct ifnet *ifp; 3396 u_long command; 3397 caddr_t data; 3398{ 3399 struct ti_softc *sc = ifp->if_softc; 3400 struct ifreq *ifr = (struct ifreq *) data; 3401 int mask, error = 0; 3402 struct ti_cmd_desc cmd; 3403 3404 switch (command) { 3405 case SIOCSIFMTU: 3406 TI_LOCK(sc); 3407 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3408 error = EINVAL; 3409 else { 3410 ifp->if_mtu = ifr->ifr_mtu; 3411 ti_init_locked(sc); 3412 } 3413 TI_UNLOCK(sc); 3414 break; 3415 case SIOCSIFFLAGS: 3416 TI_LOCK(sc); 3417 if (ifp->if_flags & IFF_UP) { 3418 /* 3419 * If only the state of the PROMISC flag changed, 3420 * then just use the 'set promisc mode' command 3421 * instead of reinitializing the entire NIC. Doing 3422 * a full re-init means reloading the firmware and 3423 * waiting for it to start up, which may take a 3424 * second or two. 3425 */ 3426 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3427 ifp->if_flags & IFF_PROMISC && 3428 !(sc->ti_if_flags & IFF_PROMISC)) { 3429 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3430 TI_CMD_CODE_PROMISC_ENB, 0); 3431 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3432 !(ifp->if_flags & IFF_PROMISC) && 3433 sc->ti_if_flags & IFF_PROMISC) { 3434 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3435 TI_CMD_CODE_PROMISC_DIS, 0); 3436 } else 3437 ti_init_locked(sc); 3438 } else { 3439 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3440 ti_stop(sc); 3441 } 3442 } 3443 sc->ti_if_flags = ifp->if_flags; 3444 TI_UNLOCK(sc); 3445 break; 3446 case SIOCADDMULTI: 3447 case SIOCDELMULTI: 3448 TI_LOCK(sc); 3449 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3450 ti_setmulti(sc); 3451 TI_UNLOCK(sc); 3452 break; 3453 case SIOCSIFMEDIA: 3454 case SIOCGIFMEDIA: 3455 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3456 break; 3457 case SIOCSIFCAP: 3458 TI_LOCK(sc); 3459 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3460 if (mask & IFCAP_HWCSUM) { 3461 if (IFCAP_HWCSUM & ifp->if_capenable) 3462 ifp->if_capenable &= ~IFCAP_HWCSUM; 3463 else 3464 ifp->if_capenable |= IFCAP_HWCSUM; 3465 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3466 ti_init_locked(sc); 3467 } 3468 TI_UNLOCK(sc); 3469 break; 3470 default: 3471 error = ether_ioctl(ifp, command, data); 3472 break; 3473 } 3474 3475 return (error); 3476} 3477 3478static int 3479ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3480{ 3481 struct ti_softc *sc; 3482 3483 sc = dev->si_drv1; 3484 if (sc == NULL) 3485 return (ENODEV); 3486 3487 TI_LOCK(sc); 3488 sc->ti_flags |= TI_FLAG_DEBUGING; 3489 TI_UNLOCK(sc); 3490 3491 return (0); 3492} 3493 3494static int 3495ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3496{ 3497 struct ti_softc *sc; 3498 3499 sc = dev->si_drv1; 3500 if (sc == NULL) 3501 return (ENODEV); 3502 3503 TI_LOCK(sc); 3504 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3505 TI_UNLOCK(sc); 3506 3507 return (0); 3508} 3509 3510/* 3511 * This ioctl routine goes along with the Tigon character device. 3512 */ 3513static int 3514ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3515 struct thread *td) 3516{ 3517 int error; 3518 struct ti_softc *sc; 3519 3520 sc = dev->si_drv1; 3521 if (sc == NULL) 3522 return (ENODEV); 3523 3524 error = 0; 3525 3526 switch (cmd) { 3527 case TIIOCGETSTATS: 3528 { 3529 struct ti_stats *outstats; 3530 3531 outstats = (struct ti_stats *)addr; 3532 3533 TI_LOCK(sc); 3534 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3535 sizeof(struct ti_stats)); 3536 TI_UNLOCK(sc); 3537 break; 3538 } 3539 case TIIOCGETPARAMS: 3540 { 3541 struct ti_params *params; 3542 3543 params = (struct ti_params *)addr; 3544 3545 TI_LOCK(sc); 3546 params->ti_stat_ticks = sc->ti_stat_ticks; 3547 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3548 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3549 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3550 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3551 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3552 params->param_mask = TI_PARAM_ALL; 3553 TI_UNLOCK(sc); 3554 3555 error = 0; 3556 3557 break; 3558 } 3559 case TIIOCSETPARAMS: 3560 { 3561 struct ti_params *params; 3562 3563 params = (struct ti_params *)addr; 3564 3565 TI_LOCK(sc); 3566 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3567 sc->ti_stat_ticks = params->ti_stat_ticks; 3568 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3569 } 3570 3571 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3572 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3573 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3574 sc->ti_rx_coal_ticks); 3575 } 3576 3577 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3578 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3579 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3580 sc->ti_tx_coal_ticks); 3581 } 3582 3583 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3584 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3585 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3586 sc->ti_rx_max_coal_bds); 3587 } 3588 3589 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3590 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3591 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3592 sc->ti_tx_max_coal_bds); 3593 } 3594 3595 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3596 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3597 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3598 sc->ti_tx_buf_ratio); 3599 } 3600 TI_UNLOCK(sc); 3601 3602 error = 0; 3603 3604 break; 3605 } 3606 case TIIOCSETTRACE: { 3607 ti_trace_type trace_type; 3608 3609 trace_type = *(ti_trace_type *)addr; 3610 3611 /* 3612 * Set tracing to whatever the user asked for. Setting 3613 * this register to 0 should have the effect of disabling 3614 * tracing. 3615 */ 3616 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3617 3618 error = 0; 3619 3620 break; 3621 } 3622 case TIIOCGETTRACE: { 3623 struct ti_trace_buf *trace_buf; 3624 u_int32_t trace_start, cur_trace_ptr, trace_len; 3625 3626 trace_buf = (struct ti_trace_buf *)addr; 3627 3628 TI_LOCK(sc); 3629 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3630 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3631 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3632 3633#if 0 3634 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3635 "trace_len = %d\n", trace_start, 3636 cur_trace_ptr, trace_len); 3637 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3638 trace_buf->buf_len); 3639#endif 3640 3641 error = ti_copy_mem(sc, trace_start, min(trace_len, 3642 trace_buf->buf_len), 3643 (caddr_t)trace_buf->buf, 1, 1); 3644 3645 if (error == 0) { 3646 trace_buf->fill_len = min(trace_len, 3647 trace_buf->buf_len); 3648 if (cur_trace_ptr < trace_start) 3649 trace_buf->cur_trace_ptr = 3650 trace_start - cur_trace_ptr; 3651 else 3652 trace_buf->cur_trace_ptr = 3653 cur_trace_ptr - trace_start; 3654 } else 3655 trace_buf->fill_len = 0; 3656 TI_UNLOCK(sc); 3657 3658 break; 3659 } 3660 3661 /* 3662 * For debugging, five ioctls are needed: 3663 * ALT_ATTACH 3664 * ALT_READ_TG_REG 3665 * ALT_WRITE_TG_REG 3666 * ALT_READ_TG_MEM 3667 * ALT_WRITE_TG_MEM 3668 */ 3669 case ALT_ATTACH: 3670 /* 3671 * From what I can tell, Alteon's Solaris Tigon driver 3672 * only has one character device, so you have to attach 3673 * to the Tigon board you're interested in. This seems 3674 * like a not-so-good way to do things, since unless you 3675 * subsequently specify the unit number of the device 3676 * you're interested in every ioctl, you'll only be 3677 * able to debug one board at a time. 3678 */ 3679 error = 0; 3680 break; 3681 case ALT_READ_TG_MEM: 3682 case ALT_WRITE_TG_MEM: 3683 { 3684 struct tg_mem *mem_param; 3685 u_int32_t sram_end, scratch_end; 3686 3687 mem_param = (struct tg_mem *)addr; 3688 3689 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3690 sram_end = TI_END_SRAM_I; 3691 scratch_end = TI_END_SCRATCH_I; 3692 } else { 3693 sram_end = TI_END_SRAM_II; 3694 scratch_end = TI_END_SCRATCH_II; 3695 } 3696 3697 /* 3698 * For now, we'll only handle accessing regular SRAM, 3699 * nothing else. 3700 */ 3701 TI_LOCK(sc); 3702 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3703 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3704 /* 3705 * In this instance, we always copy to/from user 3706 * space, so the user space argument is set to 1. 3707 */ 3708 error = ti_copy_mem(sc, mem_param->tgAddr, 3709 mem_param->len, 3710 mem_param->userAddr, 1, 3711 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3712 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3713 && (mem_param->tgAddr <= scratch_end)) { 3714 error = ti_copy_scratch(sc, mem_param->tgAddr, 3715 mem_param->len, 3716 mem_param->userAddr, 1, 3717 (cmd == ALT_READ_TG_MEM) ? 3718 1 : 0, TI_PROCESSOR_A); 3719 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3720 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3721 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3722 if_printf(sc->ti_ifp, 3723 "invalid memory range for Tigon I\n"); 3724 error = EINVAL; 3725 break; 3726 } 3727 error = ti_copy_scratch(sc, mem_param->tgAddr - 3728 TI_SCRATCH_DEBUG_OFF, 3729 mem_param->len, 3730 mem_param->userAddr, 1, 3731 (cmd == ALT_READ_TG_MEM) ? 3732 1 : 0, TI_PROCESSOR_B); 3733 } else { 3734 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3735 "out of supported range\n", 3736 mem_param->tgAddr, mem_param->len); 3737 error = EINVAL; 3738 } 3739 TI_UNLOCK(sc); 3740 3741 break; 3742 } 3743 case ALT_READ_TG_REG: 3744 case ALT_WRITE_TG_REG: 3745 { 3746 struct tg_reg *regs; 3747 u_int32_t tmpval; 3748 3749 regs = (struct tg_reg *)addr; 3750 3751 /* 3752 * Make sure the address in question isn't out of range. 3753 */ 3754 if (regs->addr > TI_REG_MAX) { 3755 error = EINVAL; 3756 break; 3757 } 3758 TI_LOCK(sc); 3759 if (cmd == ALT_READ_TG_REG) { 3760 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3761 regs->addr, &tmpval, 1); 3762 regs->data = ntohl(tmpval); 3763#if 0 3764 if ((regs->addr == TI_CPU_STATE) 3765 || (regs->addr == TI_CPU_CTL_B)) { 3766 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3767 regs->addr, tmpval); 3768 } 3769#endif 3770 } else { 3771 tmpval = htonl(regs->data); 3772 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3773 regs->addr, &tmpval, 1); 3774 } 3775 TI_UNLOCK(sc); 3776 3777 break; 3778 } 3779 default: 3780 error = ENOTTY; 3781 break; 3782 } 3783 return (error); 3784} 3785 3786static void 3787ti_watchdog(void *arg) 3788{ 3789 struct ti_softc *sc; 3790 struct ifnet *ifp; 3791 3792 sc = arg; 3793 TI_LOCK_ASSERT(sc); 3794 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3795 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3796 return; 3797 3798 /* 3799 * When we're debugging, the chip is often stopped for long periods 3800 * of time, and that would normally cause the watchdog timer to fire. 3801 * Since that impedes debugging, we don't want to do that. 3802 */ 3803 if (sc->ti_flags & TI_FLAG_DEBUGING) 3804 return; 3805 3806 ifp = sc->ti_ifp; 3807 if_printf(ifp, "watchdog timeout -- resetting\n"); 3808 ti_stop(sc); 3809 ti_init_locked(sc); 3810 3811 ifp->if_oerrors++; 3812} 3813 3814/* 3815 * Stop the adapter and free any mbufs allocated to the 3816 * RX and TX lists. 3817 */ 3818static void 3819ti_stop(sc) 3820 struct ti_softc *sc; 3821{ 3822 struct ifnet *ifp; 3823 struct ti_cmd_desc cmd; 3824 3825 TI_LOCK_ASSERT(sc); 3826 3827 ifp = sc->ti_ifp; 3828 3829 /* Disable host interrupts. */ 3830 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3831 /* 3832 * Tell firmware we're shutting down. 3833 */ 3834 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3835 3836 /* Halt and reinitialize. */ 3837 if (ti_chipinit(sc) != 0) 3838 return; 3839 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3840 if (ti_chipinit(sc) != 0) 3841 return; 3842 3843 /* Free the RX lists. */ 3844 ti_free_rx_ring_std(sc); 3845 3846 /* Free jumbo RX list. */ 3847 ti_free_rx_ring_jumbo(sc); 3848 3849 /* Free mini RX list. */ 3850 ti_free_rx_ring_mini(sc); 3851 3852 /* Free TX buffers. */ 3853 ti_free_tx_ring(sc); 3854 3855 sc->ti_ev_prodidx.ti_idx = 0; 3856 sc->ti_return_prodidx.ti_idx = 0; 3857 sc->ti_tx_considx.ti_idx = 0; 3858 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3859 3860 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3861 callout_stop(&sc->ti_watchdog); 3862} 3863 3864/* 3865 * Stop all chip I/O so that the kernel's probe routines don't 3866 * get confused by errant DMAs when rebooting. 3867 */ 3868static int 3869ti_shutdown(dev) 3870 device_t dev; 3871{ 3872 struct ti_softc *sc; 3873 3874 sc = device_get_softc(dev); 3875 TI_LOCK(sc); 3876 ti_chipinit(sc); 3877 TI_UNLOCK(sc); 3878 3879 return (0); 3880} 3881