1276333Sian/*- 2276333Sian * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3276333Sian * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4276333Sian * All rights reserved. 5276333Sian * 6276333Sian * Redistribution and use in source and binary forms, with or without 7276333Sian * modification, are permitted provided that the following conditions 8276333Sian * are met: 9276333Sian * 1. Redistributions of source code must retain the above copyright 10276333Sian * notice, this list of conditions and the following disclaimer. 11276333Sian * 2. Redistributions in binary form must reproduce the above copyright 12276333Sian * notice, this list of conditions and the following disclaimer in the 13276333Sian * documentation and/or other materials provided with the distribution. 14276333Sian * 15276333Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16276333Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17276333Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18276333Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19276333Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20276333Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21276333Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22276333Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23276333Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24276333Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25276333Sian * SUCH DAMAGE. 26276333Sian * 27276333Sian * $FreeBSD: stable/11/sys/arm/include/cpuinfo.h 331988 2018-04-04 06:11:05Z mmel $ 28276333Sian */ 29276333Sian 30276333Sian#ifndef _MACHINE_CPUINFO_H_ 31276333Sian#define _MACHINE_CPUINFO_H_ 32276333Sian 33276333Sian#include <sys/types.h> 34276333Sian 35289602Sian#define CPU_IMPLEMENTER_ARM 0x41 36289602Sian#define CPU_IMPLEMENTER_QCOM 0x51 37289602Sian#define CPU_IMPLEMENTER_MRVL 0x56 38289602Sian 39289602Sian/* ARM */ 40289602Sian#define CPU_ARCH_ARM1176 0xB76 41289602Sian#define CPU_ARCH_CORTEX_A5 0xC05 42289602Sian#define CPU_ARCH_CORTEX_A7 0xC07 43289602Sian#define CPU_ARCH_CORTEX_A8 0xC08 44289602Sian#define CPU_ARCH_CORTEX_A9 0xC09 45289602Sian#define CPU_ARCH_CORTEX_A12 0xC0D 46289602Sian#define CPU_ARCH_CORTEX_A15 0xC0F 47289602Sian#define CPU_ARCH_CORTEX_A17 0xC11 48307342Smmel#define CPU_ARCH_CORTEX_A53 0xD03 49307342Smmel#define CPU_ARCH_CORTEX_A57 0xD07 50307342Smmel#define CPU_ARCH_CORTEX_A72 0xD08 51314525Sian#define CPU_ARCH_CORTEX_A73 0xD09 52331988Smmel#define CPU_ARCH_CORTEX_A75 0xD0A 53289602Sian 54307342Smmel 55289602Sian/* QCOM */ 56289602Sian#define CPU_ARCH_KRAIT_300 0x06F 57289602Sian 58307342Smmel/* MRVL */ 59314525Sian#define CPU_ARCH_SHEEVA_581 0x581 /* PJ4/PJ4B */ 60307342Smmel#define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */ 61307342Smmel 62276333Sianstruct cpuinfo { 63276333Sian /* raw id registers */ 64276333Sian uint32_t midr; 65276333Sian uint32_t ctr; 66276333Sian uint32_t tcmtr; 67276333Sian uint32_t tlbtr; 68276333Sian uint32_t mpidr; 69276333Sian uint32_t revidr; 70276333Sian uint32_t id_pfr0; 71276333Sian uint32_t id_pfr1; 72276333Sian uint32_t id_dfr0; 73276333Sian uint32_t id_afr0; 74276333Sian uint32_t id_mmfr0; 75276333Sian uint32_t id_mmfr1; 76276333Sian uint32_t id_mmfr2; 77276333Sian uint32_t id_mmfr3; 78276333Sian uint32_t id_isar0; 79276333Sian uint32_t id_isar1; 80276333Sian uint32_t id_isar2; 81276333Sian uint32_t id_isar3; 82276333Sian uint32_t id_isar4; 83276333Sian uint32_t id_isar5; 84276333Sian uint32_t cbar; 85314525Sian uint32_t ccsidr; 86314525Sian uint32_t clidr; 87276333Sian 88314525Sian /* Parsed bits of above registers... */ 89276333Sian 90276333Sian /* midr */ 91276333Sian int implementer; 92276333Sian int revision; 93276333Sian int architecture; 94276333Sian int part_number; 95276333Sian int patch; 96276333Sian 97276333Sian /* id_mmfr0 */ 98276333Sian int outermost_shareability; 99276333Sian int shareability_levels; 100276333Sian int auxiliary_registers; 101276333Sian int innermost_shareability; 102276333Sian 103276333Sian /* id_mmfr1 */ 104276333Sian int mem_barrier; 105276333Sian 106276333Sian /* id_mmfr3 */ 107276333Sian int coherent_walk; 108276333Sian int maintenance_broadcast; 109276333Sian 110276333Sian /* id_pfr1 */ 111276333Sian int generic_timer_ext; 112276333Sian int virtualization_ext; 113276333Sian int security_ext; 114279811Sian 115279811Sian /* L1 cache info */ 116279811Sian int dcache_line_size; 117279811Sian int dcache_line_mask; 118279811Sian int icache_line_size; 119279811Sian int icache_line_mask; 120276333Sian}; 121276333Sian 122276333Sianextern struct cpuinfo cpuinfo; 123276333Sian 124276333Sianvoid cpuinfo_init(void); 125331968Smmel#if __ARM_ARCH >= 6 126331988Smmelvoid cpuinfo_init_bp_hardening(void); 127331968Smmelvoid cpuinfo_reinit_mmu(uint32_t ttb); 128331968Smmel#endif 129276333Sian#endif /* _MACHINE_CPUINFO_H_ */ 130