1/*-
2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: stable/11/sys/arm/include/cpuinfo.h 331988 2018-04-04 06:11:05Z mmel $
28 */
29
30#ifndef	_MACHINE_CPUINFO_H_
31#define	_MACHINE_CPUINFO_H_
32
33#include <sys/types.h>
34
35#define CPU_IMPLEMENTER_ARM		0x41
36#define CPU_IMPLEMENTER_QCOM		0x51
37#define CPU_IMPLEMENTER_MRVL		0x56
38
39/* ARM */
40#define CPU_ARCH_ARM1176		0xB76
41#define CPU_ARCH_CORTEX_A5		0xC05
42#define CPU_ARCH_CORTEX_A7		0xC07
43#define CPU_ARCH_CORTEX_A8		0xC08
44#define CPU_ARCH_CORTEX_A9		0xC09
45#define CPU_ARCH_CORTEX_A12		0xC0D
46#define CPU_ARCH_CORTEX_A15		0xC0F
47#define CPU_ARCH_CORTEX_A17		0xC11
48#define CPU_ARCH_CORTEX_A53		0xD03
49#define CPU_ARCH_CORTEX_A57		0xD07
50#define CPU_ARCH_CORTEX_A72		0xD08
51#define CPU_ARCH_CORTEX_A73		0xD09
52#define CPU_ARCH_CORTEX_A75		0xD0A
53
54
55/* QCOM */
56#define CPU_ARCH_KRAIT_300		0x06F
57
58/* MRVL */
59#define CPU_ARCH_SHEEVA_581		0x581	/* PJ4/PJ4B */
60#define CPU_ARCH_SHEEVA_584		0x584 	/* PJ4B-MP/PJ4C */
61
62struct cpuinfo {
63	/* raw id registers */
64	uint32_t midr;
65	uint32_t ctr;
66	uint32_t tcmtr;
67	uint32_t tlbtr;
68	uint32_t mpidr;
69	uint32_t revidr;
70	uint32_t id_pfr0;
71	uint32_t id_pfr1;
72	uint32_t id_dfr0;
73	uint32_t id_afr0;
74	uint32_t id_mmfr0;
75	uint32_t id_mmfr1;
76	uint32_t id_mmfr2;
77	uint32_t id_mmfr3;
78	uint32_t id_isar0;
79	uint32_t id_isar1;
80	uint32_t id_isar2;
81	uint32_t id_isar3;
82	uint32_t id_isar4;
83	uint32_t id_isar5;
84	uint32_t cbar;
85	uint32_t ccsidr;
86	uint32_t clidr;
87
88	/* Parsed bits of above registers... */
89
90	/* midr */
91	int implementer;
92	int revision;
93	int architecture;
94	int part_number;
95	int patch;
96
97	/* id_mmfr0 */
98	int outermost_shareability;
99	int shareability_levels;
100	int auxiliary_registers;
101	int innermost_shareability;
102
103	/* id_mmfr1 */
104	int mem_barrier;
105
106	/* id_mmfr3 */
107	int coherent_walk;
108	int maintenance_broadcast;
109
110	/* id_pfr1 */
111	int generic_timer_ext;
112	int virtualization_ext;
113	int security_ext;
114
115	/* L1 cache info */
116	int dcache_line_size;
117	int dcache_line_mask;
118	int icache_line_size;
119	int icache_line_mask;
120};
121
122extern struct cpuinfo cpuinfo;
123
124void cpuinfo_init(void);
125#if __ARM_ARCH >= 6
126void cpuinfo_init_bp_hardening(void);
127void cpuinfo_reinit_mmu(uint32_t ttb);
128#endif
129#endif	/* _MACHINE_CPUINFO_H_ */
130