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331968 |
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04-Apr-2018 |
mmel |
MFC r319896,r320054:
r319896: Implement tunable CPU quirks. These quirks are intended for optimizing CPU performance, not for applying errata workarounds. Nobody can expect that CPU with unfixed errata is stable enough to execute the kernel until quirks are applied. r320054: Manually load tunable CPU quirks. These are needed too early, far before SYSINIT is processed.
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289602 |
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19-Oct-2015 |
ian |
Set the correct values in the arm aux control register, based on chip type.
The bits in the aux control register vary based on the processor type. In the past we've always just set the 'smp' and "broadcast tlb/cache ops' bits, which worked fine for the first few SoCs we supported. Now that we support most of the cortex-a series processors, it's important to get the right bits set based on the processor type.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
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276333 |
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28-Dec-2014 |
ian |
Add new code to read and parse cpu identification data using the new CPUID mechanism defined for armv7 (and also present on some armv6 chips including the arm1176 used on rpi). The information is parsed into a global cpuinfo structure, which will be used by (upcoming) new cache and tlb maintenance code to handle cpu-specific variations of the maintence sequences.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz
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