History log of /freebsd-11-stable/sys/arm/include/cpuinfo.h
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# 331988 04-Apr-2018 mmel

MFC r328467:

Implement mitigation for Spectre version 2 attacks on ARMv7.


# 331968 04-Apr-2018 mmel

MFC r319896,r320054:

r319896:
Implement tunable CPU quirks. These quirks are intended for optimizing CPU
performance, not for applying errata workarounds. Nobody can expect that
CPU with unfixed errata is stable enough to execute the kernel until quirks
are applied.
r320054:
Manually load tunable CPU quirks. These are needed too early, far before
SYSINIT is processed.


# 314525 01-Mar-2017 ian

MFC r306901:

ARM: Split identify_arm_cpu() into ARMv4 and ARMv6 variant.
On ARMv6, be more verbose about supported CPU features and/or
optional instructions.


# 307342 15-Oct-2016 mmel

MFC r306755:

ARM: Add identifiers for ARM Cortex v8 and Marvell Sheeva v7 cores. Not a
functional change.


# 302408 07-Jul-2016 gjb

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation


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# 289602 19-Oct-2015 ian

Set the correct values in the arm aux control register, based on chip type.

The bits in the aux control register vary based on the processor type. In
the past we've always just set the 'smp' and "broadcast tlb/cache ops' bits,
which worked fine for the first few SoCs we supported. Now that we support
most of the cortex-a series processors, it's important to get the right bits
set based on the processor type.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>


# 279811 09-Mar-2015 ian

Add minimum cache line sizes to struct cpuinfo, use them in the new cache
maintenance routines. Also add a routine to invalidate the branch cache.

Submitted by: Michal Meloun


# 276333 28-Dec-2014 ian

Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7 (and also present on some armv6 chips including
the arm1176 used on rpi). The information is parsed into a global cpuinfo
structure, which will be used by (upcoming) new cache and tlb maintenance
code to handle cpu-specific variations of the maintence sequences.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz