Searched refs:ETH_CTL (Results 1 - 4 of 4) sorted by relevance
/netbsd-current/sys/arch/arm/at91/ |
H A D | at91emac.c | 145 EMAC_WRITE(ETH_CTL, 0); // disable everything 240 ctl = EMAC_READ(ETH_CTL); // get current control register value 241 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 243 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 338 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 355 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); 480 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 700 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG)); 717 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 734 EMAC_WRITE(ETH_CTL, ETH_CTL_MP [all...] |
H A D | at91emacreg.h | 36 #define ETH_CTL 0x00U /* 0x00: Control Register */ macro
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/netbsd-current/sys/dev/cadence/ |
H A D | if_cemac.c | 189 CEMAC_WRITE(ETH_CTL, 0); // disable everything 302 ctl = CEMAC_READ(ETH_CTL); // get current control register value 303 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 305 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 411 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 592 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 861 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 862 CEMAC_WRITE(ETH_CTL, ctl); 863 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); [all...] |
H A D | cemacreg.h | 39 #define ETH_CTL 0x00U /* 0x00: Control Register */ macro
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