Lines Matching refs:ETH_CTL
189 CEMAC_WRITE(ETH_CTL, 0); // disable everything
302 ctl = CEMAC_READ(ETH_CTL); // get current control register value
303 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
305 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
411 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
592 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
861 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX;
862 CEMAC_WRITE(ETH_CTL, ctl);
863 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL)));
884 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG));
922 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
939 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
977 uint32_t ctl = CEMAC_READ(ETH_CTL);
981 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
1082 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);