1/* $NetBSD: cemacreg.h,v 1.2 2015/08/13 14:51:35 rjs Exp $ */ 2 3/*- 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Copyright (c) 2007 Embedtronics Oy 8 * All rights reserved 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33#ifndef _IF_CEMACREG_H_ 34#define _IF_CEMACREG_H_ 35 36/* Ethernet MAC (EMAC), 37 * at91rm9200.pdf, page 573 */ 38 39#define ETH_CTL 0x00U /* 0x00: Control Register */ 40#define ETH_CFG 0x04U /* 0x04: Configuration Register */ 41#define ETH_SR 0x08U /* 0x08: Status Register */ 42#define ETH_TAR 0x0CU /* 0x0C: Transmit Address Register (at91rm9200 only) */ 43#define ETH_TCR 0x10U /* 0x10: Transmit Control Register (at91rm9200 only) */ 44#define ETH_TSR 0x14U /* 0x14: Transmit Status Register */ 45#define ETH_RBQP 0x18U /* 0x18: Receive Buffer Queue Pointer */ 46#define ETH_TBQP 0x1CU /* 0x1C: Transmit Buffer Queue Pointer */ 47#define ETH_RSR 0x20U /* 0x20: Receive Status Register */ 48#define ETH_ISR 0x24U /* 0x24: Interrupt Status Register */ 49#define ETH_IER 0x28U /* 0x28: Interrupt Enable Register */ 50#define ETH_IDR 0x2CU /* 0x2C: Interrupt Disable Register */ 51#define ETH_IMR 0x30U /* 0x30: Interrupt Mask Register */ 52#define ETH_MAN 0x34U /* 0x34: PHY Maintenance Register */ 53 54#define ETH_FRA 0x40U /* 0x40: Frames Transmitted OK */ 55#define ETH_SCOL 0x44U /* 0x44: Single Collision Frames */ 56#define ETH_MCOL 0x48U /* 0x48: Multiple Collision Frames */ 57#define ETH_OK 0x4CU /* 0x4C: Frames Received OK */ 58#define ETH_SEQE 0x50U /* 0x50: Frame Check Sequence Errors */ 59#define ETH_ALE 0x54U /* 0x54: Alignment Errors */ 60#define ETH_DTE 0x58U /* 0x58: Deferred Transmission Frame */ 61#define ETH_LCOL 0x5CU /* 0x5C: Late Collisions */ 62#define ETH_ECOL 0x60U /* 0x60: Excessive Collisions */ 63#define ETH_CSE 0x64U /* 0x64: Carrier Sense Errors */ 64#define ETH_TUE 0x68U /* 0x68: Transmit Underrun Errors */ 65#define ETH_CDE 0x6CU /* 0x6C: Code Errors */ 66#define ETH_ELR 0x70U /* 0x70: Excessive Length Errors */ 67#define ETH_RJB 0x74U /* 0x74: Receive Jabbers */ 68#define ETH_USF 0x78U /* 0x78: Undersize Frames */ 69#define ETH_SQEE 0x7CU /* 0x7C: SQE Test Errors */ 70#define ETH_DRFC 0x80U /* 0x80: Discarded RX Frames */ 71 72#define ETH_HSH 0x90U /* 0x90: Hash Address High */ 73#define ETH_HSL 0x94U /* 0x94: Hash Address Low */ 74 75#define ETH_SA1L 0x98U /* 0x98: Specific Address 1 Low */ 76#define ETH_SA1H 0x9CU /* 0x9C: Specific Address 1 High */ 77 78#define ETH_SA2L 0xA0U /* 0xA0: Specific Address 2 Low */ 79#define ETH_SA2H 0xA4U /* 0xA4: Specific Address 2 High */ 80 81#define ETH_SA3L 0xA8U /* 0xA8: Specific Address 3 Low */ 82#define ETH_SA3H 0xACU /* 0xAC: Specific Address 3 High */ 83 84#define ETH_SA4L 0xB0U /* 0xB0: Specific Address 4 Low */ 85#define ETH_SA4H 0xB4U /* 0xB4: Specific Address 4 High */ 86 87/* 88 * Gigabit Ethernet Controller (GEM) 89 * ug585-Zynq-7000-TRM.pdf 90 */ 91 92#define GEM_USER_IO 0x000C 93#define GEM_DMA_CFG 0x0010 /* DMA Configuration */ 94#define GEM_DMA_CFG_DISC_WHEN_NO_AHB __BIT(24) 95#define GEM_DMA_CFG_RX_BUF_SIZE __BITS(23, 16) 96#define GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN __BIT(11) 97#define GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL __BIT(10) 98#define GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL __BITS(9, 8) 99#define GEM_DMA_CFG_AHB_ENDIAN_SWAP_PKT_EN __BIT(7) 100#define GEM_DMA_CFG_AHB_ENDIAN_SWAP_MGMT_EN __BIT(6) 101#define GEM_DMA_CFG_AHB_FIXED_BURST_LEN __BITS(4, 0) 102#define GEM_HSH 0x0080 103#define GEM_HSL 0x0084 104#define GEM_SA1L 0x0088 105#define GEM_SA1H 0x008C 106#define GEM_SA2L 0x0090 107#define GEM_SA2H 0x0094 108#define GEM_SA3L 0x0098 109#define GEM_SA3H 0x009C 110#define GEM_SA4L 0x0090 111#define GEM_SA4H 0x0094 112#define GEM_SCOL 0x0138 113#define GEM_MCOL 0x013C 114#define GEM_DCFG2 0x0284 115#define GEM_DCFG3 0x0288 116#define GEM_DCFG4 0x028C 117#define GEM_DCFG5 0x0290 118 119#define ETH_SIZE 0x1000 120 121/* Control Register bits: */ 122#define GEM_CTL_ZEROPAUSETX __BIT(12) 123#define GEM_CTL_PAUSETX __BIT(11) 124#define GEM_CTL_HALTTX __BIT(10) 125#define GEM_CTL_STARTTX __BIT(9) 126 127#define ETH_CTL_BP 0x100U /* 1 = back pressure enabled */ 128#define ETH_CTL_WES 0x080U /* 1 = statistics registers writeable */ 129#define ETH_CTL_ISR 0x040U /* 1 = increment statistics registers */ 130#define ETH_CTL_CSR 0x020U /* 1 = clear statistics registers */ 131#define ETH_CTL_MPE 0x010U /* 1 = management port enabled */ 132#define ETH_CTL_TE 0x008U /* 1 = transmit enable */ 133#define ETH_CTL_RE 0x004U /* 1 = receive enable */ 134#define ETH_CTL_LBL 0x002U /* 1 = local loopback enabled */ 135#define ETH_CTL_LB 0x001U /* 1 = loopback signal is at high level */ 136 137 138/* Configuration Register bits: */ 139#define ETH_CFG_RMII 0x2000U /* 1 = enable RMII (Reduce MII) (AT91RM9200 only) */ 140#define ETH_CFG_RTY 0x1000U /* 1 = retry test enabled */ 141 142#define ETH_CFG_CLK 0x0C00U /* clock */ 143#define ETH_CFG_CLK_8 0x0000U 144#define ETH_CFG_CLK_16 0x0400U 145#define ETH_CFG_CLK_32 0x0800U 146#define ETH_CFG_CLK_64 0x0C00U 147 148#define ETH_CFG_EAE 0x0200U /* 1 = external address match enable */ 149#define ETH_CFG_BIG 0x0100U /* 1 = receive up to 1522 bytes (VLAN) */ 150#define ETH_CFG_UNI 0x0080U /* 1 = enable unicast hash */ 151#define ETH_CFG_MTI 0x0040U /* 1 = enable multicast hash */ 152#define ETH_CFG_NBC 0x0020U /* 1 = ignore received broadcasts */ 153#define ETH_CFG_CAF 0x0010U /* 1 = receive all valid frames */ 154#define ETH_CFG_BR 0x0004U 155#define ETH_CFG_FD 0x0002U /* 1 = force full duplex */ 156#define ETH_CFG_SPD 0x0001U /* 1 = 100 Mbps */ 157 158#define GEM_CFG_GEN __BIT(10) 159#define GEM_CFG_CLK __BITS(20, 18) 160#define GEM_CFG_CLK_8 __SHIFTIN(0, GEM_CFG_CLK) 161#define GEM_CFG_CLK_16 __SHIFTIN(1, GEM_CFG_CLK) 162#define GEM_CFG_CLK_32 __SHIFTIN(2, GEM_CFG_CLK) 163#define GEM_CFG_CLK_48 __SHIFTIN(3, GEM_CFG_CLK) 164#define GEM_CFG_CLK_64 __SHIFTIN(4, GEM_CFG_CLK) 165#define GEM_CFG_CLK_96 __SHIFTIN(5, GEM_CFG_CLK) 166#define GEM_CFG_DBW __BITS(22, 21) 167#define GEM_CFG_RX_CHKSUM_OFFLD_EN __BIT(24) 168 169/* Status Register bits: */ 170#define ETH_SR_IDLE 0x0004U /* 1 = PHY logic is running */ 171#define ETH_SR_MDIO 0x0002U /* 1 = MDIO pin set */ 172#define ETH_SR_LINK 0x0001U 173 174 175/* Transmit Control Register bits: */ 176#define ETH_TCR_NCRC 0x8000U /* 1 = don't append CRC */ 177#define ETH_TCR_LEN 0x07FFU /* transmit frame length */ 178 179 180/* Transmit Status Register bits: */ 181#define ETH_TSR_UND 0x40U /* 1 = transmit underrun detected */ 182#define ETH_TSR_COMP 0x20U /* 1 = transmit complete */ 183#define ETH_TSR_BNQ 0x10U /* 1 = transmit buffer not queued (at91rm9200 only) */ 184#define ETH_TSR_IDLE 0x08U /* 1 = transmitter idle */ 185#define ETH_TSR_RLE 0x04U /* 1 = retry limit exceeded */ 186#define ETH_TSR_COL 0x02U /* 1 = collision occurred */ 187#define ETH_TSR_OVR 0x01U /* 1 = transmit buffer overrun */ 188 189#define GEM_TSR_TXGO __BIT(3) 190 191/* Receive Status Register bits: */ 192#define ETH_RSR_OVR 0x04U /* 1 = RX overrun */ 193#define ETH_RSR_REC 0x02U /* 1 = frame received */ 194#define ETH_RSR_BNA 0x01U /* 1 = buffer not available */ 195 196 197/* Interrupt bits: */ 198#define ETH_ISR_ABT 0x0800U /* 1 = abort during DMA transfer */ 199#define ETH_ISR_ROVR 0x0400U /* 1 = RX overrun */ 200#define ETH_ISR_LINK 0x0200U /* 1 = link pin changed */ 201#define ETH_ISR_TIDLE 0x0100U /* 1 = transmitter idle */ 202#define ETH_ISR_TCOM 0x0080U /* 1 = transmit complete */ 203#define ETH_ISR_TBRE 0x0040U /* 1 = transmit buffer register empty */ 204#define ETH_ISR_RTRY 0x0020U /* 1 = retry limit exceeded */ 205#define ETH_ISR_TUND 0x0010U /* 1 = transmit buffer underrun */ 206#define ETH_ISR_TOVR 0x0008U /* 1 = transmit buffer overrun */ 207#define ETH_ISR_RBNA 0x0004U /* 1 = receive buffer not available */ 208#define ETH_ISR_RCOM 0x0002U /* 1 = receive complete */ 209#define ETH_ISR_DONE 0x0001U /* 1 = management done */ 210 211 212/* PHY Maintenance Register bits: */ 213#define ETH_MAN_LOW 0x80000000U /* must not be set */ 214#define ETH_MAN_HIGH 0x40000000U /* must be set */ 215 216#define ETH_MAN_RW 0x30000000U 217#define ETH_MAN_RW_RD 0x20000000U 218#define ETH_MAN_RW_WR 0x10000000U 219 220#define ETH_MAN_PHYA 0x0F800000U /* PHY address (normally 0) */ 221#define ETH_MAN_PHYA_SHIFT 23U 222#define ETH_MAN_REGA 0x007C0000U 223#define ETH_MAN_REGA_SHIFT 18U 224#define ETH_MAN_CODE 0x00030000U /* must be 10 */ 225#define ETH_MAN_CODE_IEEE802_3 \ 226 0x00020000U 227#define ETH_MAN_DATA 0x0000FFFFU /* data to be written to the PHY */ 228 229#define ETH_MAN_VAL (ETH_MAN_HIGH|ETH_MAN_CODE_IEEE802_3) 230 231 232/* received buffer descriptor: */ 233#define ETH_DSC_ADDR 0x00U 234#define ETH_DSC_FLAGS 0x00U 235#define ETH_DSC_INFO 0x04U 236#define ETH_DSC_SIZE 0x08U 237 238typedef struct eth_dsc { 239 volatile uint32_t Addr; 240 volatile uint32_t Info; 241} __attribute__ ((aligned(4))) eth_dsc_t; 242 243/* flags: */ 244#define ETH_RDSC_F_WRAP 0x00000002U 245#define ETH_RDSC_F_USED 0x00000001U 246 247/* frame info bits: */ 248#define ETH_RDSC_I_BCAST __BIT(31) 249#define ETH_RDSC_I_MULTICAST __BIT(30) 250#define ETH_RDSC_I_UNICAST __BIT(29) 251#define ETH_RDSC_I_VLAN 0x10000000U 252#define ETH_RDSC_I_UNKNOWN_SRC 0x08000000U 253#define ETH_RDSC_I_MATCH1 0x04000000U 254#define ETH_RDSC_I_MATCH2 0x02000000U 255#define ETH_RDSC_I_MATCH3 0x01000000U 256#define ETH_RDSC_I_MATCH4 0x00800000U 257#define ETH_RDSC_I_CHKSUM __BITS(23, 22) 258#define ETH_RDSC_I_CHKSUM_NONE __SHIFTIN(0, ETH_RDSC_I_CHKSUM) 259#define ETH_RDSC_I_CHKSUM_IP __SHIFTIN(1, ETH_RDSC_I_CHKSUM) 260#define ETH_RDSC_I_CHKSUM_TCP __SHIFTIN(2, ETH_RDSC_I_CHKSUM) 261#define ETH_RDSC_I_CHKSUM_UDP __SHIFTIN(3, ETH_RDSC_I_CHKSUM) 262#define ETH_RDSC_I_LEN __BITS(13, 0) 263 264#define ETH_TDSC_I_USED __BIT(31) /* done transmitting */ 265#define ETH_TDSC_I_WRAP __BIT(30) /* end of descr ring */ 266#define ETH_TDSC_I_RETRY_ERR __BIT(29) 267#define ETH_TDSC_I_AHB_ERR __BIT(27) 268#define ETH_TDSC_I_LATE_COLL __BIT(26) 269#define ETH_TDSC_I_CHKSUM __BITS(22, 20) 270#define ETH_TDSC_I_CHKSUM_GEN_STAT_NO_ERR __SHIFTIN(0, ETH_TDSC_I_CHKSUM) 271#define ETH_TDSC_I_CHKSUM_GEN_STAT_VLAN_HDR_ERR __SHIFTIN(1, ETH_TDSC_I_CHKSUM) 272#define ETH_TDSC_I_CHKSUM_GEN_STAT_SNAP_HDR_ERR __SHIFTIN(2, ETH_TDSC_I_CHKSUM) 273#define ETH_TDSC_I_CHKSUM_GEN_STAT_IP_HDR_ERR __SHIFTIN(3, ETH_TDSC_I_CHKSUM) 274#define ETH_TDSC_I_CHKSUM_GEN_STAT_UNKNOWN_TYPE __SHIFTIN(4, ETH_TDSC_I_CHKSUM) 275#define ETH_TDSC_I_CHKSUM_GEN_STAT_UNSUPP_FRAG __SHIFTIN(5, ETH_TDSC_I_CHKSUM) 276#define ETH_TDSC_I_CHKSUM_GEN_STAT_NOT_TCPUDP __SHIFTIN(6, ETH_TDSC_I_CHKSUM) 277#define ETH_TDSC_I_CHKSUM_GEN_STAT_SHORT_PKT __SHIFTIN(7, ETH_TDSC_I_CHKSUM) 278#define ETH_TDSC_I_NO_CRC_APPENDED __BIT(16) 279#define ETH_TDSC_I_LAST_BUF __BIT(15) /* last buf in frame */ 280#define ETH_TDSC_I_LEN __BITS(13, 0) 281 282#endif /* !_IF_CEMACREG_H_ */ 283