Lines Matching refs:ETH_CTL
145 EMAC_WRITE(ETH_CTL, 0); // disable everything
240 ctl = EMAC_READ(ETH_CTL); // get current control register value
241 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
243 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
338 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
355 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);
480 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
700 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG));
717 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
734 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
767 uint32_t ctl = EMAC_READ(ETH_CTL);
771 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
871 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);