/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
H A D | base.c | 31 struct nvkm_gr *gr = device->gr; local 32 if (gr && gr->func->ctxsw.inst) 33 return gr->func->ctxsw.inst(gr); 40 struct nvkm_gr *gr = device->gr; local 41 if (gr && gr 49 struct nvkm_gr *gr = device->gr; local 58 struct nvkm_gr *gr = nvkm_gr(engine); local 67 struct nvkm_gr *gr = nvkm_gr(engine); local 73 nvkm_gr_units(struct nvkm_gr *gr) argument 81 nvkm_gr_tlb_flush(struct nvkm_gr *gr) argument 91 struct nvkm_gr *gr = nvkm_gr(oclass->engine); local 115 struct nvkm_gr *gr = nvkm_gr(oclass->engine); local 124 struct nvkm_gr *gr = nvkm_gr(engine); local 131 struct nvkm_gr *gr = nvkm_gr(engine); local 142 struct nvkm_gr *gr = nvkm_gr(engine); local 151 struct nvkm_gr *gr = nvkm_gr(engine); local 162 struct nvkm_gr *gr = nvkm_gr(engine); local 173 struct nvkm_gr *gr = nvkm_gr(engine); local 182 struct nvkm_gr *gr = nvkm_gr(engine); local 204 nvkm_gr_ctor(const struct nvkm_gr_func *func, struct nvkm_device *device, enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_gr *gr) argument [all...] |
H A D | ctxgm20b.c | 27 struct gf100_gr *gr = chan->gr; local 28 struct nvkm_device *device = gr->base.engine.subdev.device; 29 const struct gf100_grctx_func *grctx = gr->func->grctx; 33 gf100_gr_mmio(gr, gr->sw_ctx); 35 gf100_gr_wait_idle(gr); 39 grctx->attrib_cb(chan, chan->attrib_cb->addr, grctx->attrib_cb_size(gr)); 42 grctx->unkn(gr); 44 gf100_grctx_generate_floorsweep(gr); [all...] |
H A D | ctxgk20a.c | 30 struct gf100_gr *gr = chan->gr; local 31 struct nvkm_device *device = gr->base.engine.subdev.device; 32 const struct gf100_grctx_func *grctx = gr->func->grctx; 36 gf100_gr_mmio(gr, gr->sw_ctx); 38 gf100_gr_wait_idle(gr); 42 grctx->attrib_cb(chan, chan->attrib_cb->addr, grctx->attrib_cb_size(gr)); 45 grctx->unkn(gr); 47 gf100_grctx_generate_floorsweep(gr); [all...] |
H A D | ctxgm200.c | 31 gm200_grctx_generate_r419a3c(struct gf100_gr *gr) argument 33 struct nvkm_device *device = gr->base.engine.subdev.device; 38 gm200_grctx_generate_r418e94(struct gf100_gr *gr) argument 40 struct nvkm_device *device = gr->base.engine.subdev.device; 46 gm200_grctx_generate_smid_config(struct gf100_gr *gr) argument 48 struct nvkm_device *device = gr->base.engine.subdev.device; 49 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); 54 for (sm = 0; sm < gr->sm_nr; sm++) { 55 const u8 gpc = gr->sm[sm].gpc; 56 const u8 tpc = gr 68 gm200_grctx_generate_tpc_mask(struct gf100_gr *gr) argument 77 gm200_grctx_generate_r406500(struct gf100_gr *gr) argument 83 gm200_grctx_generate_dist_skip_table(struct gf100_gr *gr) argument [all...] |
H A D | gm200.c | 35 gm200_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) argument 37 nvkm_warn(&gr->base.engine.subdev, "firmware unavailable\n"); 92 gm200_gr_rops(struct gf100_gr *gr) argument 94 return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c); 98 gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr) argument 100 struct nvkm_device *device = gr->base.engine.subdev.device; 106 gm200_gr_init_num_active_ltcs(struct gf100_gr *gr) argument 108 struct nvkm_device *device = gr->base.engine.subdev.device; 114 gm200_gr_init_gpc_mmu(struct gf100_gr *gr) argument 116 struct nvkm_device *device = gr 128 gm200_gr_init_rop_active_fbps(struct gf100_gr *gr) argument 152 gm200_gr_oneinit_sm_id(struct gf100_gr *gr) argument 159 gm200_gr_oneinit_tiles(struct gf100_gr *gr) argument 222 gm200_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) argument [all...] |
H A D | gf100.c | 49 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) argument 51 struct nvkm_device *device = gr->base.engine.subdev.device; 52 if (gr->zbc_color[zbc].format) { 53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); 54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); 55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); 56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); 58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); 64 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, argument 67 struct nvkm_ltc *ltc = gr 100 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) argument 111 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, const u32 ds, const u32 l2) argument 163 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); local 209 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); local 301 struct gf100_gr *gr = gf100_gr(base); local 324 struct gf100_gr *gr = chan->gr; local 381 struct gf100_gr *gr = gf100_gr(base); local 744 gf100_gr_ctxsw_inst(struct nvkm_gr *gr) argument 750 gf100_gr_fecs_ctrl_ctxsw(struct gf100_gr *gr, u32 mthd) argument 772 struct gf100_gr *gr = gf100_gr(base); local 787 struct gf100_gr *gr = gf100_gr(base); local 800 gf100_gr_fecs_halt_pipeline(struct gf100_gr *gr) argument 814 gf100_gr_fecs_wfi_golden_save(struct gf100_gr *gr, u32 inst) argument 833 gf100_gr_fecs_bind_pointer(struct gf100_gr *gr, u32 inst) argument 852 gf100_gr_fecs_set_reglist_virtual_address(struct gf100_gr *gr, u64 addr) argument 869 gf100_gr_fecs_set_reglist_bind_instance(struct gf100_gr *gr, u32 inst) argument 886 gf100_gr_fecs_discover_reglist_image_size(struct gf100_gr *gr, u32 *psize) argument 902 gf100_gr_fecs_elpg_bind(struct gf100_gr *gr) argument 924 gf100_gr_fecs_discover_pm_image_size(struct gf100_gr *gr, u32 *psize) argument 940 gf100_gr_fecs_discover_zcull_image_size(struct gf100_gr *gr, u32 *psize) argument 956 gf100_gr_fecs_discover_image_size(struct gf100_gr *gr, u32 *psize) argument 972 gf100_gr_fecs_set_watchdog_timeout(struct gf100_gr *gr, u32 timeout) argument 984 struct gf100_gr *gr = gf100_gr(base); local 998 gf100_gr_rops(struct gf100_gr *gr) argument 1005 gf100_gr_zbc_init(struct gf100_gr *gr) argument 1049 gf100_gr_wait_idle(struct gf100_gr *gr) argument 1078 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) argument 1095 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) argument 1135 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) argument 1162 struct gf100_gr *gr = gf100_gr(base); local 1234 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) argument 1295 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) argument 1316 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) argument 1361 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) argument 1409 gf100_gr_trap_intr(struct gf100_gr *gr) argument 1535 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) argument 1554 gf100_gr_ctxctl_debug(struct gf100_gr *gr) argument 1566 gf100_gr_ctxctl_isr(struct gf100_gr *gr) argument 1608 struct gf100_gr *gr = container_of(inth, typeof(*gr), base.engine.subdev.inth); local 1707 gf100_gr_init_csdata(struct gf100_gr *gr, const struct gf100_gr_pack *pack, u32 falcon, u32 starstar, u32 base) argument 1750 gf100_gr_init_ctxctl_ext(struct gf100_gr *gr) argument 1831 gf100_gr_init_ctxctl_int(struct gf100_gr *gr) argument 1882 gf100_gr_init_ctxctl(struct gf100_gr *gr) argument 1895 gf100_gr_oneinit_sm_id(struct gf100_gr *gr) argument 1913 gf100_gr_oneinit_tiles(struct gf100_gr *gr) argument 1991 struct gf100_gr *gr = gf100_gr(base); local 2066 struct gf100_gr *gr = gf100_gr(base); local 2117 struct gf100_gr *gr = gf100_gr(base); local 2130 struct gf100_gr *gr = gf100_gr(base); local 2169 gf100_gr_init_num_tpc_per_gpc(struct gf100_gr *gr, bool pd, bool ds) argument 2186 gf100_gr_init_400054(struct gf100_gr *gr) argument 2192 gf100_gr_init_exception2(struct gf100_gr *gr) argument 2201 gf100_gr_init_rop_exceptions(struct gf100_gr *gr) argument 2215 gf100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) argument 2223 gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int gpc, int tpc) argument 2230 gf100_gr_init_419eb4(struct gf100_gr *gr) argument 2237 gf100_gr_init_419cc0(struct gf100_gr *gr) argument 2251 gf100_gr_init_40601c(struct gf100_gr *gr) argument 2257 gf100_gr_init_fecs_exceptions(struct gf100_gr *gr) argument 2264 gf100_gr_init_gpc_mmu(struct gf100_gr *gr) argument 2280 gf100_gr_init_num_active_ltcs(struct gf100_gr *gr) argument 2287 gf100_gr_init_zcull(struct gf100_gr *gr) argument 2315 gf100_gr_init_vsc_stream_master(struct gf100_gr *gr) argument 2326 struct gf100_gr *gr = gf100_gr(base); local 2342 gf100_gr_init(struct gf100_gr *gr) argument 2466 gf100_gr_fecs_reset(struct gf100_gr *gr) argument 2500 struct gf100_gr *gr = gf100_gr(base); local 2561 gf100_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) argument 2568 gf100_gr_load_fw(struct gf100_gr *gr, const char *name, struct nvkm_blob *blob) argument 2595 gf100_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) argument 2623 struct gf100_gr *gr; local [all...] |
H A D | gv100.c | 28 gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) argument 30 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 49 gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) argument 51 gv100_gr_trap_sm(gr, gpc, tpc, 0); 52 gv100_gr_trap_sm(gr, gpc, tpc, 1); 56 gv100_gr_init_4188a4(struct gf100_gr *gr) argument 58 struct nvkm_device *device = gr->base.engine.subdev.device; 64 gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) argument 66 struct nvkm_device *device = gr->base.engine.subdev.device; 75 gv100_gr_init_504430(struct gf100_gr *gr, in argument 82 gv100_gr_init_419bd8(struct gf100_gr *gr) argument 89 gv100_gr_nonpes_aware_tpc(struct gf100_gr *gr, u32 gpc, u32 tpc) argument 106 gv100_gr_scg_estimate_perf(struct gf100_gr *gr, unsigned long *gpc_tpc_mask, u32 disable_gpc, u32 disable_tpc, int *perf) argument 227 gv100_gr_oneinit_sm_id(struct gf100_gr *gr) argument [all...] |
H A D | gp100.c | 33 gp100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) argument 35 struct nvkm_device *device = gr->base.engine.subdev.device; 39 if (gr->zbc_color[zbc].format) { 40 nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]); 41 nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]); 42 nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]); 43 nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]); 48 gr->zbc_color[zbc].format << ((znum % 4) * 7)); 52 gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) argument 54 struct nvkm_device *device = gr 72 gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) argument 80 gp100_gr_init_419c9c(struct gf100_gr *gr) argument 88 gp100_gr_init_fecs_exceptions(struct gf100_gr *gr) argument 94 gp100_gr_init_rop_active_fbps(struct gf100_gr *gr) argument [all...] |
H A D | gk20a.c | 156 gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr) argument 158 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 181 gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr) argument 183 struct nvkm_device *device = gr->base.engine.subdev.device; 189 gk20a_gr_init(struct gf100_gr *gr) argument 191 struct nvkm_device *device = gr->base.engine.subdev.device; 197 gf100_gr_mmio(gr, gr->sw_nonctx); 199 ret = gk20a_gr_wait_mem_scrubbing(gr); 203 ret = gf100_gr_wait_idle(gr); 277 gk20a_gr_load_net(struct gf100_gr *gr, const char *path, const char *name, int ver, int (*load)(struct nvkm_blob *, struct gf100_gr_pack **), struct gf100_gr_pack **ppack) argument 294 gk20a_gr_load_sw(struct gf100_gr *gr, const char *path, int ver) argument 317 gk20a_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) argument [all...] |
H A D | ctxgp102.c | 33 gp102_grctx_generate_r408840(struct gf100_gr *gr) argument 35 struct nvkm_device *device = gr->base.engine.subdev.device; 42 struct gf100_gr *gr = chan->gr; local 43 const struct gf100_grctx_func *grctx = gr->func->grctx; 48 u32 size = grctx->alpha_nr_max * gr->tpc_total; 57 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 58 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) { 59 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; 60 const u32 bs = attrib * gr 86 gp102_grctx_generate_attrib_cb_size(struct gf100_gr *gr) argument [all...] |
H A D | gp102.c | 30 gp102_gr_zbc_clear_stencil(struct gf100_gr *gr, int zbc) argument 32 struct nvkm_device *device = gr->base.engine.subdev.device; 36 if (gr->zbc_stencil[zbc].format) 37 nvkm_wr32(device, 0x41815c + zoff, gr->zbc_stencil[zbc].ds); 40 gr->zbc_stencil[zbc].format << ((znum % 4) * 7)); 44 gp102_gr_zbc_stencil_get(struct gf100_gr *gr, int format, argument 47 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 51 if (gr->zbc_stencil[i].format) { 52 if (gr->zbc_stencil[i].format != format) 54 if (gr 86 gp102_gr_init_swdx_pes_mask(struct gf100_gr *gr) argument [all...] |
H A D | r535.c | 63 struct r535_gr *gr; member in struct:r535_gr_chan 112 struct r535_gr *gr = grc->gr; local 114 for (int i = 0; i < gr->ctxbuf_nr; i++) { 129 r535_gr_promote_ctx(struct r535_gr *gr, bool golden, struct nvkm_vmm *vmm, argument 133 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 146 for (int i = 0; i < gr->ctxbuf_nr; i++) { 149 const bool alloc = golden || !gr->ctxbuf[i].global; 152 entry->bufferId = gr->ctxbuf[i].bufferId; 153 entry->bInitialize = gr 215 struct r535_gr *gr = r535_gr(base); local 236 r535_gr_units(struct nvkm_gr *gr) argument 247 struct r535_gr *gr = container_of(base, typeof(*gr), base); local 466 struct r535_gr *gr = r535_gr(base); local 480 struct r535_gr *gr; local [all...] |
H A D | ctxga102.c | 25 ga102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) argument 27 struct nvkm_device *device = gr->base.engine.subdev.device; 29 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc); 35 ga102_grctx_generate_unkn(struct gf100_gr *gr) argument 37 struct nvkm_device *device = gr->base.engine.subdev.device; 44 ga102_grctx_generate_r419ea8(struct gf100_gr *gr) argument 46 struct nvkm_device *device = gr->base.engine.subdev.device;
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H A D | tu102.c | 30 tu102_gr_init_fecs_exceptions(struct gf100_gr *gr) argument 32 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006e0003); 36 tu102_gr_init_fs(struct gf100_gr *gr) argument 38 struct nvkm_device *device = gr->base.engine.subdev.device; 41 gp100_grctx_generate_smid_config(gr); 42 gk104_grctx_generate_gpc_tpc_nr(gr); 44 for (sm = 0; sm < gr->sm_nr; sm++) { 45 int tpc = gv100_gr_nonpes_aware_tpc(gr, gr->sm[sm].gpc, gr 55 tu102_gr_init_zcull(struct gf100_gr *gr) argument 83 tu102_gr_init_gpc_mmu(struct gf100_gr *gr) argument [all...] |
H A D | ctxgv100.c | 64 struct gf100_gr *gr = chan->gr; local 65 const struct gf100_grctx_func *grctx = gr->func->grctx; 70 u32 size = grctx->alpha_nr_max * gr->tpc_total; 79 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 80 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) { 81 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; 82 const u32 bs = attrib * gr->ppc_tpc_max; 83 const u32 gs = gfxp * gr->ppc_tpc_max; 87 if (!(gr 115 gv100_grctx_generate_rop_mapping(struct gf100_gr *gr) argument 153 gv100_grctx_generate_r400088(struct gf100_gr *gr, bool on) argument 160 gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) argument 172 gv100_grctx_generate_unkn(struct gf100_gr *gr) argument 183 gv100_grctx_unkn88c(struct gf100_gr *gr, bool on) argument [all...] |
H A D | ga102.c | 36 ga102_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) argument 38 struct nvkm_device *device = gr->base.engine.subdev.device; 41 if (gr->zbc_color[zbc].format) 42 color = gr->zbc_color[zbc].l2; 62 ga102_gr_gpccs_reset(struct gf100_gr *gr) argument 64 struct nvkm_device *device = gr->base.engine.subdev.device; 81 ga102_gr_fecs_reset(struct gf100_gr *gr) argument 83 struct nvkm_device *device = gr->base.engine.subdev.device; 104 ga102_gr_init_rop_exceptions(struct gf100_gr *gr) argument 106 struct nvkm_device *device = gr 114 ga102_gr_init_40a790(struct gf100_gr *gr) argument 120 ga102_gr_init_gpc_mmu(struct gf100_gr *gr) argument 133 ga102_gr_oneinit_intr(struct gf100_gr *gr, enum nvkm_intr_type *pvector) argument 142 ga102_gr_nonstall(struct gf100_gr *gr) argument 272 ga102_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) argument [all...] |
H A D | ctxgp100.c | 44 struct gf100_gr *gr = chan->gr; local 45 const struct gf100_grctx_func *grctx = gr->func->grctx; 49 u32 size = grctx->alpha_nr_max * gr->tpc_total; 58 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 59 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) { 60 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; 61 const u32 bs = attrib * gr->ppc_tpc_max; 65 if (!(gr->ppc_mask[gpc] & (1 << ppc))) 71 bo += grctx->attrib_nr_max * gr 93 gp100_grctx_generate_attrib_cb_size(struct gf100_gr *gr) argument 106 gp100_grctx_generate_smid_config(struct gf100_gr *gr) argument [all...] |
H A D | ctxgf117.c | 188 gf117_grctx_generate_dist_skip_table(struct gf100_gr *gr) argument 190 struct nvkm_device *device = gr->base.engine.subdev.device; 198 gf117_grctx_generate_rop_mapping(struct gf100_gr *gr) argument 200 struct nvkm_device *device = gr->base.engine.subdev.device; 207 data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5); 211 ntpcv = gr->tpc_total; 224 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | 225 gr->screen_tile_row_offset); 230 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | 231 gr 246 struct gf100_gr *gr = chan->gr; local [all...] |
H A D | gf117.c | 124 gf117_gr_init_zcull(struct gf100_gr *gr) argument 126 struct nvkm_device *device = gr->base.engine.subdev.device; 127 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); 129 const u8 tile_nr = !gr->func->gpc_nr ? ALIGN(gr->tpc_total, 32) : 130 (gr->func->gpc_nr * gr->func->tpc_nr); 135 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { 136 data |= bank[gr->tile[i + j]] << (j * 4); 137 bank[gr [all...] |
H A D | nv10.c | 401 struct nv10_gr *gr; member in struct:nv10_gr_chan 414 #define PIPE_SAVE(gr, state, addr) \ 422 #define PIPE_RESTORE(gr, state, addr) \ 434 struct nvkm_gr *gr = &chan->gr->base; local 445 nv04_gr_idle(gr); 452 nv04_gr_idle(gr); 462 nv04_gr_idle(gr); 485 nv04_gr_idle(gr); 500 nv04_gr_idle(gr); 507 struct nvkm_gr *gr = &chan->gr->base; local 547 nv10_gr_channel(struct nv10_gr *gr) argument 562 struct nv10_gr *gr = chan->gr; local 581 struct nv10_gr *gr = chan->gr; local 632 struct nv10_gr *gr = chan->gr; local 786 nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) argument 799 nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) argument 814 struct nv10_gr *gr = chan->gr; local 885 struct nv10_gr *gr = chan->gr; local 912 struct nv10_gr *gr = chan->gr; local 932 nv10_gr_context_switch(struct nv10_gr *gr) argument 957 struct nv10_gr *gr = chan->gr; local 974 struct nv10_gr *gr = chan->gr; local 1005 struct nv10_gr *gr = nv10_gr(base); local 1051 struct nv10_gr *gr = nv10_gr(base); local 1083 struct nv10_gr *gr = nv10_gr(base); local 1138 struct nv10_gr *gr = nv10_gr(base); local 1178 struct nv10_gr *gr; local [all...] |
/linux-master/arch/parisc/kernel/ |
H A D | kgdb.c | 65 struct parisc_gdb_regs *gr = (struct parisc_gdb_regs *)gdb_regs; local 67 memset(gr, 0, sizeof(struct parisc_gdb_regs)); 69 memcpy(gr->gpr, regs->gr, sizeof(gr->gpr)); 70 memcpy(gr->fr, regs->fr, sizeof(gr->fr)); 72 gr->sr0 = regs->sr[0]; 73 gr->sr1 = regs->sr[1]; 74 gr 97 struct parisc_gdb_regs *gr = (struct parisc_gdb_regs *)gdb_regs; local [all...] |
H A D | ptrace.c | 165 task_regs(child)->gr[0] &= ~USER_PSW_BITS; 166 task_regs(child)->gr[0] |= data; 231 * the gr registers at the start of pt_regs. The 32 bit pt_regs should 240 if (offset < 32*4) /* gr[0..31] */ 335 regs->gr[28] = -ENOSYS; 345 * regs->gr[20] to an invalid syscall number, 348 regs->gr[20] = -1UL; 359 trace_sys_enter(regs, regs->gr[20]); 364 audit_syscall_entry(regs->gr[20], regs->gr[2 [all...] |
/linux-master/arch/parisc/include/asm/ |
H A D | syscall.h | 17 return regs->gr[20]; 24 args[5] = regs->gr[21]; 25 args[4] = regs->gr[22]; 26 args[3] = regs->gr[23]; 27 args[2] = regs->gr[24]; 28 args[1] = regs->gr[25]; 29 args[0] = regs->gr[26]; 35 unsigned long error = regs->gr[28]; 42 return regs->gr[28]; 49 regs->gr[2 [all...] |
/linux-master/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ |
H A D | ia_css_wb_types.h | 33 u32 gr; /** Significand of Gr gain. member in struct:ia_css_wb_config
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/linux-master/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ |
H A D | ia_css_dp_types.h | 43 u32 gr; /* unsigned <integer_bits>.<16-integer_bits> */ member in struct:ia_css_dp_config
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