engine/gr/gk20a.c

156 gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
158 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
181 gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
183 	struct nvkm_device *device = gr->base.engine.subdev.device;
189 gk20a_gr_init(struct gf100_gr *gr)
191 	struct nvkm_device *device = gr->base.engine.subdev.device;
197 	gf100_gr_mmio(gr, gr->sw_nonctx);
199 	ret = gk20a_gr_wait_mem_scrubbing(gr);
203 	ret = gf100_gr_wait_idle(gr);
208 	if (gr->func->init_gpc_mmu)
209 		gr->func->init_gpc_mmu(gr);
215 	gr->func->init_zcull(gr);
217 	gr->func->init_rop_active_fbps(gr);
233 	if (gr->func->set_hww_esr_report_mask)
234 		gr->func->set_hww_esr_report_mask(gr);
238 	nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
248 	gf100_gr_zbc_init(gr);
250 	return gf100_gr_init_ctxctl(gr);
277 gk20a_gr_load_net(struct gf100_gr *gr, const char *path, const char *name, int ver,
284 	ret = nvkm_firmware_load_blob(&gr->base.engine.subdev, path, name, ver, &blob);
294 gk20a_gr_load_sw(struct gf100_gr *gr, const char *path, int ver)
296 	if (gk20a_gr_load_net(gr, path, "sw_nonctx", ver, gk20a_gr_av_to_init, &gr->sw_nonctx) ||
297 	    gk20a_gr_load_net(gr, path, "sw_ctx", ver, gk20a_gr_aiv_to_init, &gr->sw_ctx) ||
298 	    gk20a_gr_load_net(gr, path, "sw_bundle_init", ver, gk20a_gr_av_to_init, &gr->bundle) ||
299 	    gk20a_gr_load_net(gr, path, "sw_method_init", ver, gk20a_gr_av_to_method, &gr->method))
317 gk20a_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
319 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
322 				    &gr->fecs.inst) ||
324 				    &gr->fecs.data) ||
326 				    &gr->gpccs.inst) ||
328 				    &gr->gpccs.data))
331 	gr->firmware = true;
333 	return gk20a_gr_load_sw(gr, "", ver);