1/*
2 * Copyright 2015 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24#include "ctxgf100.h"
25
26/*******************************************************************************
27 * PGRAPH context implementation
28 ******************************************************************************/
29
30void
31gm200_grctx_generate_r419a3c(struct gf100_gr *gr)
32{
33	struct nvkm_device *device = gr->base.engine.subdev.device;
34	nvkm_mask(device, 0x419a3c, 0x00000014, 0x00000000);
35}
36
37static void
38gm200_grctx_generate_r418e94(struct gf100_gr *gr)
39{
40	struct nvkm_device *device = gr->base.engine.subdev.device;
41	nvkm_mask(device, 0x418e94, 0xffffffff, 0xc4230000);
42	nvkm_mask(device, 0x418e4c, 0xffffffff, 0x70000000);
43}
44
45void
46gm200_grctx_generate_smid_config(struct gf100_gr *gr)
47{
48	struct nvkm_device *device = gr->base.engine.subdev.device;
49	const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
50	u32 dist[TPC_MAX / 4] = {};
51	u32 gpcs[GPC_MAX] = {};
52	u8  sm, i;
53
54	for (sm = 0; sm < gr->sm_nr; sm++) {
55		const u8 gpc = gr->sm[sm].gpc;
56		const u8 tpc = gr->sm[sm].tpc;
57		dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8);
58		gpcs[gpc] |= sm << (tpc * 8);
59	}
60
61	for (i = 0; i < dist_nr; i++)
62		nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]);
63	for (i = 0; i < gr->gpc_nr; i++)
64		nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]);
65}
66
67void
68gm200_grctx_generate_tpc_mask(struct gf100_gr *gr)
69{
70	u32 tmp, i;
71	for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
72		tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * gr->func->tpc_nr);
73	nvkm_wr32(gr->base.engine.subdev.device, 0x4041c4, tmp);
74}
75
76void
77gm200_grctx_generate_r406500(struct gf100_gr *gr)
78{
79	nvkm_wr32(gr->base.engine.subdev.device, 0x406500, 0x00000000);
80}
81
82void
83gm200_grctx_generate_dist_skip_table(struct gf100_gr *gr)
84{
85	struct nvkm_device *device = gr->base.engine.subdev.device;
86	u32 data[8] = {};
87	int gpc, ppc, i;
88
89	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
90		for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) {
91			u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc];
92			u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc];
93			while (ppc_tpcs-- > gr->ppc_tpc_min)
94				ppc_tpcm &= ppc_tpcm - 1;
95			ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc];
96			((u8 *)data)[gpc] |= ppc_tpcm;
97		}
98	}
99
100	for (i = 0; i < ARRAY_SIZE(data); i++)
101		nvkm_wr32(device, 0x4064d0 + (i * 0x04), data[i]);
102}
103
104const struct gf100_grctx_func
105gm200_grctx = {
106	.main  = gf100_grctx_generate_main,
107	.unkn  = gk104_grctx_generate_unkn,
108	.bundle = gm107_grctx_generate_bundle,
109	.bundle_size = 0x3000,
110	.bundle_min_gpm_fifo_depth = 0x180,
111	.bundle_token_limit = 0x780,
112	.pagepool = gm107_grctx_generate_pagepool,
113	.pagepool_size = 0x20000,
114	.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
115	.attrib_cb = gm107_grctx_generate_attrib_cb,
116	.attrib = gm107_grctx_generate_attrib,
117	.attrib_nr_max = 0x600,
118	.attrib_nr = 0x400,
119	.alpha_nr_max = 0x1800,
120	.alpha_nr = 0x1000,
121	.sm_id = gm107_grctx_generate_sm_id,
122	.rop_mapping = gf117_grctx_generate_rop_mapping,
123	.dist_skip_table = gm200_grctx_generate_dist_skip_table,
124	.r406500 = gm200_grctx_generate_r406500,
125	.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
126	.tpc_mask = gm200_grctx_generate_tpc_mask,
127	.smid_config = gm200_grctx_generate_smid_config,
128	.r418e94 = gm200_grctx_generate_r418e94,
129	.r419a3c = gm200_grctx_generate_r419a3c,
130};
131