/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64StorePairSuppress.cpp | 152 bool OffsetIsScalable; local 153 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
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H A D | AArch64InstrInfo.h | 118 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 121 /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`. 127 int64_t &Offset, bool &OffsetIsScalable,
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H A D | AArch64InstrInfo.cpp | 2052 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 2058 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, 2067 bool &OffsetIsScalable, unsigned &Width, 2105 OffsetIsScalable = Scale.isScalable(); 6075 bool OffsetIsScalable; 6079 if (!getMemOperandWithOffset(MI, Base, Offset, OffsetIsScalable, &TRI) || 6084 if (OffsetIsScalable) 6496 bool OffsetIsScalable; 6500 !getMemOperandWithOffsetWidth(MI, Base, Offset, OffsetIsScalable, Width, 6513 assert(!OffsetIsScalable 2050 getMemOperandsWithOffsetWidth( const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const argument 2065 getMemOperandWithOffsetWidth( const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiInstrInfo.h | 73 bool &OffsetIsScalable, unsigned &Width,
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H A D | LanaiInstrInfo.cpp | 800 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 815 OffsetIsScalable = false; 798 getMemOperandsWithOffsetWidth( const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ImplicitNullChecks.cpp | 367 bool OffsetIsScalable; local 371 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI) || 376 if (OffsetIsScalable)
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H A D | TargetInstrInfo.cpp | 1046 bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const { 1049 if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable, 1154 bool OffsetIsScalable; local 1198 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, 1203 if (OffsetIsScalable) 1044 getMemOperandWithOffset( const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const argument
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H A D | MachineSink.cpp | 774 bool OffsetIsScalable; local 775 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI))
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H A D | ModuloSchedule.cpp | 917 bool OffsetIsScalable; local 918 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) 922 if (OffsetIsScalable)
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H A D | MachinePipeliner.cpp | 2142 bool OffsetIsScalable; local 2143 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) 2147 if (OffsetIsScalable)
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H A D | MachineScheduler.cpp | 1573 bool OffsetIsScalable; local 1576 OffsetIsScalable, Width, TRI)) { 1580 << Offset << ", OffsetIsScalable: " << OffsetIsScalable
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 210 bool &OffsetIsScalable, unsigned &Width,
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H A D | HexagonInstrInfo.cpp | 2972 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 2974 OffsetIsScalable = false; 2970 getMemOperandsWithOffsetWidth( const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 323 bool &OffsetIsScalable, unsigned &Width,
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H A D | X86InstrInfo.cpp | 3667 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 3699 OffsetIsScalable = false; 3665 getMemOperandsWithOffsetWidth( const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetInstrInfo.h | 1248 bool &OffsetIsScalable, 1259 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 1257 getMemOperandsWithOffsetWidth( const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineScheduler.cpp | 1954 bool OffsetIsScalable; local 1956 OffsetIsScalable, TRI))
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H A D | SIInstrInfo.h | 190 bool &OffsetIsScalable, unsigned &Width,
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H A D | SIInstrInfo.cpp | 273 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 279 OffsetIsScalable = false; 271 getMemOperandsWithOffsetWidth( const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const argument
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