Searched refs:tile (Results 1 - 25 of 138) sorted by path

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/linux-master/arch/arm/include/debug/
H A Dvexpress.S26 @ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
/linux-master/drivers/accel/ivpu/
H A Divpu_hw_37xx.c23 #define WP_CONFIG(tile, ratio) (((tile) << 8) | (ratio))
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c994 uint32_t *tile, *macrotile; local
996 tile = adev->gfx.config.tile_mode_array;
1013 tile[reg_offset] = 0;
1019 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1023 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1027 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1031 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1035 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1039 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1042 tile[
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/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu14_driver_if_v14_0_0.h225 //ISP tile definitions
242 #define ISP_TILE_SEL(tile) (1<<tile)
/linux-master/drivers/gpu/drm/
H A Ddrm_connector.c1208 * Connector tile group property to indicate how a set of DRM connector
2323 * drm_connector_set_path_property - set tile property on connector
2352 * drm_connector_set_tile_property - set tile property on connector
2355 * This looks up the tile information for a connector, and creates a
2367 char tile[256]; local
2380 snprintf(tile, 256, "%d:%d:%d:%d:%d:%d:%d:%d",
2388 strlen(tile) + 1,
2389 tile,
3101 * we store this in a tile group, so we have a common identifier for all tiles
3102 * in a monitor group. The property is called "TILE". Drivers can manage tile
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H A Ddrm_edid.c6895 * Since we also parse tile information from EDID's displayID block, we also
6896 * set the connector's tile property here. See drm_connector_set_tile_property()
7272 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; local
7278 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7279 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7281 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7282 num_h_tile = (tile
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/linux-master/drivers/gpu/drm/exynos/
H A Dexynos_drm_scaler.c144 u32 src_fmt, u32 tile)
148 val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10);
143 scaler_set_src_fmt(struct scaler_context *scaler, u32 src_fmt, u32 tile) argument
/linux-master/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_mman.c30 struct tile { struct
44 static u64 tiled_offset(const struct tile *tile, u64 v) argument
48 if (tile->tiling == I915_TILING_NONE)
51 y = div64_u64_rem(v, tile->stride, &x);
52 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height;
54 if (tile->tiling == I915_TILING_X) {
55 v += y * tile
92 check_partial_mapping(struct drm_i915_gem_object *obj, const struct tile *tile, struct rnd_state *prng) argument
185 check_partial_mappings(struct drm_i915_gem_object *obj, const struct tile *tile, unsigned long end_time) argument
290 setup_tile_size(struct tile *tile, struct drm_i915_private *i915) argument
352 struct tile tile; local
370 struct tile tile; local
489 struct tile tile; local
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/linux-master/drivers/gpu/drm/i915/gvt/
H A Dcmd_parser.c1392 u32 stride, tile; local
1399 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1404 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1410 if (tile != info->tile_val)
1411 gvt_dbg_cmd("cannot change tile during async flip\n");
/linux-master/drivers/gpu/drm/imx/dcss/
H A Ddcss-dpr.c98 enum dcss_tile_type tile; member in struct:dcss_dpr_ch
197 pix_in_64byte = pix_in_64byte_map[ch->pix_size][ch->tile];
466 ch->tile = TILE_LINEAR;
469 ch->tile = TILE_GPU_STANDARD;
472 ch->tile = TILE_GPU_SUPER;
481 ch->tile = TILE_LINEAR;
489 ch->mode_ctrl |= ((ch->tile << TILE_TYPE_POS) & TILE_TYPE_MASK);
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dengine.h27 void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *); member in struct:nvkm_engine_func
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dfb.h54 } tile; member in struct:nvkm_fb
/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_bo.c60 int i = reg - drm->tile.reg;
62 struct nvkm_fb_tile *tile = &fb->tile.region[i]; local
66 if (tile->pitch)
67 nvkm_fb_tile_fini(fb, i, tile);
70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
72 nvkm_fb_tile_prog(fb, i, tile);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; local
81 spin_lock(&drm->tile
94 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, struct dma_fence *fence) argument
113 struct nouveau_drm_tile *tile, *found = NULL; local
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H A Dnouveau_bo.h47 struct nouveau_drm_tile *tile; member in struct:nouveau_bo
H A Dnouveau_drm.c615 spin_lock_init(&drm->tile.lock);
H A Dnouveau_drv.h274 } tile; member in struct:nouveau_drm
/linux-master/drivers/gpu/drm/nouveau/nvkm/core/
H A Dengine.c77 if (engine->func->tile)
78 engine->func->tile(engine, region, &fb->tile.region[region]);
119 for (i = 0; fb && i < fb->tile.regions; i++)
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dbase.c65 nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) argument
68 if (gr->func->tile)
69 gr->func->tile(gr, region, tile);
197 .tile = nvkm_gr_tile,
H A Dctxgf100.c1100 /* Pack tile map into register format. */
1102 data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5);
H A Dctxgf117.c205 /* Pack tile map into register format. */
207 data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5);
H A Dctxgv100.c122 /* Pack tile map into register format. */
127 data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5);
H A Dgf100.c1961 /* Determine tile->GPC mapping */
1979 gr->tile[i++] = gpc_map[j];
2057 memset(gr->tile, 0xff, sizeof(gr->tile));
2297 data |= bank[gr->tile[i + j]] << (j * 4);
2298 bank[gr->tile[i + j]]++;
H A Dgf100.h124 u8 tile[TPC_MAX]; member in struct:gf100_gr
H A Dgf117.c136 data |= bank[gr->tile[i + j]] << (j * 4);
137 bank[gr->tile[i + j]]++;
H A Dgm200.c168 memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total);
172 memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total);
176 memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total);

Completed in 370 milliseconds

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