Searched refs:setting (Results 1 - 25 of 104) sorted by path

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/linux-master/arch/m68k/fpsp040/
H A Dsgetem.S80 fmovel %d0,%fpcr |this fpcr setting is used by the 882
/linux-master/arch/m68k/ifpsp060/src/
H A Dfpsp.S11675 # save setting this until now because this is where fmul_may_ovfl may jump in
12817 # emulated by simply setting sign bit. Sgl/dbl operands must be scaled #
13224 # For zeroes/infs/NANs, return the same while setting the FPSR #
13330 # For zeroes/infs/NANs, return the same while setting the FPSR #
14035 # save setting this until now because this is where fsglmul_may_ovfl may jump in
16165 # then the SNAN is converted to a nonsignalling NAN (by setting the #
16335 # and are incapable of setting the BSUN exception bit. #
16963 # and are incapable of setting the BSUN exception bit. #
17533 # and are incapable of setting the BSUN exception bit. #
H A Dilsp.S198 # it was a divs.l, so ccode setting is a little more complicated...
/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-asxx-defs.h65 uint64_t setting:5; member in struct:cvmx_asxx_gmii_rx_clk_set::cvmx_asxx_gmii_rx_clk_set_s
67 uint64_t setting:5;
78 uint64_t setting:5; member in struct:cvmx_asxx_gmii_rx_dat_set::cvmx_asxx_gmii_rx_dat_set_s
80 uint64_t setting:5;
159 uint64_t setting:5; member in struct:cvmx_asxx_mii_rx_dat_set::cvmx_asxx_mii_rx_dat_set_s
161 uint64_t setting:5;
213 uint64_t setting:5; member in struct:cvmx_asxx_rld_bypass_setting::cvmx_asxx_rld_bypass_setting_s
215 uint64_t setting:5;
336 uint64_t setting:5; member in struct:cvmx_asxx_rld_setting::cvmx_asxx_rld_setting_s
338 uint64_t setting
349 uint64_t setting:5; member in struct:cvmx_asxx_rld_setting::cvmx_asxx_rld_setting_cn38xx
362 uint64_t setting:5; member in struct:cvmx_asxx_rx_clk_setx::cvmx_asxx_rx_clk_setx_s
449 uint64_t setting:5; member in struct:cvmx_asxx_tx_clk_setx::cvmx_asxx_tx_clk_setx_s
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H A Dcvmx-mio-defs.h2569 uint64_t setting:17; member in struct:cvmx_mio_pll_setting::cvmx_mio_pll_setting_s
2571 uint64_t setting:17;
/linux-master/arch/sparc/lib/
H A DM7memcpy.S447 ! before we finish setting it, while minimizing the effects on
H A DM7memset.S49 * In the main loop, continue pre-setting the first long
51 * setting the other seven long words (56 bytes) of each
222 ! setting the first long word of each cache line in advance
/linux-master/drivers/net/ethernet/mellanox/mlx4/
H A Den_dcb_nl.c125 u8 *setting)
129 *setting = priv->cee_config.dcb_pfc[priority];
133 u8 setting)
137 priv->cee_config.dcb_pfc[priority] = setting;
207 en_err(priv, "Failed setting pause params\n");
435 en_err(priv, "Failed setting pause params\n");
124 mlx4_en_dcbnl_get_pfc_cfg(struct net_device *netdev, int priority, u8 *setting) argument
132 mlx4_en_dcbnl_set_pfc_cfg(struct net_device *netdev, int priority, u8 setting) argument
/linux-master/include/linux/mlx4/
H A Dcmd.h316 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting);
/linux-master/arch/arm/common/
H A Dmcpm_head.S145 @ power_up_setup is now responsible for setting up the cluster:
/linux-master/arch/arm/mm/
H A Dproc-xsc3.S470 and r0, r0, #2 @ preserve bit P bit setting
/linux-master/arch/mips/kernel/
H A Dentry.S48 # interrupt setting need_resched
/linux-master/arch/x86/kernel/
H A Dhead_32.S6 * Enhanced CPU detection and feature setting code by Mike Jagdis
179 jz .Lenable_paging # hw disallowed setting of ID bit
/linux-master/drivers/clk/meson/
H A Dclk-dualdiv.c52 struct meson_clk_dualdiv_param setting; local
54 setting.dual = meson_parm_read(clk->map, &dualdiv->dual);
55 setting.n1 = meson_parm_read(clk->map, &dualdiv->n1) + 1;
56 setting.m1 = meson_parm_read(clk->map, &dualdiv->m1) + 1;
57 setting.n2 = meson_parm_read(clk->map, &dualdiv->n2) + 1;
58 setting.m2 = meson_parm_read(clk->map, &dualdiv->m2) + 1;
60 return __dualdiv_param_to_rate(parent_rate, &setting);
94 const struct meson_clk_dualdiv_param *setting; local
96 setting = __dualdiv_get_setting(req->rate, req->best_parent_rate,
98 if (setting)
113 const struct meson_clk_dualdiv_param *setting = local
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/linux-master/drivers/cxl/
H A Dpci.c637 static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting) argument
642 if (FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting) != CXL_INT_MSI_MSIX)
646 FIELD_GET(CXLDEV_EVENT_INT_MSGNUM_MASK, setting));
738 static bool cxl_event_int_is_fw(u8 setting) argument
740 u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting);
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu72.h662 uint16_t setting; member in struct:SMU_ClockStretcherDataTableEntry
675 uint8_t setting; member in struct:SMU_CKS_LOOKUPTableEntry
H A Dsmu73.h647 uint16_t setting; member in struct:SMU_ClockStretcherDataTableEntry
660 uint8_t setting; member in struct:SMU_CKS_LOOKUPTableEntry
H A Dsmu74.h728 uint16_t setting; member in struct:SMU_ClockStretcherDataTableEntry
741 uint8_t setting; member in struct:SMU_CKS_LOOKUPTableEntry
H A Dsmu75.h611 uint16_t setting; member in struct:SMU_ClockStretcherDataTableEntry
624 uint8_t setting; member in struct:SMU_CKS_LOOKUPTableEntry
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dci_smumgr.c2063 "Failed to populate VRConfig setting!", return result);
2766 struct profile_mode_setting *setting; local
2782 setting = (struct profile_mode_setting *)profile_setting;
2784 if (setting->bupdate_sclk) {
2789 cpu_to_be16(setting->sclk_activity)) {
2790 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2800 if (levels[i].UpH != setting->sclk_up_hyst ||
2801 levels[i].DownH != setting->sclk_down_hyst) {
2802 levels[i].UpH = setting->sclk_up_hyst;
2803 levels[i].DownH = setting
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H A Dfiji_smumgr.c1764 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1766 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1803 ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
1807 ClockStretcherDataTableEntry[i].setting);
2033 "Failed to populate VRConfig setting!", return result);
2554 struct profile_mode_setting *setting; local
2570 setting = (struct profile_mode_setting *)profile_setting;
2572 if (setting->bupdate_sclk) {
2577 cpu_to_be16(setting->sclk_activity)) {
2578 levels[i].ActivityLevel = cpu_to_be16(setting
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H A Dpolaris10_smumgr.c187 pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
2036 "Failed to populate VRConfig setting!", return result);
2592 struct profile_mode_setting *setting; local
2608 setting = (struct profile_mode_setting *)profile_setting;
2610 if (setting->bupdate_sclk) {
2615 cpu_to_be16(setting->sclk_activity)) {
2616 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2626 if (levels[i].UpHyst != setting->sclk_up_hyst ||
2627 levels[i].DownHyst != setting->sclk_down_hyst) {
2628 levels[i].UpHyst = setting
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H A Dtonga_smumgr.c1693 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1695 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1730 ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
1734 ClockStretcherDataTableEntry[i].setting);
2356 "Failed to populate VRConfig setting !", return result);
3153 struct profile_mode_setting *setting; local
3169 setting = (struct profile_mode_setting *)profile_setting;
3171 if (setting->bupdate_sclk) {
3176 cpu_to_be16(setting->sclk_activity)) {
3177 levels[i].ActivityLevel = cpu_to_be16(setting
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/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c1243 enum SMU_11_0_ODSETTING_ID setting,
1247 *min = od_table->min[setting];
1249 *max = od_table->max[setting];
2436 enum SMU_11_0_ODSETTING_ID setting,
2439 if (value < od_table->min[setting]) {
2440 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2443 if (value > od_table->max[setting]) {
2444 dev_warn(smu->adev->dev, "OD setting (
1242 navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t *min, uint32_t *max) argument
2434 navi10_od_setting_check_range(struct smu_context *smu, struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value) argument
[all...]
H A Dsienna_cichlid_ppt.c1265 enum SMU_11_0_7_ODSETTING_ID setting,
1269 *min = od_table->min[setting];
1271 *max = od_table->max[setting];
2214 enum SMU_11_0_7_ODSETTING_ID setting,
2217 if (value < od_table->min[setting]) {
2218 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2219 setting, value, od_table->min[setting]);
2222 if (value > od_table->max[setting]) {
2223 dev_warn(smu->adev->dev, "OD setting (
1264 sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, enum SMU_11_0_7_ODSETTING_ID setting, uint32_t *min, uint32_t *max) argument
2212 sienna_cichlid_od_setting_check_range(struct smu_context *smu, struct smu_11_0_7_overdrive_table *od_table, enum SMU_11_0_7_ODSETTING_ID setting, uint32_t value) argument
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