/haiku/headers/os/drivers/ |
H A D | bios.h | 60 status_t (*interrupt)(bios_state* state, uint8 vector, bios_regs* regs);
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/haiku/headers/posix/ |
H A D | setjmp.h | 17 __jmp_buf regs; /* saved registers, stack & program pointer */ member in struct:__jmp_buf_tag
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/haiku/headers/private/graphics/matrox/ |
H A D | mga_macros.h | 308 #define MGA_REG8(r_) ((vuint8 *)regs)[(r_)] 309 #define MGA_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/haiku/headers/private/graphics/neomagic/ |
H A D | nm_macros.h | 302 #define NM_REG8(r_) ((vuint8 *)regs)[(r_)] 303 #define NM_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 304 #define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/haiku/headers/private/graphics/radeon/ |
H A D | mmio.h | 14 #define INREG8( regs, addr ) (*(regs + (addr))) 16 #define OUTREG8( regs, addr, val ) do { *(regs + (addr)) = (val); } while( 0 ) 18 #define INREG( regs, addr ) (*((vuint32 *)(regs + (addr)))) 20 #define OUTREG( regs, addr, val ) do { *(vuint32 *)(regs + (addr)) = (val); } while( 0 ) 22 #define OUTREGP( regs, addr, val, mask ) \ 24 uint32 tmp = INREG( (regs), (add [all...] |
H A D | pll_access.h | 19 void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic ); 24 void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic ); 36 uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr ); 39 void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val ); 42 void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask );
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/haiku/headers/private/graphics/skeleton/ |
H A D | macros.h | 741 #define ENG_REG8(r_) ((vuint8 *)regs)[(r_)] 742 #define ENG_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 743 #define ENG_RG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/haiku/headers/private/graphics/via/ |
H A D | macros.h | 804 #define ENG_REG8(r_) ((vuint8 *)regs)[(r_)] 805 #define ENG_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 806 #define ENG_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/haiku/src/add-ons/accelerants/3dfx/ |
H A D | accelerant.cpp | 43 gInfo.regsArea = clone_area("3DFX regs area", (void**)&(gInfo.regs), 60 gInfo.regs = 0;
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H A D | accelerant.h | 38 uint8* regs; // base address of MMIO register area member in struct:AccelerantInfo 177 #define INREG8(addr) *((vuint8*)(gInfo.regs + addr)) 178 #define INREG16(addr) *((vuint16*)(gInfo.regs + addr)) 179 #define INREG32(addr) *((vuint32*)(gInfo.regs + addr)) 181 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val 182 #define OUTREG16(addr, val) *((vuint16*)(gInfo.regs + addr)) = val 183 #define OUTREG32(addr, val) *((vuint32*)(gInfo.regs + addr)) = val
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/haiku/src/add-ons/accelerants/ati/ |
H A D | accelerant.cpp | 41 gInfo.regsArea = clone_area("ATI regs area", (void**)&(gInfo.regs), 67 gInfo.regs = 0;
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H A D | accelerant.h | 34 uint8* regs; // base address of MMIO register area member in struct:AccelerantInfo 236 #define INREG8(addr) *((vuint8*)(gInfo.regs + addr)) 237 #define INREG16(addr) *((vuint16*)(gInfo.regs + addr)) 238 #define INREG(addr) *((vuint32*)(gInfo.regs + addr)) 240 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val 241 #define OUTREG16(addr, val) *((vuint16*)(gInfo.regs + addr)) = val 242 #define OUTREG(addr, val) *((vuint32*)(gInfo.regs + addr)) = val
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/haiku/src/add-ons/accelerants/intel_810/ |
H A D | accelerant.cpp | 78 gInfo.regsArea = clone_area("i810 regs area", (void**)&(gInfo.regs), 95 gInfo.regs = 0;
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H A D | accelerant.h | 33 uint8* regs; // base address of MMIO register area member in struct:AccelerantInfo
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H A D | i810_regs.h | 55 // General error reporting regs. 111 #define INREG8(addr) (*((vuint8*)(gInfo.regs + (addr)))) 112 #define INREG16(addr) (*((vuint16*)(gInfo.regs + (addr)))) 113 #define INREG32(addr) (*((vuint32*)(gInfo.regs + (addr)))) 115 #define OUTREG8(addr, val) (*((vuint8*)(gInfo.regs + (addr))) = (val)) 116 #define OUTREG16(addr, val) (*((vuint16*)(gInfo.regs + (addr))) = (val)) 117 #define OUTREG32(addr, val) (*((vuint32*)(gInfo.regs + (addr))) = (val))
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/haiku/src/add-ons/accelerants/matrox/engine/ |
H A D | mga_globals.c | 14 vuint32 *regs; variable
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H A D | mga_globals.h | 5 extern vuint32 *regs;
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/haiku/src/add-ons/accelerants/matrox/ |
H A D | global.h | 5 extern vuint32 *regs;
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/haiku/src/add-ons/accelerants/neomagic/ |
H A D | InitAccelerant.c | 52 regs = si->clone_bugfix_regs; 63 regs = si->clone_bugfix_regs; 69 regs_area = clone_area(DRIVER_PREFIX " regs", (void **)®s, B_ANY_ADDRESS, 113 regs = 0;
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/haiku/src/add-ons/accelerants/neomagic/engine/ |
H A D | nm_globals.c | 15 vuint32 *regs, *regs2; variable
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H A D | nm_globals.h | 5 extern vuint32 *regs, *regs2;
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/haiku/src/add-ons/accelerants/nvidia/engine/ |
H A D | nv_acc.c | 1358 &(regs[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID]) >> 2]); 1361 &(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_BLACK_RECTANGLE]) >> 2]); 1364 &(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_PATTERN]) >> 2]); 1367 &(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_BLIT]) >> 2]); 1370 &(regs[(si->engine.fifo.ch_ptr[NV4_GDI_RECTANGLE_TEXT]) >> 2]);
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/haiku/src/add-ons/accelerants/radeon/ |
H A D | CP.c | 59 //space = INREG( ai->regs, RADEON_CP_RB_RPTR ) - cp->ring.tail; 89 //INREG( ai->regs, RADEON_SCRATCH_REG1 ); 339 INREG( ai->regs, RADEON_CP_RB_RPTR ); 347 OUTREG( ai->regs, RADEON_CP_RB_WPTR, cp->ring.tail ); 350 //INREG( ai->regs, RADEON_CP_RB_RPTR );
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H A D | Cursor.c | 25 OUTREG( ai->regs, RADEON_CUR_CLR0, 0xffffff ); 26 OUTREG( ai->regs, RADEON_CUR_CLR1, 0 ); 28 OUTREG( ai->regs, RADEON_CUR2_CLR0, 0xffffff ); 29 OUTREG( ai->regs, RADEON_CUR2_CLR1, 0 ); 197 OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_OFF, RADEON_CUR_LOCK 200 OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_POSN, RADEON_CUR_LOCK 203 OUTREG( ai->regs, RADEON_CUR_OFFSET, 206 OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_OFF, RADEON_CUR2_LOCK 209 OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_POSN, RADEON_CUR2_LOCK 212 OUTREG( ai->regs, RADEON_CUR2_OFFSE [all...] |
H A D | EngineManagment.c | 86 OUTREG( ai->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 87 OUTREG( ai->regs, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | 211 /*if( (int32)(INREG( ai->regs, RADEON_SCRATCH_REG0 ) - st->counter) >= 0 ) 239 st->counter, /*INREG( ai->regs, RADEON_SCRATCH_REG0 )*/
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