Searched refs:registers (Results 1 - 25 of 278) sorted by last modified time

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/linux-master/drivers/media/dvb-frontends/
H A Drtl2832.c13 static const struct rtl2832_reg_entry registers[] = { variable in typeref:struct:rtl2832_reg_entry
151 reg_start_addr = registers[reg].start_address;
152 msb = registers[reg].msb;
153 lsb = registers[reg].lsb;
181 reg_start_addr = registers[reg].start_address;
182 msb = registers[reg].msb;
183 lsb = registers[reg].lsb;
252 /* initialization values for the demodulator registers */
/linux-master/drivers/gpu/drm/msm/
H A DMakefile166 cmd_headergen = mkdir -p $(obj)/generated && $(PYTHON3) $(src)/registers/gen_header.py \
167 $(headergen-opts) --rnn $(src)/registers --xml $< c-defines > $@
169 $(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \
170 $(src)/registers/adreno/adreno_common.xml \
171 $(src)/registers/adreno/adreno_pm4.xml \
172 $(src)/registers/freedreno_copyright.xml \
173 $(src)/registers/gen_header.py \
174 $(src)/registers/rules-fd.xsd \
178 $(obj)/generated/%.xml.h: $(src)/registers/display/%.xml \
179 $(src)/registers/freedreno_copyrigh
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H A Dmsm_gpu.h543 u32 *registers; member in struct:msm_gpu_state
576 * Why not a readq here? Two reasons: 1) many of the LO registers are
578 * of a history of putting registers where they fit, especially in
585 * For some lo/hi registers (like perfcounters), the hi value is latched
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c917 gvt_vgpu_err("Unsupported registers %x\n", offset);
1188 /* write to the data registers */
1292 /* clear the data registers */
1363 if (display->sbi.registers[i].offset == sbi_offset)
1369 return display->sbi.registers[i].value;
1380 if (display->sbi.registers[i].offset == offset)
1392 display->sbi.registers[i].offset = offset;
1393 display->sbi.registers[i].value = value;
1733 * anytime, since we don't touch real physical registers here.
1755 * update the VM CSB status correctly. Here listed registers ca
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/linux-master/sound/soc/samsung/
H A Dmidas_wm1811.c10 #include <linux/mfd/wm8994/registers.h>
/linux-master/sound/soc/codecs/
H A Dwm8994.c31 #include <linux/mfd/wm8994/registers.h>
2261 * registers will actually be written but we avoid GCC flow
H A Dwcd934x.c8 #include <linux/mfd/wcd934x/registers.h>
/linux-master/drivers/platform/x86/x86-android-tablets/
H A Dlenovo.c16 #include <linux/mfd/arizona/registers.h>
/linux-master/drivers/platform/x86/intel/
H A Dsdsi.c532 static BIN_ATTR_ADMIN_RO(registers, SDSI_SIZE_REGS);
684 /* Map the SDSi mailbox registers */
/linux-master/drivers/net/wireless/ath/ath10k/
H A Dsdio.c784 * flag that we should re-check IRQ status registers again
959 * registers and the lookahead registers.
969 /* Update only those registers that are enabled */
1060 /* An optimization to bypass reading the IRQ status registers
1064 * registers which can re-wake the target.
2286 crash_data->registers[i] = __cpu_to_le32(reg_dump_values[i]);
/linux-master/drivers/media/platform/nxp/
H A Dimx-mipi-csis.c197 /* ISP shadow registers */
879 } registers[] = { local
903 for (i = 0; i < ARRAY_SIZE(registers); i++) {
904 cfg = mipi_csis_read(csis, registers[i].offset);
905 dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg);
/linux-master/drivers/gpu/drm/vc4/
H A Dvc4_hdmi.c820 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
2694 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
3382 const struct vc4_hdmi_register *field = &variant->registers[i];
3804 .registers = vc4_hdmi_fields,
3824 .registers = vc5_hdmi_hdmi0_fields,
3853 .registers = vc5_hdmi_hdmi1_fields,
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon.h442 * Tiling registers
661 * GPU scratch registers structures, functions & helpers
2428 /* srbm instance registers */
2562 * Indirect registers accessors.
2815 const u32 *registers,
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h61 .registers = _reg, \
68 const u32 *registers; member in struct:a6xx_cluster
135 .registers = _reg, .count = ARRAY_SIZE(_reg) }
141 const u32 *registers; member in struct:a6xx_dbgahb_cluster
176 const u32 *registers; member in struct:a6xx_registers
183 { .val0 = _base, .val1 = _type, .registers = _array, \
300 { .registers = _array, .count = ARRAY_SIZE(_array), \
H A Da6xx_gpu_state.c36 struct a6xx_gpu_state_obj *registers; member in struct:a6xx_gpu_state
462 * temporary ioremap for the registers
566 int count = RANGE(dbgahb->registers, j);
568 dbgahb->registers[j] - (dbgahb->base >> 2);
704 /* Skip registers that are not present on older generation */
706 cluster->registers == a660_fe_cluster)
710 cluster->registers == a6xx_ps_cluster)
724 int count = RANGE(cluster->registers, j);
726 in += CRASHDUMP_READ(in, cluster->registers[j],
987 /* Read registers fro
1672 a6xx_show_registers(const u32 *registers, u32 *data, size_t count, struct drm_printer *p) argument
1695 a7xx_show_registers_indented(const u32 *registers, u32 *data, struct drm_printer *p, unsigned indent) argument
1719 a7xx_show_registers(const u32 *registers, u32 *data, struct drm_printer *p) argument
1809 a6xx_show_cluster_data(const u32 *registers, int size, u32 *data, struct drm_printer *p) argument
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H A Da6xx_gpu.c119 /* Turn off protected mode to write to special registers */
202 * GPU registers so we need to add 0x1a800 to the register value on A630
1067 /* Don't re-program the registers if they are already correct */
1071 /* Disable SP clock before programming HWCG registers */
1337 * Enable access protection to privileged registers, fault on an access
1347 /* Intentionally skip writing to some registers */
1913 /* Protect registers from the CP */
3044 adreno_gpu->registers = NULL;
H A Da2xx_gpu.c221 /* NOTE: PM4/micro-engine firmware registers look to be the same
224 * parameterize the pfp ucode addr/data registers..
277 /* dump registers before resetting gpu, if enabled: */
548 adreno_gpu->registers = a200_registers;
550 adreno_gpu->registers = a225_registers;
552 adreno_gpu->registers = a220_registers;
/linux-master/drivers/gpu/drm/i915/selftests/
H A Dintel_uncore.c149 } registers[] = { local
191 for (r = registers; r->name; r++)
/linux-master/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c258 struct guc_mmio_reg *registers; member in struct:temp_regset
289 regset->registers = r + (regset->registers - regset->storage);
305 u32 count = regset->storage_used - (regset->registers - regset->storage);
318 if (bsearch(&entry, regset->registers, count,
326 while (slot-- > regset->registers) {
357 * steer all registers that need steering. However, we do not keep track
386 * Each engine's registers point to a new start relative to
389 regset->registers = regset->storage + regset->storage_used;
400 * some of the WA registers ar
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15.h110 const struct soc15_reg_golden *registers,
H A Damdgpu_device.c1353 * amdgpu_device_program_register_sequence - program an array of registers.
1356 * @registers: pointer to the register array
1359 * Programs an array or registers with and or masks.
1360 * This is a helper for setting golden registers.
1363 const u32 *registers,
1373 reg = registers[i + 0];
1374 and_mask = registers[i + 1];
1375 or_mask = registers[i + 2];
4455 /* Unmap all mapped bars - Doorbell, registers and VRAM */
6234 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
1362 amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 *registers, const u32 array_size) argument
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H A Damdgpu.h1412 const u32 *registers,
/linux-master/arch/powerpc/platforms/52xx/
H A Dlite5200_sleep.S37 registers: label
63 * possibly because BDI sets SDRAM registers before wakeup code does
65 lis r4, registers@h
66 ori r4, r4, registers@l
70 /* save registers to r4 [destroys r10] */
262 /* save registers */
329 /* restore registers */
347 lis r4, registers@h
348 ori r4, r4, registers@l
/linux-master/arch/arm/mm/
H A Dproc-v7.S265 @ rules, and so it may corrupt registers that we need to preserve.
606 @ Cortex-A9 - needs more registers preserved across suspend/resume
H A Dproc-v7m.S129 @ some registers to the stack.

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