/linux-master/drivers/net/ethernet/ibm/ehea/ |
H A D | ehea_phyp.c | 574 const u8 reg_type, const u64 mc_mac_addr, 581 r6_reg_type = EHEA_BMASK_SET(H_REGBCMC_REGTYPE, reg_type); 573 ehea_h_reg_dereg_bcmc(const u64 adapter_handle, const u16 port_num, const u8 reg_type, const u64 mc_mac_addr, const u16 vlan_id, const u32 hcall_id) argument
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H A D | ehea_phyp.h | 424 const u8 reg_type, const u64 mc_mac_addr,
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/linux-master/drivers/scsi/mvsas/ |
H A D | mv_94xx.c | 1042 u8 reg_type, u8 reg_index, 1047 switch (reg_type) { 1041 mvs_94xx_gpio_write(struct mvs_prv_info *mvs_prv, u8 reg_type, u8 reg_index, u8 reg_count, u8 *write_data) argument
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/linux-master/arch/arm/probes/kprobes/ |
H A D | test-core.c | 780 enum decode_reg_type reg_type = (regs >> i) & 0xf; local 784 if (!reg_type) 795 switch (reg_type) {
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/linux-master/arch/powerpc/include/asm/ |
H A D | mpic.h | 300 enum mpic_reg_type reg_type; member in struct:mpic
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/linux-master/arch/powerpc/platforms/powernv/ |
H A D | opal-fadump.h | 81 __be32 reg_type; member in struct:hdat_fadump_reg_entry 87 u32 reg_type, u32 reg_num, 90 if (reg_type == HDAT_FADUMP_REG_TYPE_GPR) { 140 be32_to_cpu(reg_entry->reg_type), 86 opal_fadump_set_regval_regnum(struct pt_regs *regs, u32 reg_type, u32 reg_num, u64 reg_val) argument
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/linux-master/arch/powerpc/platforms/ps3/ |
H A D | device-init.c | 183 enum ps3_interrupt_type interrupt_type, enum ps3_reg_type reg_type) 222 result = ps3_repository_find_reg(repo, reg_type, 181 ps3_setup_uhc_device( const struct ps3_repository_device *repo, enum ps3_match_id match_id, enum ps3_interrupt_type interrupt_type, enum ps3_reg_type reg_type) argument
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H A D | platform.h | 115 enum ps3_reg_type *reg_type); 121 enum ps3_reg_type *reg_type, u64 *bus_addr, u64 *len); 144 enum ps3_reg_type reg_type, u64 *bus_addr, u64 *len);
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H A D | repository.c | 251 enum ps3_reg_type *reg_type) 262 *reg_type = v1; 279 enum ps3_reg_type *reg_type, u64 *bus_addr, u64 *len) 282 reg_index, reg_type); 521 enum ps3_reg_type reg_type, u64 *bus_addr, u64 *len) 526 pr_devel("%s:%d: find reg_type %u\n", __func__, __LINE__, reg_type); 544 if (t == reg_type) { 554 pr_devel("%s:%d: found reg_type %u at res_index %u\n", 555 __func__, __LINE__, reg_type, res_inde 249 ps3_repository_read_dev_reg_type(unsigned int bus_index, unsigned int dev_index, unsigned int reg_index, enum ps3_reg_type *reg_type) argument 277 ps3_repository_read_dev_reg(unsigned int bus_index, unsigned int dev_index, unsigned int reg_index, enum ps3_reg_type *reg_type, u64 *bus_addr, u64 *len) argument 520 ps3_repository_find_reg(const struct ps3_repository_device *repo, enum ps3_reg_type reg_type, u64 *bus_addr, u64 *len) argument 1210 enum ps3_reg_type reg_type; local [all...] |
/linux-master/arch/powerpc/sysdev/ |
H A D | mpic.c | 214 enum mpic_reg_type type = mpic->reg_type; 228 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 242 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); 250 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); 257 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 264 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 273 val = _mpic_read(mpic->reg_type, &mpic->isus[isu], 289 _mpic_write(mpic->reg_type, &mpic->isus[isu], 299 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 300 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type, [all...] |
/linux-master/arch/x86/lib/ |
H A D | insn-eval.c | 21 enum reg_type { enum 447 static int get_regno(struct insn *insn, enum reg_type type) 523 enum reg_type type)
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/linux-master/drivers/comedi/drivers/ |
H A D | ni_pcimio.c | 461 .reg_type = ni_reg_611x, 476 .reg_type = ni_reg_611x, 527 .reg_type = ni_reg_6711, 537 .reg_type = ni_reg_6711, 547 .reg_type = ni_reg_6713, 557 .reg_type = ni_reg_6713, 567 .reg_type = ni_reg_6711, 577 .reg_type = ni_reg_6711, 588 .reg_type = ni_reg_6713, 598 .reg_type [all...] |
H A D | ni_stc.h | 962 int reg_type; member in struct:ni_board_struct 1046 /* ni_pcimio board type flags (based on the boardinfo reg_type) */
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/linux-master/drivers/crypto/intel/qat/qat_common/ |
H A D | adf_common_drv.h | 165 enum icp_qat_uof_regtype reg_type, 169 enum icp_qat_uof_regtype reg_type, 173 enum icp_qat_uof_regtype reg_type,
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H A D | icp_qat_uclo.h | 297 char reg_type; member in struct:icp_qat_uof_init_regsym 329 unsigned char reg_type; member in struct:icp_qat_uof_sbreak
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H A D | qat_hal.c | 1116 enum icp_qat_uof_regtype reg_type, 1125 reg_addr = qat_hal_get_reg_addr(reg_type, reg_num); 1130 switch (reg_type) { 1177 enum icp_qat_uof_regtype reg_type, 1190 dest_addr = qat_hal_get_reg_addr(reg_type, reg_num); 1202 switch (reg_type) { 1331 enum icp_qat_uof_regtype reg_type, 1354 switch (reg_type) { 1372 enum icp_qat_uof_regtype reg_type, 1402 xfr_addr = qat_hal_get_reg_addr(reg_type, reg_nu 1114 qat_hal_rd_rel_reg(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int *data) argument 1175 qat_hal_wr_rel_reg(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int data) argument 1329 qat_hal_put_rel_rd_xfer(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int val) argument 1370 qat_hal_put_rel_wr_xfer(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int data) argument 1468 qat_hal_init_gpr(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned long ctx_mask, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int regdata) argument 1502 qat_hal_init_wr_xfer(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned long ctx_mask, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int regdata) argument 1537 qat_hal_init_rd_xfer(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned long ctx_mask, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int regdata) argument [all...] |
H A D | qat_uclo.c | 766 enum icp_qat_uof_regtype reg_type, 769 switch (reg_type) { 776 return qat_hal_init_gpr(handle, ae, ctx_mask, reg_type, 788 return qat_hal_init_rd_xfer(handle, ae, ctx_mask, reg_type, 796 return qat_hal_init_wr_xfer(handle, ae, ctx_mask, reg_type, 801 pr_err("QAT: UOF uses not supported reg type 0x%x\n", reg_type); 830 init_regsym->reg_type, 845 init_regsym->reg_type, 764 qat_uclo_init_reg(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx_mask, enum icp_qat_uof_regtype reg_type, unsigned short reg_addr, unsigned int value) argument
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/linux-master/drivers/crypto/marvell/octeontx/ |
H A D | otx_cptvf_algs.c | 1213 static u32 cpt_aead_enc_dec(struct aead_request *req, u8 reg_type, u8 enc) argument 1227 req_info->req_type = reg_type; 1231 switch (reg_type) {
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/linux-master/drivers/crypto/marvell/octeontx2/ |
H A D | otx2_cptvf_algs.c | 1311 static int cpt_aead_enc_dec(struct aead_request *req, u8 reg_type, u8 enc) argument 1326 req_info->req_type = reg_type; 1333 switch (reg_type) {
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/linux-master/drivers/cxl/core/ |
H A D | port.c | 756 .reg_type = CXL_REGLOC_RBI_EMPTY, 763 map->reg_type = CXL_REGLOC_RBI_COMPONENT;
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H A D | regs.c | 274 u8 reg_type = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo); local 282 &pdev->resource[bar], &offset, reg_type); 286 map->reg_type = reg_type; 337 if (map->reg_type == type) { 431 switch (map->reg_type) {
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/linux-master/drivers/cxl/ |
H A D | cxl.h | 264 * @reg_type: see enum cxl_regloc_type 274 u8 reg_type; member in struct:cxl_register_map
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H A D | pci.c | 497 map->reg_type = CXL_REGLOC_RBI_COMPONENT;
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/linux-master/drivers/gpio/ |
H A D | gpio-crystalcove.c | 82 static inline int to_reg(int gpio, enum ctrl_register reg_type) argument 99 if (reg_type == CTRL_IN) {
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H A D | gpio-ftgpio010.c | 91 u32 reg_both, reg_level, reg_type; local 93 reg_type = readl(g->base + GPIO_INT_TYPE); 100 reg_type &= ~mask; 105 reg_type &= ~mask; 111 reg_type &= ~mask; 117 reg_type |= mask; 122 reg_type |= mask; 130 writel(reg_type, g->base + GPIO_INT_TYPE);
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