1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Register descriptions for NI DAQ-STC chip 4 * 5 * COMEDI - Linux Control and Measurement Device Interface 6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org> 7 */ 8 9/* 10 * References: 11 * DAQ-STC Technical Reference Manual 12 */ 13 14#ifndef _COMEDI_NI_STC_H 15#define _COMEDI_NI_STC_H 16 17#include "ni_tio.h" 18#include "ni_routes.h" 19 20/* 21 * Registers in the National Instruments DAQ-STC chip 22 */ 23 24#define NISTC_INTA_ACK_REG 2 25#define NISTC_INTA_ACK_G0_GATE BIT(15) 26#define NISTC_INTA_ACK_G0_TC BIT(14) 27#define NISTC_INTA_ACK_AI_ERR BIT(13) 28#define NISTC_INTA_ACK_AI_STOP BIT(12) 29#define NISTC_INTA_ACK_AI_START BIT(11) 30#define NISTC_INTA_ACK_AI_START2 BIT(10) 31#define NISTC_INTA_ACK_AI_START1 BIT(9) 32#define NISTC_INTA_ACK_AI_SC_TC BIT(8) 33#define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7) 34#define NISTC_INTA_ACK_G0_TC_ERR BIT(6) 35#define NISTC_INTA_ACK_G0_GATE_ERR BIT(5) 36#define NISTC_INTA_ACK_AI_ALL (NISTC_INTA_ACK_AI_ERR | \ 37 NISTC_INTA_ACK_AI_STOP | \ 38 NISTC_INTA_ACK_AI_START | \ 39 NISTC_INTA_ACK_AI_START2 | \ 40 NISTC_INTA_ACK_AI_START1 | \ 41 NISTC_INTA_ACK_AI_SC_TC | \ 42 NISTC_INTA_ACK_AI_SC_TC_ERR) 43 44#define NISTC_INTB_ACK_REG 3 45#define NISTC_INTB_ACK_G1_GATE BIT(15) 46#define NISTC_INTB_ACK_G1_TC BIT(14) 47#define NISTC_INTB_ACK_AO_ERR BIT(13) 48#define NISTC_INTB_ACK_AO_STOP BIT(12) 49#define NISTC_INTB_ACK_AO_START BIT(11) 50#define NISTC_INTB_ACK_AO_UPDATE BIT(10) 51#define NISTC_INTB_ACK_AO_START1 BIT(9) 52#define NISTC_INTB_ACK_AO_BC_TC BIT(8) 53#define NISTC_INTB_ACK_AO_UC_TC BIT(7) 54#define NISTC_INTB_ACK_AO_UI2_TC BIT(6) 55#define NISTC_INTB_ACK_AO_UI2_TC_ERR BIT(5) 56#define NISTC_INTB_ACK_AO_BC_TC_ERR BIT(4) 57#define NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR BIT(3) 58#define NISTC_INTB_ACK_G1_TC_ERR BIT(2) 59#define NISTC_INTB_ACK_G1_GATE_ERR BIT(1) 60#define NISTC_INTB_ACK_AO_ALL (NISTC_INTB_ACK_AO_ERR | \ 61 NISTC_INTB_ACK_AO_STOP | \ 62 NISTC_INTB_ACK_AO_START | \ 63 NISTC_INTB_ACK_AO_UPDATE | \ 64 NISTC_INTB_ACK_AO_START1 | \ 65 NISTC_INTB_ACK_AO_BC_TC | \ 66 NISTC_INTB_ACK_AO_UC_TC | \ 67 NISTC_INTB_ACK_AO_BC_TC_ERR | \ 68 NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR) 69 70#define NISTC_AI_CMD2_REG 4 71#define NISTC_AI_CMD2_END_ON_SC_TC BIT(15) 72#define NISTC_AI_CMD2_END_ON_EOS BIT(14) 73#define NISTC_AI_CMD2_START1_DISABLE BIT(11) 74#define NISTC_AI_CMD2_SC_SAVE_TRACE BIT(10) 75#define NISTC_AI_CMD2_SI_SW_ON_SC_TC BIT(9) 76#define NISTC_AI_CMD2_SI_SW_ON_STOP BIT(8) 77#define NISTC_AI_CMD2_SI_SW_ON_TC BIT(7) 78#define NISTC_AI_CMD2_SC_SW_ON_TC BIT(4) 79#define NISTC_AI_CMD2_STOP_PULSE BIT(3) 80#define NISTC_AI_CMD2_START_PULSE BIT(2) 81#define NISTC_AI_CMD2_START2_PULSE BIT(1) 82#define NISTC_AI_CMD2_START1_PULSE BIT(0) 83 84#define NISTC_AO_CMD2_REG 5 85#define NISTC_AO_CMD2_END_ON_BC_TC(x) (((x) & 0x3) << 14) 86#define NISTC_AO_CMD2_START_STOP_GATE_ENA BIT(13) 87#define NISTC_AO_CMD2_UC_SAVE_TRACE BIT(12) 88#define NISTC_AO_CMD2_BC_GATE_ENA BIT(11) 89#define NISTC_AO_CMD2_BC_SAVE_TRACE BIT(10) 90#define NISTC_AO_CMD2_UI_SW_ON_BC_TC BIT(9) 91#define NISTC_AO_CMD2_UI_SW_ON_STOP BIT(8) 92#define NISTC_AO_CMD2_UI_SW_ON_TC BIT(7) 93#define NISTC_AO_CMD2_UC_SW_ON_BC_TC BIT(6) 94#define NISTC_AO_CMD2_UC_SW_ON_TC BIT(5) 95#define NISTC_AO_CMD2_BC_SW_ON_TC BIT(4) 96#define NISTC_AO_CMD2_MUTE_B BIT(3) 97#define NISTC_AO_CMD2_MUTE_A BIT(2) 98#define NISTC_AO_CMD2_UPDATE2_PULSE BIT(1) 99#define NISTC_AO_CMD2_START1_PULSE BIT(0) 100 101#define NISTC_G0_CMD_REG 6 102#define NISTC_G1_CMD_REG 7 103 104#define NISTC_AI_CMD1_REG 8 105#define NISTC_AI_CMD1_ATRIG_RESET BIT(14) 106#define NISTC_AI_CMD1_DISARM BIT(13) 107#define NISTC_AI_CMD1_SI2_ARM BIT(12) 108#define NISTC_AI_CMD1_SI2_LOAD BIT(11) 109#define NISTC_AI_CMD1_SI_ARM BIT(10) 110#define NISTC_AI_CMD1_SI_LOAD BIT(9) 111#define NISTC_AI_CMD1_DIV_ARM BIT(8) 112#define NISTC_AI_CMD1_DIV_LOAD BIT(7) 113#define NISTC_AI_CMD1_SC_ARM BIT(6) 114#define NISTC_AI_CMD1_SC_LOAD BIT(5) 115#define NISTC_AI_CMD1_SCAN_IN_PROG_PULSE BIT(4) 116#define NISTC_AI_CMD1_EXTMUX_CLK_PULSE BIT(3) 117#define NISTC_AI_CMD1_LOCALMUX_CLK_PULSE BIT(2) 118#define NISTC_AI_CMD1_SC_TC_PULSE BIT(1) 119#define NISTC_AI_CMD1_CONVERT_PULSE BIT(0) 120 121#define NISTC_AO_CMD1_REG 9 122#define NISTC_AO_CMD1_ATRIG_RESET BIT(15) 123#define NISTC_AO_CMD1_START_PULSE BIT(14) 124#define NISTC_AO_CMD1_DISARM BIT(13) 125#define NISTC_AO_CMD1_UI2_ARM_DISARM BIT(12) 126#define NISTC_AO_CMD1_UI2_LOAD BIT(11) 127#define NISTC_AO_CMD1_UI_ARM BIT(10) 128#define NISTC_AO_CMD1_UI_LOAD BIT(9) 129#define NISTC_AO_CMD1_UC_ARM BIT(8) 130#define NISTC_AO_CMD1_UC_LOAD BIT(7) 131#define NISTC_AO_CMD1_BC_ARM BIT(6) 132#define NISTC_AO_CMD1_BC_LOAD BIT(5) 133#define NISTC_AO_CMD1_DAC1_UPDATE_MODE BIT(4) 134#define NISTC_AO_CMD1_LDAC1_SRC_SEL BIT(3) 135#define NISTC_AO_CMD1_DAC0_UPDATE_MODE BIT(2) 136#define NISTC_AO_CMD1_LDAC0_SRC_SEL BIT(1) 137#define NISTC_AO_CMD1_UPDATE_PULSE BIT(0) 138 139#define NISTC_DIO_OUT_REG 10 140#define NISTC_DIO_OUT_SERIAL(x) (((x) & 0xff) << 8) 141#define NISTC_DIO_OUT_SERIAL_MASK NISTC_DIO_OUT_SERIAL(0xff) 142#define NISTC_DIO_OUT_PARALLEL(x) ((x) & 0xff) 143#define NISTC_DIO_OUT_PARALLEL_MASK NISTC_DIO_OUT_PARALLEL(0xff) 144#define NISTC_DIO_SDIN BIT(4) 145#define NISTC_DIO_SDOUT BIT(0) 146 147#define NISTC_DIO_CTRL_REG 11 148#define NISTC_DIO_SDCLK BIT(11) 149#define NISTC_DIO_CTRL_HW_SER_TIMEBASE BIT(10) 150#define NISTC_DIO_CTRL_HW_SER_ENA BIT(9) 151#define NISTC_DIO_CTRL_HW_SER_START BIT(8) 152#define NISTC_DIO_CTRL_DIR(x) ((x) & 0xff) 153#define NISTC_DIO_CTRL_DIR_MASK NISTC_DIO_CTRL_DIR(0xff) 154 155#define NISTC_AI_MODE1_REG 12 156#define NISTC_AI_MODE1_CONVERT_SRC(x) (((x) & 0x1f) << 11) 157#define NISTC_AI_MODE1_SI_SRC(x) (((x) & 0x1f) << 6) 158#define NISTC_AI_MODE1_CONVERT_POLARITY BIT(5) 159#define NISTC_AI_MODE1_SI_POLARITY BIT(4) 160#define NISTC_AI_MODE1_START_STOP BIT(3) 161#define NISTC_AI_MODE1_RSVD BIT(2) 162#define NISTC_AI_MODE1_CONTINUOUS BIT(1) 163#define NISTC_AI_MODE1_TRIGGER_ONCE BIT(0) 164 165#define NISTC_AI_MODE2_REG 13 166#define NISTC_AI_MODE2_SC_GATE_ENA BIT(15) 167#define NISTC_AI_MODE2_START_STOP_GATE_ENA BIT(14) 168#define NISTC_AI_MODE2_PRE_TRIGGER BIT(13) 169#define NISTC_AI_MODE2_EXTMUX_PRESENT BIT(12) 170#define NISTC_AI_MODE2_SI2_INIT_LOAD_SRC BIT(9) 171#define NISTC_AI_MODE2_SI2_RELOAD_MODE BIT(8) 172#define NISTC_AI_MODE2_SI_INIT_LOAD_SRC BIT(7) 173#define NISTC_AI_MODE2_SI_RELOAD_MODE(x) (((x) & 0x7) << 4) 174#define NISTC_AI_MODE2_SI_WR_SWITCH BIT(3) 175#define NISTC_AI_MODE2_SC_INIT_LOAD_SRC BIT(2) 176#define NISTC_AI_MODE2_SC_RELOAD_MODE BIT(1) 177#define NISTC_AI_MODE2_SC_WR_SWITCH BIT(0) 178 179#define NISTC_AI_SI_LOADA_REG 14 180#define NISTC_AI_SI_LOADB_REG 16 181#define NISTC_AI_SC_LOADA_REG 18 182#define NISTC_AI_SC_LOADB_REG 20 183#define NISTC_AI_SI2_LOADA_REG 23 184#define NISTC_AI_SI2_LOADB_REG 25 185 186#define NISTC_G0_MODE_REG 26 187#define NISTC_G1_MODE_REG 27 188#define NISTC_G0_LOADA_REG 28 189#define NISTC_G0_LOADB_REG 30 190#define NISTC_G1_LOADA_REG 32 191#define NISTC_G1_LOADB_REG 34 192#define NISTC_G0_INPUT_SEL_REG 36 193#define NISTC_G1_INPUT_SEL_REG 37 194 195#define NISTC_AO_MODE1_REG 38 196#define NISTC_AO_MODE1_UPDATE_SRC(x) (((x) & 0x1f) << 11) 197#define NISTC_AO_MODE1_UPDATE_SRC_MASK NISTC_AO_MODE1_UPDATE_SRC(0x1f) 198#define NISTC_AO_MODE1_UI_SRC(x) (((x) & 0x1f) << 6) 199#define NISTC_AO_MODE1_UI_SRC_MASK NISTC_AO_MODE1_UI_SRC(0x1f) 200#define NISTC_AO_MODE1_MULTI_CHAN BIT(5) 201#define NISTC_AO_MODE1_UPDATE_SRC_POLARITY BIT(4) 202#define NISTC_AO_MODE1_UI_SRC_POLARITY BIT(3) 203#define NISTC_AO_MODE1_UC_SW_EVERY_TC BIT(2) 204#define NISTC_AO_MODE1_CONTINUOUS BIT(1) 205#define NISTC_AO_MODE1_TRIGGER_ONCE BIT(0) 206 207#define NISTC_AO_MODE2_REG 39 208#define NISTC_AO_MODE2_FIFO_MODE(x) (((x) & 0x3) << 14) 209#define NISTC_AO_MODE2_FIFO_MODE_MASK NISTC_AO_MODE2_FIFO_MODE(3) 210#define NISTC_AO_MODE2_FIFO_MODE_E NISTC_AO_MODE2_FIFO_MODE(0) 211#define NISTC_AO_MODE2_FIFO_MODE_HF NISTC_AO_MODE2_FIFO_MODE(1) 212#define NISTC_AO_MODE2_FIFO_MODE_F NISTC_AO_MODE2_FIFO_MODE(2) 213#define NISTC_AO_MODE2_FIFO_MODE_HF_F NISTC_AO_MODE2_FIFO_MODE(3) 214#define NISTC_AO_MODE2_FIFO_REXMIT_ENA BIT(13) 215#define NISTC_AO_MODE2_START1_DISABLE BIT(12) 216#define NISTC_AO_MODE2_UC_INIT_LOAD_SRC BIT(11) 217#define NISTC_AO_MODE2_UC_WR_SWITCH BIT(10) 218#define NISTC_AO_MODE2_UI2_INIT_LOAD_SRC BIT(9) 219#define NISTC_AO_MODE2_UI2_RELOAD_MODE BIT(8) 220#define NISTC_AO_MODE2_UI_INIT_LOAD_SRC BIT(7) 221#define NISTC_AO_MODE2_UI_RELOAD_MODE(x) (((x) & 0x7) << 4) 222#define NISTC_AO_MODE2_UI_WR_SWITCH BIT(3) 223#define NISTC_AO_MODE2_BC_INIT_LOAD_SRC BIT(2) 224#define NISTC_AO_MODE2_BC_RELOAD_MODE BIT(1) 225#define NISTC_AO_MODE2_BC_WR_SWITCH BIT(0) 226 227#define NISTC_AO_UI_LOADA_REG 40 228#define NISTC_AO_UI_LOADB_REG 42 229#define NISTC_AO_BC_LOADA_REG 44 230#define NISTC_AO_BC_LOADB_REG 46 231#define NISTC_AO_UC_LOADA_REG 48 232#define NISTC_AO_UC_LOADB_REG 50 233 234#define NISTC_CLK_FOUT_REG 56 235#define NISTC_CLK_FOUT_ENA BIT(15) 236#define NISTC_CLK_FOUT_TIMEBASE_SEL BIT(14) 237#define NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 BIT(13) 238#define NISTC_CLK_FOUT_SLOW_DIV2 BIT(12) 239#define NISTC_CLK_FOUT_SLOW_TIMEBASE BIT(11) 240#define NISTC_CLK_FOUT_G_SRC_DIV2 BIT(10) 241#define NISTC_CLK_FOUT_TO_BOARD_DIV2 BIT(9) 242#define NISTC_CLK_FOUT_TO_BOARD BIT(8) 243#define NISTC_CLK_FOUT_AI_OUT_DIV2 BIT(7) 244#define NISTC_CLK_FOUT_AI_SRC_DIV2 BIT(6) 245#define NISTC_CLK_FOUT_AO_OUT_DIV2 BIT(5) 246#define NISTC_CLK_FOUT_AO_SRC_DIV2 BIT(4) 247#define NISTC_CLK_FOUT_DIVIDER(x) (((x) & 0xf) << 0) 248#define NISTC_CLK_FOUT_TO_DIVIDER(x) (((x) >> 0) & 0xf) 249#define NISTC_CLK_FOUT_DIVIDER_MASK NISTC_CLK_FOUT_DIVIDER(0xf) 250 251#define NISTC_IO_BIDIR_PIN_REG 57 252 253#define NISTC_RTSI_TRIG_DIR_REG 58 254#define NISTC_RTSI_TRIG_OLD_CLK_CHAN 7 255#define NISTC_RTSI_TRIG_NUM_CHAN(_m) ((_m) ? 8 : 7) 256#define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c))) 257#define NISTC_RTSI_TRIG_DIR_SUB_SEL1 BIT(2) /* only for M-Series */ 258#define NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT 2 /* only for M-Series */ 259#define NISTC_RTSI_TRIG_USE_CLK BIT(1) 260#define NISTC_RTSI_TRIG_DRV_CLK BIT(0) 261 262#define NISTC_INT_CTRL_REG 59 263#define NISTC_INT_CTRL_INTB_ENA BIT(15) 264#define NISTC_INT_CTRL_INTB_SEL(x) (((x) & 0x7) << 12) 265#define NISTC_INT_CTRL_INTA_ENA BIT(11) 266#define NISTC_INT_CTRL_INTA_SEL(x) (((x) & 0x7) << 8) 267#define NISTC_INT_CTRL_PASSTHRU0_POL BIT(3) 268#define NISTC_INT_CTRL_PASSTHRU1_POL BIT(2) 269#define NISTC_INT_CTRL_3PIN_INT BIT(1) 270#define NISTC_INT_CTRL_INT_POL BIT(0) 271 272#define NISTC_AI_OUT_CTRL_REG 60 273#define NISTC_AI_OUT_CTRL_START_SEL BIT(10) 274#define NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(x) (((x) & 0x3) << 8) 275#define NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(x) (((x) & 0x3) << 6) 276#define NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(x) (((x) & 0x3) << 4) 277#define NISTC_AI_OUT_CTRL_SC_TC_SEL(x) (((x) & 0x3) << 2) 278#define NISTC_AI_OUT_CTRL_CONVERT_SEL(x) (((x) & 0x3) << 0) 279#define NISTC_AI_OUT_CTRL_CONVERT_HIGH_Z NISTC_AI_OUT_CTRL_CONVERT_SEL(0) 280#define NISTC_AI_OUT_CTRL_CONVERT_GND NISTC_AI_OUT_CTRL_CONVERT_SEL(1) 281#define NISTC_AI_OUT_CTRL_CONVERT_LOW NISTC_AI_OUT_CTRL_CONVERT_SEL(2) 282#define NISTC_AI_OUT_CTRL_CONVERT_HIGH NISTC_AI_OUT_CTRL_CONVERT_SEL(3) 283 284#define NISTC_ATRIG_ETC_REG 61 285#define NISTC_ATRIG_ETC_GPFO_1_ENA BIT(15) 286#define NISTC_ATRIG_ETC_GPFO_0_ENA BIT(14) 287#define NISTC_ATRIG_ETC_GPFO_0_SEL(x) (((x) & 0x7) << 11) 288#define NISTC_ATRIG_ETC_GPFO_0_SEL_TO_SRC(x) (((x) >> 11) & 0x7) 289#define NISTC_ATRIG_ETC_GPFO_1_SEL BIT(7) 290#define NISTC_ATRIG_ETC_GPFO_1_SEL_TO_SRC(x) (((x) >> 7) & 0x1) 291#define NISTC_ATRIG_ETC_DRV BIT(4) 292#define NISTC_ATRIG_ETC_ENA BIT(3) 293#define NISTC_ATRIG_ETC_MODE(x) (((x) & 0x7) << 0) 294#define NISTC_GPFO_0_G_OUT 0 /* input to GPFO_0_SEL for Ctr0Out */ 295#define NISTC_GPFO_1_G_OUT 0 /* input to GPFO_1_SEL for Ctr1Out */ 296 297#define NISTC_AI_START_STOP_REG 62 298#define NISTC_AI_START_POLARITY BIT(15) 299#define NISTC_AI_STOP_POLARITY BIT(14) 300#define NISTC_AI_STOP_SYNC BIT(13) 301#define NISTC_AI_STOP_EDGE BIT(12) 302#define NISTC_AI_STOP_SEL(x) (((x) & 0x1f) << 7) 303#define NISTC_AI_START_SYNC BIT(6) 304#define NISTC_AI_START_EDGE BIT(5) 305#define NISTC_AI_START_SEL(x) (((x) & 0x1f) << 0) 306 307#define NISTC_AI_TRIG_SEL_REG 63 308#define NISTC_AI_TRIG_START1_POLARITY BIT(15) 309#define NISTC_AI_TRIG_START2_POLARITY BIT(14) 310#define NISTC_AI_TRIG_START2_SYNC BIT(13) 311#define NISTC_AI_TRIG_START2_EDGE BIT(12) 312#define NISTC_AI_TRIG_START2_SEL(x) (((x) & 0x1f) << 7) 313#define NISTC_AI_TRIG_START1_SYNC BIT(6) 314#define NISTC_AI_TRIG_START1_EDGE BIT(5) 315#define NISTC_AI_TRIG_START1_SEL(x) (((x) & 0x1f) << 0) 316 317#define NISTC_AI_DIV_LOADA_REG 64 318 319#define NISTC_AO_START_SEL_REG 66 320#define NISTC_AO_START_UI2_SW_GATE BIT(15) 321#define NISTC_AO_START_UI2_EXT_GATE_POL BIT(14) 322#define NISTC_AO_START_POLARITY BIT(13) 323#define NISTC_AO_START_AOFREQ_ENA BIT(12) 324#define NISTC_AO_START_UI2_EXT_GATE_SEL(x) (((x) & 0x1f) << 7) 325#define NISTC_AO_START_SYNC BIT(6) 326#define NISTC_AO_START_EDGE BIT(5) 327#define NISTC_AO_START_SEL(x) (((x) & 0x1f) << 0) 328 329#define NISTC_AO_TRIG_SEL_REG 67 330#define NISTC_AO_TRIG_UI2_EXT_GATE_ENA BIT(15) 331#define NISTC_AO_TRIG_DELAYED_START1 BIT(14) 332#define NISTC_AO_TRIG_START1_POLARITY BIT(13) 333#define NISTC_AO_TRIG_UI2_SRC_POLARITY BIT(12) 334#define NISTC_AO_TRIG_UI2_SRC_SEL(x) (((x) & 0x1f) << 7) 335#define NISTC_AO_TRIG_START1_SYNC BIT(6) 336#define NISTC_AO_TRIG_START1_EDGE BIT(5) 337#define NISTC_AO_TRIG_START1_SEL(x) (((x) & 0x1f) << 0) 338#define NISTC_AO_TRIG_START1_SEL_MASK NISTC_AO_TRIG_START1_SEL(0x1f) 339 340#define NISTC_G0_AUTOINC_REG 68 341#define NISTC_G1_AUTOINC_REG 69 342 343#define NISTC_AO_MODE3_REG 70 344#define NISTC_AO_MODE3_UI2_SW_NEXT_TC BIT(13) 345#define NISTC_AO_MODE3_UC_SW_EVERY_BC_TC BIT(12) 346#define NISTC_AO_MODE3_TRIG_LEN BIT(11) 347#define NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR BIT(5) 348#define NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR BIT(4) 349#define NISTC_AO_MODE3_STOP_ON_BC_TC_ERR BIT(3) 350#define NISTC_AO_MODE3_NOT_AN_UPDATE BIT(2) 351#define NISTC_AO_MODE3_SW_GATE BIT(1) 352#define NISTC_AO_MODE3_LAST_GATE_DISABLE BIT(0) /* M-Series only */ 353 354#define NISTC_RESET_REG 72 355#define NISTC_RESET_SOFTWARE BIT(11) 356#define NISTC_RESET_AO_CFG_END BIT(9) 357#define NISTC_RESET_AI_CFG_END BIT(8) 358#define NISTC_RESET_AO_CFG_START BIT(5) 359#define NISTC_RESET_AI_CFG_START BIT(4) 360#define NISTC_RESET_G1 BIT(3) 361#define NISTC_RESET_G0 BIT(2) 362#define NISTC_RESET_AO BIT(1) 363#define NISTC_RESET_AI BIT(0) 364 365#define NISTC_INTA_ENA_REG 73 366#define NISTC_INTA2_ENA_REG 74 367#define NISTC_INTA_ENA_PASSTHRU0 BIT(9) 368#define NISTC_INTA_ENA_G0_GATE BIT(8) 369#define NISTC_INTA_ENA_AI_FIFO BIT(7) 370#define NISTC_INTA_ENA_G0_TC BIT(6) 371#define NISTC_INTA_ENA_AI_ERR BIT(5) 372#define NISTC_INTA_ENA_AI_STOP BIT(4) 373#define NISTC_INTA_ENA_AI_START BIT(3) 374#define NISTC_INTA_ENA_AI_START2 BIT(2) 375#define NISTC_INTA_ENA_AI_START1 BIT(1) 376#define NISTC_INTA_ENA_AI_SC_TC BIT(0) 377#define NISTC_INTA_ENA_AI_MASK (NISTC_INTA_ENA_AI_FIFO | \ 378 NISTC_INTA_ENA_AI_ERR | \ 379 NISTC_INTA_ENA_AI_STOP | \ 380 NISTC_INTA_ENA_AI_START | \ 381 NISTC_INTA_ENA_AI_START2 | \ 382 NISTC_INTA_ENA_AI_START1 | \ 383 NISTC_INTA_ENA_AI_SC_TC) 384 385#define NISTC_INTB_ENA_REG 75 386#define NISTC_INTB2_ENA_REG 76 387#define NISTC_INTB_ENA_PASSTHRU1 BIT(11) 388#define NISTC_INTB_ENA_G1_GATE BIT(10) 389#define NISTC_INTB_ENA_G1_TC BIT(9) 390#define NISTC_INTB_ENA_AO_FIFO BIT(8) 391#define NISTC_INTB_ENA_AO_UI2_TC BIT(7) 392#define NISTC_INTB_ENA_AO_UC_TC BIT(6) 393#define NISTC_INTB_ENA_AO_ERR BIT(5) 394#define NISTC_INTB_ENA_AO_STOP BIT(4) 395#define NISTC_INTB_ENA_AO_START BIT(3) 396#define NISTC_INTB_ENA_AO_UPDATE BIT(2) 397#define NISTC_INTB_ENA_AO_START1 BIT(1) 398#define NISTC_INTB_ENA_AO_BC_TC BIT(0) 399 400#define NISTC_AI_PERSONAL_REG 77 401#define NISTC_AI_PERSONAL_SHIFTIN_PW BIT(15) 402#define NISTC_AI_PERSONAL_EOC_POLARITY BIT(14) 403#define NISTC_AI_PERSONAL_SOC_POLARITY BIT(13) 404#define NISTC_AI_PERSONAL_SHIFTIN_POL BIT(12) 405#define NISTC_AI_PERSONAL_CONVERT_TIMEBASE BIT(11) 406#define NISTC_AI_PERSONAL_CONVERT_PW BIT(10) 407#define NISTC_AI_PERSONAL_CONVERT_ORIG_PULSE BIT(9) 408#define NISTC_AI_PERSONAL_FIFO_FLAGS_POL BIT(8) 409#define NISTC_AI_PERSONAL_OVERRUN_MODE BIT(7) 410#define NISTC_AI_PERSONAL_EXTMUX_CLK_PW BIT(6) 411#define NISTC_AI_PERSONAL_LOCALMUX_CLK_PW BIT(5) 412#define NISTC_AI_PERSONAL_AIFREQ_POL BIT(4) 413 414#define NISTC_AO_PERSONAL_REG 78 415#define NISTC_AO_PERSONAL_MULTI_DACS BIT(15) /* M-Series only */ 416#define NISTC_AO_PERSONAL_NUM_DAC BIT(14) /* 1:single; 0:dual */ 417#define NISTC_AO_PERSONAL_FAST_CPU BIT(13) /* M-Series reserved */ 418#define NISTC_AO_PERSONAL_TMRDACWR_PW BIT(12) 419#define NISTC_AO_PERSONAL_FIFO_FLAGS_POL BIT(11) /* M-Series reserved */ 420#define NISTC_AO_PERSONAL_FIFO_ENA BIT(10) 421#define NISTC_AO_PERSONAL_AOFREQ_POL BIT(9) /* M-Series reserved */ 422#define NISTC_AO_PERSONAL_DMA_PIO_CTRL BIT(8) /* M-Series reserved */ 423#define NISTC_AO_PERSONAL_UPDATE_ORIG_PULSE BIT(7) 424#define NISTC_AO_PERSONAL_UPDATE_TIMEBASE BIT(6) 425#define NISTC_AO_PERSONAL_UPDATE_PW BIT(5) 426#define NISTC_AO_PERSONAL_BC_SRC_SEL BIT(4) 427#define NISTC_AO_PERSONAL_INTERVAL_BUFFER_MODE BIT(3) 428 429#define NISTC_RTSI_TRIGA_OUT_REG 79 430#define NISTC_RTSI_TRIGB_OUT_REG 80 431#define NISTC_RTSI_TRIGB_SUB_SEL1 BIT(15) /* not for M-Series */ 432#define NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT 15 /* not for M-Series */ 433#define NISTC_RTSI_TRIG(_c, _s) (((_s) & 0xf) << (((_c) % 4) * 4)) 434#define NISTC_RTSI_TRIG_MASK(_c) NISTC_RTSI_TRIG((_c), 0xf) 435#define NISTC_RTSI_TRIG_TO_SRC(_c, _b) (((_b) >> (((_c) % 4) * 4)) & 0xf) 436 437#define NISTC_RTSI_BOARD_REG 81 438 439#define NISTC_CFG_MEM_CLR_REG 82 440#define NISTC_ADC_FIFO_CLR_REG 83 441#define NISTC_DAC_FIFO_CLR_REG 84 442#define NISTC_WR_STROBE3_REG 85 443 444#define NISTC_AO_OUT_CTRL_REG 86 445#define NISTC_AO_OUT_CTRL_EXT_GATE_ENA BIT(15) 446#define NISTC_AO_OUT_CTRL_EXT_GATE_SEL(x) (((x) & 0x1f) << 10) 447#define NISTC_AO_OUT_CTRL_CHANS(x) (((x) & 0xf) << 6) 448#define NISTC_AO_OUT_CTRL_UPDATE2_SEL(x) (((x) & 0x3) << 4) 449#define NISTC_AO_OUT_CTRL_EXT_GATE_POL BIT(3) 450#define NISTC_AO_OUT_CTRL_UPDATE2_TOGGLE BIT(2) 451#define NISTC_AO_OUT_CTRL_UPDATE_SEL(x) (((x) & 0x3) << 0) 452#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ NISTC_AO_OUT_CTRL_UPDATE_SEL(0) 453#define NISTC_AO_OUT_CTRL_UPDATE_SEL_GND NISTC_AO_OUT_CTRL_UPDATE_SEL(1) 454#define NISTC_AO_OUT_CTRL_UPDATE_SEL_LOW NISTC_AO_OUT_CTRL_UPDATE_SEL(2) 455#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGH NISTC_AO_OUT_CTRL_UPDATE_SEL(3) 456 457#define NISTC_AI_MODE3_REG 87 458#define NISTC_AI_MODE3_TRIG_LEN BIT(15) 459#define NISTC_AI_MODE3_DELAY_START BIT(14) 460#define NISTC_AI_MODE3_SOFTWARE_GATE BIT(13) 461#define NISTC_AI_MODE3_SI_TRIG_DELAY BIT(12) 462#define NISTC_AI_MODE3_SI2_SRC_SEL BIT(11) 463#define NISTC_AI_MODE3_DELAYED_START2 BIT(10) 464#define NISTC_AI_MODE3_DELAYED_START1 BIT(9) 465#define NISTC_AI_MODE3_EXT_GATE_MODE BIT(8) 466#define NISTC_AI_MODE3_FIFO_MODE(x) (((x) & 0x3) << 6) 467#define NISTC_AI_MODE3_FIFO_MODE_NE NISTC_AI_MODE3_FIFO_MODE(0) 468#define NISTC_AI_MODE3_FIFO_MODE_HF NISTC_AI_MODE3_FIFO_MODE(1) 469#define NISTC_AI_MODE3_FIFO_MODE_F NISTC_AI_MODE3_FIFO_MODE(2) 470#define NISTC_AI_MODE3_FIFO_MODE_HF_E NISTC_AI_MODE3_FIFO_MODE(3) 471#define NISTC_AI_MODE3_EXT_GATE_POL BIT(5) 472#define NISTC_AI_MODE3_EXT_GATE_SEL(x) (((x) & 0x1f) << 0) 473 474#define NISTC_AI_STATUS1_REG 2 475#define NISTC_AI_STATUS1_INTA BIT(15) 476#define NISTC_AI_STATUS1_FIFO_F BIT(14) 477#define NISTC_AI_STATUS1_FIFO_HF BIT(13) 478#define NISTC_AI_STATUS1_FIFO_E BIT(12) 479#define NISTC_AI_STATUS1_OVERRUN BIT(11) 480#define NISTC_AI_STATUS1_OVERFLOW BIT(10) 481#define NISTC_AI_STATUS1_SC_TC_ERR BIT(9) 482#define NISTC_AI_STATUS1_OVER (NISTC_AI_STATUS1_OVERRUN | \ 483 NISTC_AI_STATUS1_OVERFLOW) 484#define NISTC_AI_STATUS1_ERR (NISTC_AI_STATUS1_OVER | \ 485 NISTC_AI_STATUS1_SC_TC_ERR) 486#define NISTC_AI_STATUS1_START2 BIT(8) 487#define NISTC_AI_STATUS1_START1 BIT(7) 488#define NISTC_AI_STATUS1_SC_TC BIT(6) 489#define NISTC_AI_STATUS1_START BIT(5) 490#define NISTC_AI_STATUS1_STOP BIT(4) 491#define NISTC_AI_STATUS1_G0_TC BIT(3) 492#define NISTC_AI_STATUS1_G0_GATE BIT(2) 493#define NISTC_AI_STATUS1_FIFO_REQ BIT(1) 494#define NISTC_AI_STATUS1_PASSTHRU0 BIT(0) 495 496#define NISTC_AO_STATUS1_REG 3 497#define NISTC_AO_STATUS1_INTB BIT(15) 498#define NISTC_AO_STATUS1_FIFO_F BIT(14) 499#define NISTC_AO_STATUS1_FIFO_HF BIT(13) 500#define NISTC_AO_STATUS1_FIFO_E BIT(12) 501#define NISTC_AO_STATUS1_BC_TC_ERR BIT(11) 502#define NISTC_AO_STATUS1_START BIT(10) 503#define NISTC_AO_STATUS1_OVERRUN BIT(9) 504#define NISTC_AO_STATUS1_START1 BIT(8) 505#define NISTC_AO_STATUS1_BC_TC BIT(7) 506#define NISTC_AO_STATUS1_UC_TC BIT(6) 507#define NISTC_AO_STATUS1_UPDATE BIT(5) 508#define NISTC_AO_STATUS1_UI2_TC BIT(4) 509#define NISTC_AO_STATUS1_G1_TC BIT(3) 510#define NISTC_AO_STATUS1_G1_GATE BIT(2) 511#define NISTC_AO_STATUS1_FIFO_REQ BIT(1) 512#define NISTC_AO_STATUS1_PASSTHRU1 BIT(0) 513 514#define NISTC_G01_STATUS_REG 4 515 516#define NISTC_AI_STATUS2_REG 5 517 518#define NISTC_AO_STATUS2_REG 6 519 520#define NISTC_DIO_IN_REG 7 521 522#define NISTC_G0_HW_SAVE_REG 8 523#define NISTC_G1_HW_SAVE_REG 10 524 525#define NISTC_G0_SAVE_REG 12 526#define NISTC_G1_SAVE_REG 14 527 528#define NISTC_AO_UI_SAVE_REG 16 529#define NISTC_AO_BC_SAVE_REG 18 530#define NISTC_AO_UC_SAVE_REG 20 531 532#define NISTC_STATUS1_REG 27 533#define NISTC_STATUS1_SERIO_IN_PROG BIT(12) 534 535#define NISTC_DIO_SERIAL_IN_REG 28 536 537#define NISTC_STATUS2_REG 29 538#define NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS BIT(5) 539 540#define NISTC_AI_SI_SAVE_REG 64 541#define NISTC_AI_SC_SAVE_REG 66 542 543/* 544 * PCI E Series Registers 545 */ 546#define NI_E_STC_WINDOW_ADDR_REG 0x00 /* rw16 */ 547#define NI_E_STC_WINDOW_DATA_REG 0x02 /* rw16 */ 548 549#define NI_E_STATUS_REG 0x01 /* r8 */ 550#define NI_E_STATUS_AI_FIFO_LOWER_NE BIT(3) 551#define NI_E_STATUS_PROMOUT BIT(0) 552 553#define NI_E_DMA_AI_AO_SEL_REG 0x09 /* w8 */ 554#define NI_E_DMA_AI_SEL(x) (((x) & 0xf) << 0) 555#define NI_E_DMA_AI_SEL_MASK NI_E_DMA_AI_SEL(0xf) 556#define NI_E_DMA_AO_SEL(x) (((x) & 0xf) << 4) 557#define NI_E_DMA_AO_SEL_MASK NI_E_DMA_AO_SEL(0xf) 558 559#define NI_E_DMA_G0_G1_SEL_REG 0x0b /* w8 */ 560#define NI_E_DMA_G0_G1_SEL(_g, _c) (((_c) & 0xf) << ((_g) * 4)) 561#define NI_E_DMA_G0_G1_SEL_MASK(_g) NI_E_DMA_G0_G1_SEL((_g), 0xf) 562 563#define NI_E_SERIAL_CMD_REG 0x0d /* w8 */ 564#define NI_E_SERIAL_CMD_DAC_LD(x) BIT(3 + (x)) 565#define NI_E_SERIAL_CMD_EEPROM_CS BIT(2) 566#define NI_E_SERIAL_CMD_SDATA BIT(1) 567#define NI_E_SERIAL_CMD_SCLK BIT(0) 568 569#define NI_E_MISC_CMD_REG 0x0f /* w8 */ 570#define NI_E_MISC_CMD_INTEXT_ATRIG(x) (((x) & 0x1) << 7) 571#define NI_E_MISC_CMD_EXT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(0) 572#define NI_E_MISC_CMD_INT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(1) 573 574#define NI_E_AI_CFG_LO_REG 0x10 /* w16 */ 575#define NI_E_AI_CFG_LO_LAST_CHAN BIT(15) 576#define NI_E_AI_CFG_LO_GEN_TRIG BIT(12) 577#define NI_E_AI_CFG_LO_DITHER BIT(9) 578#define NI_E_AI_CFG_LO_UNI BIT(8) 579#define NI_E_AI_CFG_LO_GAIN(x) ((x) << 0) 580 581#define NI_E_AI_CFG_HI_REG 0x12 /* w16 */ 582#define NI_E_AI_CFG_HI_TYPE(x) (((x) & 0x7) << 12) 583#define NI_E_AI_CFG_HI_TYPE_DIFF NI_E_AI_CFG_HI_TYPE(1) 584#define NI_E_AI_CFG_HI_TYPE_COMMON NI_E_AI_CFG_HI_TYPE(2) 585#define NI_E_AI_CFG_HI_TYPE_GROUND NI_E_AI_CFG_HI_TYPE(3) 586#define NI_E_AI_CFG_HI_AC_COUPLE BIT(11) 587#define NI_E_AI_CFG_HI_CHAN(x) (((x) & 0x3f) << 0) 588 589#define NI_E_AO_CFG_REG 0x16 /* w16 */ 590#define NI_E_AO_DACSEL(x) ((x) << 8) 591#define NI_E_AO_GROUND_REF BIT(3) 592#define NI_E_AO_EXT_REF BIT(2) 593#define NI_E_AO_DEGLITCH BIT(1) 594#define NI_E_AO_CFG_BIP BIT(0) 595 596#define NI_E_DAC_DIRECT_DATA_REG(x) (0x18 + ((x) * 2)) /* w16 */ 597 598#define NI_E_8255_BASE 0x19 /* rw8 */ 599 600#define NI_E_AI_FIFO_DATA_REG 0x1c /* r16 */ 601 602#define NI_E_AO_FIFO_DATA_REG 0x1e /* w16 */ 603 604/* 605 * 611x registers (these boards differ from the e-series) 606 */ 607#define NI611X_MAGIC_REG 0x19 /* w8 (new) */ 608#define NI611X_CALIB_CHAN_SEL_REG 0x1a /* w16 (new) */ 609#define NI611X_AI_FIFO_DATA_REG 0x1c /* r32 (incompatible) */ 610#define NI611X_AI_FIFO_OFFSET_LOAD_REG 0x05 /* r8 (new) */ 611#define NI611X_AO_FIFO_DATA_REG 0x14 /* w32 (incompatible) */ 612#define NI611X_CAL_GAIN_SEL_REG 0x05 /* w8 (new) */ 613 614#define NI611X_AO_WINDOW_ADDR_REG 0x18 615#define NI611X_AO_WINDOW_DATA_REG 0x1e 616 617/* 618 * 6143 registers 619 */ 620#define NI6143_MAGIC_REG 0x19 /* w8 */ 621#define NI6143_DMA_G0_G1_SEL_REG 0x0b /* w8 */ 622#define NI6143_PIPELINE_DELAY_REG 0x1f /* w8 */ 623#define NI6143_EOC_SET_REG 0x1d /* w8 */ 624#define NI6143_DMA_AI_SEL_REG 0x09 /* w8 */ 625#define NI6143_AI_FIFO_DATA_REG 0x8c /* r32 */ 626#define NI6143_AI_FIFO_FLAG_REG 0x84 /* w32 */ 627#define NI6143_AI_FIFO_CTRL_REG 0x88 /* w32 */ 628#define NI6143_AI_FIFO_STATUS_REG 0x88 /* r32 */ 629#define NI6143_AI_FIFO_DMA_THRESH_REG 0x90 /* w32 */ 630#define NI6143_AI_FIFO_WORDS_AVAIL_REG 0x94 /* w32 */ 631 632#define NI6143_CALIB_CHAN_REG 0x42 /* w16 */ 633#define NI6143_CALIB_CHAN_RELAY_ON BIT(15) 634#define NI6143_CALIB_CHAN_RELAY_OFF BIT(14) 635#define NI6143_CALIB_CHAN(x) (((x) & 0xf) << 0) 636#define NI6143_CALIB_CHAN_GND_GND NI6143_CALIB_CHAN(0) /* Offset Cal */ 637#define NI6143_CALIB_CHAN_2V5_GND NI6143_CALIB_CHAN(2) /* 2.5V ref */ 638#define NI6143_CALIB_CHAN_PWM_GND NI6143_CALIB_CHAN(5) /* +-5V Self Cal */ 639#define NI6143_CALIB_CHAN_2V5_PWM NI6143_CALIB_CHAN(10) /* PWM Cal */ 640#define NI6143_CALIB_CHAN_PWM_PWM NI6143_CALIB_CHAN(13) /* CMRR */ 641#define NI6143_CALIB_CHAN_GND_PWM NI6143_CALIB_CHAN(14) /* PWM Cal */ 642#define NI6143_CALIB_LO_TIME_REG 0x20 /* w16 */ 643#define NI6143_CALIB_HI_TIME_REG 0x22 /* w16 */ 644#define NI6143_RELAY_COUNTER_LOAD_REG 0x4c /* w32 */ 645#define NI6143_SIGNATURE_REG 0x50 /* w32 */ 646#define NI6143_RELEASE_DATE_REG 0x54 /* w32 */ 647#define NI6143_RELEASE_OLDEST_DATE_REG 0x58 /* w32 */ 648 649/* 650 * 671x, 611x windowed ao registers 651 */ 652#define NI671X_DAC_DIRECT_DATA_REG(x) (0x00 + (x)) /* w16 */ 653#define NI611X_AO_TIMED_REG 0x10 /* w16 */ 654#define NI671X_AO_IMMEDIATE_REG 0x11 /* w16 */ 655#define NI611X_AO_FIFO_OFFSET_LOAD_REG 0x13 /* w32 */ 656#define NI67XX_AO_SP_UPDATES_REG 0x14 /* w16 */ 657#define NI611X_AO_WAVEFORM_GEN_REG 0x15 /* w16 */ 658#define NI611X_AO_MISC_REG 0x16 /* w16 */ 659#define NI611X_AO_MISC_CLEAR_WG BIT(0) 660#define NI67XX_AO_CAL_CHAN_SEL_REG 0x17 /* w16 */ 661#define NI67XX_AO_CFG2_REG 0x18 /* w16 */ 662#define NI67XX_CAL_CMD_REG 0x19 /* w16 */ 663#define NI67XX_CAL_STATUS_REG 0x1a /* r8 */ 664#define NI67XX_CAL_STATUS_BUSY BIT(0) 665#define NI67XX_CAL_STATUS_OSC_DETECT BIT(1) 666#define NI67XX_CAL_STATUS_OVERRANGE BIT(2) 667#define NI67XX_CAL_DATA_REG 0x1b /* r16 */ 668#define NI67XX_CAL_CFG_HI_REG 0x1c /* rw16 */ 669#define NI67XX_CAL_CFG_LO_REG 0x1d /* rw16 */ 670 671#define CS5529_CMD_CB BIT(7) 672#define CS5529_CMD_SINGLE_CONV BIT(6) 673#define CS5529_CMD_CONT_CONV BIT(5) 674#define CS5529_CMD_READ BIT(4) 675#define CS5529_CMD_REG(x) (((x) & 0x7) << 1) 676#define CS5529_CMD_REG_MASK CS5529_CMD_REG(7) 677#define CS5529_CMD_PWR_SAVE BIT(0) 678 679#define CS5529_OFFSET_REG CS5529_CMD_REG(0) 680#define CS5529_GAIN_REG CS5529_CMD_REG(1) 681#define CS5529_CONV_DATA_REG CS5529_CMD_REG(3) 682#define CS5529_SETUP_REG CS5529_CMD_REG(4) 683 684#define CS5529_CFG_REG CS5529_CMD_REG(2) 685#define CS5529_CFG_AOUT(x) BIT(22 + (x)) 686#define CS5529_CFG_DOUT(x) BIT(18 + (x)) 687#define CS5529_CFG_LOW_PWR_MODE BIT(16) 688#define CS5529_CFG_WORD_RATE(x) (((x) & 0x7) << 13) 689#define CS5529_CFG_WORD_RATE_MASK CS5529_CFG_WORD_RATE(0x7) 690#define CS5529_CFG_WORD_RATE_2180 CS5529_CFG_WORD_RATE(0) 691#define CS5529_CFG_WORD_RATE_1092 CS5529_CFG_WORD_RATE(1) 692#define CS5529_CFG_WORD_RATE_532 CS5529_CFG_WORD_RATE(2) 693#define CS5529_CFG_WORD_RATE_388 CS5529_CFG_WORD_RATE(3) 694#define CS5529_CFG_WORD_RATE_324 CS5529_CFG_WORD_RATE(4) 695#define CS5529_CFG_WORD_RATE_17444 CS5529_CFG_WORD_RATE(5) 696#define CS5529_CFG_WORD_RATE_8724 CS5529_CFG_WORD_RATE(6) 697#define CS5529_CFG_WORD_RATE_4364 CS5529_CFG_WORD_RATE(7) 698#define CS5529_CFG_UNIPOLAR BIT(12) 699#define CS5529_CFG_RESET BIT(7) 700#define CS5529_CFG_RESET_VALID BIT(6) 701#define CS5529_CFG_PORT_FLAG BIT(5) 702#define CS5529_CFG_PWR_SAVE_SEL BIT(4) 703#define CS5529_CFG_DONE_FLAG BIT(3) 704#define CS5529_CFG_CALIB(x) (((x) & 0x7) << 0) 705#define CS5529_CFG_CALIB_NONE CS5529_CFG_CALIB(0) 706#define CS5529_CFG_CALIB_OFFSET_SELF CS5529_CFG_CALIB(1) 707#define CS5529_CFG_CALIB_GAIN_SELF CS5529_CFG_CALIB(2) 708#define CS5529_CFG_CALIB_BOTH_SELF CS5529_CFG_CALIB(3) 709#define CS5529_CFG_CALIB_OFFSET_SYS CS5529_CFG_CALIB(5) 710#define CS5529_CFG_CALIB_GAIN_SYS CS5529_CFG_CALIB(6) 711 712/* 713 * M-Series specific registers not handled by the DAQ-STC and GPCT register 714 * remapping. 715 */ 716#define NI_M_CDIO_DMA_SEL_REG 0x007 717#define NI_M_CDIO_DMA_SEL_CDO(x) (((x) & 0xf) << 4) 718#define NI_M_CDIO_DMA_SEL_CDO_MASK NI_M_CDIO_DMA_SEL_CDO(0xf) 719#define NI_M_CDIO_DMA_SEL_CDI(x) (((x) & 0xf) << 0) 720#define NI_M_CDIO_DMA_SEL_CDI_MASK NI_M_CDIO_DMA_SEL_CDI(0xf) 721#define NI_M_SCXI_STATUS_REG 0x007 722#define NI_M_AI_AO_SEL_REG 0x009 723#define NI_M_G0_G1_SEL_REG 0x00b 724#define NI_M_MISC_CMD_REG 0x00f 725#define NI_M_SCXI_SER_DO_REG 0x011 726#define NI_M_SCXI_CTRL_REG 0x013 727#define NI_M_SCXI_OUT_ENA_REG 0x015 728#define NI_M_AI_FIFO_DATA_REG 0x01c 729#define NI_M_DIO_REG 0x024 730#define NI_M_DIO_DIR_REG 0x028 731#define NI_M_CAL_PWM_REG 0x040 732#define NI_M_CAL_PWM_HIGH_TIME(x) (((x) & 0xffff) << 16) 733#define NI_M_CAL_PWM_LOW_TIME(x) (((x) & 0xffff) << 0) 734#define NI_M_GEN_PWM_REG(x) (0x044 + ((x) * 2)) 735#define NI_M_AI_CFG_FIFO_DATA_REG 0x05e 736#define NI_M_AI_CFG_LAST_CHAN BIT(14) 737#define NI_M_AI_CFG_DITHER BIT(13) 738#define NI_M_AI_CFG_POLARITY BIT(12) 739#define NI_M_AI_CFG_GAIN(x) (((x) & 0x7) << 9) 740#define NI_M_AI_CFG_CHAN_TYPE(x) (((x) & 0x7) << 6) 741#define NI_M_AI_CFG_CHAN_TYPE_MASK NI_M_AI_CFG_CHAN_TYPE(7) 742#define NI_M_AI_CFG_CHAN_TYPE_CALIB NI_M_AI_CFG_CHAN_TYPE(0) 743#define NI_M_AI_CFG_CHAN_TYPE_DIFF NI_M_AI_CFG_CHAN_TYPE(1) 744#define NI_M_AI_CFG_CHAN_TYPE_COMMON NI_M_AI_CFG_CHAN_TYPE(2) 745#define NI_M_AI_CFG_CHAN_TYPE_GROUND NI_M_AI_CFG_CHAN_TYPE(3) 746#define NI_M_AI_CFG_CHAN_TYPE_AUX NI_M_AI_CFG_CHAN_TYPE(5) 747#define NI_M_AI_CFG_CHAN_TYPE_GHOST NI_M_AI_CFG_CHAN_TYPE(7) 748#define NI_M_AI_CFG_BANK_SEL(x) ((((x) & 0x40) << 4) | ((x) & 0x30)) 749#define NI_M_AI_CFG_CHAN_SEL(x) (((x) & 0xf) << 0) 750#define NI_M_INTC_ENA_REG 0x088 751#define NI_M_INTC_ENA BIT(0) 752#define NI_M_INTC_STATUS_REG 0x088 753#define NI_M_INTC_STATUS BIT(0) 754#define NI_M_ATRIG_CTRL_REG 0x08c 755#define NI_M_AO_SER_INT_ENA_REG 0x0a0 756#define NI_M_AO_SER_INT_ACK_REG 0x0a1 757#define NI_M_AO_SER_INT_STATUS_REG 0x0a1 758#define NI_M_AO_CALIB_REG 0x0a3 759#define NI_M_AO_FIFO_DATA_REG 0x0a4 760#define NI_M_PFI_FILTER_REG 0x0b0 761#define NI_M_PFI_FILTER_SEL(_c, _f) (((_f) & 0x3) << ((_c) * 2)) 762#define NI_M_PFI_FILTER_SEL_MASK(_c) NI_M_PFI_FILTER_SEL((_c), 0x3) 763#define NI_M_RTSI_FILTER_REG 0x0b4 764#define NI_M_SCXI_LEGACY_COMPAT_REG 0x0bc 765#define NI_M_DAC_DIRECT_DATA_REG(x) (0x0c0 + ((x) * 4)) 766#define NI_M_AO_WAVEFORM_ORDER_REG(x) (0x0c2 + ((x) * 4)) 767#define NI_M_AO_CFG_BANK_REG(x) (0x0c3 + ((x) * 4)) 768#define NI_M_AO_CFG_BANK_BIPOLAR BIT(7) 769#define NI_M_AO_CFG_BANK_UPDATE_TIMED BIT(6) 770#define NI_M_AO_CFG_BANK_REF(x) (((x) & 0x7) << 3) 771#define NI_M_AO_CFG_BANK_REF_MASK NI_M_AO_CFG_BANK_REF(7) 772#define NI_M_AO_CFG_BANK_REF_INT_10V NI_M_AO_CFG_BANK_REF(0) 773#define NI_M_AO_CFG_BANK_REF_INT_5V NI_M_AO_CFG_BANK_REF(1) 774#define NI_M_AO_CFG_BANK_OFFSET(x) (((x) & 0x7) << 0) 775#define NI_M_AO_CFG_BANK_OFFSET_MASK NI_M_AO_CFG_BANK_OFFSET(7) 776#define NI_M_AO_CFG_BANK_OFFSET_0V NI_M_AO_CFG_BANK_OFFSET(0) 777#define NI_M_AO_CFG_BANK_OFFSET_5V NI_M_AO_CFG_BANK_OFFSET(1) 778#define NI_M_RTSI_SHARED_MUX_REG 0x1a2 779#define NI_M_CLK_FOUT2_REG 0x1c4 780#define NI_M_CLK_FOUT2_RTSI_10MHZ BIT(7) 781#define NI_M_CLK_FOUT2_TIMEBASE3_PLL BIT(6) 782#define NI_M_CLK_FOUT2_TIMEBASE1_PLL BIT(5) 783#define NI_M_CLK_FOUT2_PLL_SRC(x) (((x) & 0x1f) << 0) 784#define NI_M_CLK_FOUT2_PLL_SRC_MASK NI_M_CLK_FOUT2_PLL_SRC(0x1f) 785#define NI_M_MAX_RTSI_CHAN 7 786#define NI_M_CLK_FOUT2_PLL_SRC_RTSI(x) (((x) == NI_M_MAX_RTSI_CHAN) \ 787 ? NI_M_CLK_FOUT2_PLL_SRC(0x1b) \ 788 : NI_M_CLK_FOUT2_PLL_SRC(0xb + (x))) 789#define NI_M_CLK_FOUT2_PLL_SRC_STAR NI_M_CLK_FOUT2_PLL_SRC(0x14) 790#define NI_M_CLK_FOUT2_PLL_SRC_PXI10 NI_M_CLK_FOUT2_PLL_SRC(0x1d) 791#define NI_M_PLL_CTRL_REG 0x1c6 792#define NI_M_PLL_CTRL_VCO_MODE(x) (((x) & 0x3) << 13) 793#define NI_M_PLL_CTRL_VCO_MODE_200_325MHZ NI_M_PLL_CTRL_VCO_MODE(0) 794#define NI_M_PLL_CTRL_VCO_MODE_175_225MHZ NI_M_PLL_CTRL_VCO_MODE(1) 795#define NI_M_PLL_CTRL_VCO_MODE_100_225MHZ NI_M_PLL_CTRL_VCO_MODE(2) 796#define NI_M_PLL_CTRL_VCO_MODE_75_150MHZ NI_M_PLL_CTRL_VCO_MODE(3) 797#define NI_M_PLL_CTRL_ENA BIT(12) 798#define NI_M_PLL_MAX_DIVISOR 0x10 799#define NI_M_PLL_CTRL_DIVISOR(x) (((x) & 0xf) << 8) 800#define NI_M_PLL_MAX_MULTIPLIER 0x100 801#define NI_M_PLL_CTRL_MULTIPLIER(x) (((x) & 0xff) << 0) 802#define NI_M_PLL_STATUS_REG 0x1c8 803#define NI_M_PLL_STATUS_LOCKED BIT(0) 804#define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2)) 805#define NI_M_PFI_CHAN(_c) (((_c) % 3) * 5) 806#define NI_M_PFI_OUT_SEL(_c, _s) (((_s) & 0x1f) << NI_M_PFI_CHAN(_c)) 807#define NI_M_PFI_OUT_SEL_MASK(_c) (0x1f << NI_M_PFI_CHAN(_c)) 808#define NI_M_PFI_OUT_SEL_TO_SRC(_c, _b) (((_b) >> NI_M_PFI_CHAN(_c)) & 0x1f) 809#define NI_M_PFI_DI_REG 0x1dc 810#define NI_M_PFI_DO_REG 0x1de 811#define NI_M_CFG_BYPASS_FIFO_REG 0x218 812#define NI_M_CFG_BYPASS_FIFO BIT(31) 813#define NI_M_CFG_BYPASS_AI_POLARITY BIT(22) 814#define NI_M_CFG_BYPASS_AI_DITHER BIT(21) 815#define NI_M_CFG_BYPASS_AI_GAIN(x) (((x) & 0x7) << 18) 816#define NI_M_CFG_BYPASS_AO_CAL(x) (((x) & 0xf) << 15) 817#define NI_M_CFG_BYPASS_AO_CAL_MASK NI_M_CFG_BYPASS_AO_CAL(0xf) 818#define NI_M_CFG_BYPASS_AI_MODE_MUX(x) (((x) & 0x3) << 13) 819#define NI_M_CFG_BYPASS_AI_MODE_MUX_MASK NI_M_CFG_BYPASS_AI_MODE_MUX(3) 820#define NI_M_CFG_BYPASS_AI_CAL_NEG(x) (((x) & 0x7) << 10) 821#define NI_M_CFG_BYPASS_AI_CAL_NEG_MASK NI_M_CFG_BYPASS_AI_CAL_NEG(7) 822#define NI_M_CFG_BYPASS_AI_CAL_POS(x) (((x) & 0x7) << 7) 823#define NI_M_CFG_BYPASS_AI_CAL_POS_MASK NI_M_CFG_BYPASS_AI_CAL_POS(7) 824#define NI_M_CFG_BYPASS_AI_CAL_MASK (NI_M_CFG_BYPASS_AI_CAL_POS_MASK | \ 825 NI_M_CFG_BYPASS_AI_CAL_NEG_MASK | \ 826 NI_M_CFG_BYPASS_AI_MODE_MUX_MASK | \ 827 NI_M_CFG_BYPASS_AO_CAL_MASK) 828#define NI_M_CFG_BYPASS_AI_BANK(x) (((x) & 0xf) << 3) 829#define NI_M_CFG_BYPASS_AI_BANK_MASK NI_M_CFG_BYPASS_AI_BANK(0xf) 830#define NI_M_CFG_BYPASS_AI_CHAN(x) (((x) & 0x7) << 0) 831#define NI_M_CFG_BYPASS_AI_CHAN_MASK NI_M_CFG_BYPASS_AI_CHAN(7) 832#define NI_M_SCXI_DIO_ENA_REG 0x21c 833#define NI_M_CDI_FIFO_DATA_REG 0x220 834#define NI_M_CDO_FIFO_DATA_REG 0x220 835#define NI_M_CDIO_STATUS_REG 0x224 836#define NI_M_CDIO_STATUS_CDI_OVERFLOW BIT(20) 837#define NI_M_CDIO_STATUS_CDI_OVERRUN BIT(19) 838#define NI_M_CDIO_STATUS_CDI_ERROR (NI_M_CDIO_STATUS_CDI_OVERFLOW | \ 839 NI_M_CDIO_STATUS_CDI_OVERRUN) 840#define NI_M_CDIO_STATUS_CDI_FIFO_REQ BIT(18) 841#define NI_M_CDIO_STATUS_CDI_FIFO_FULL BIT(17) 842#define NI_M_CDIO_STATUS_CDI_FIFO_EMPTY BIT(16) 843#define NI_M_CDIO_STATUS_CDO_UNDERFLOW BIT(4) 844#define NI_M_CDIO_STATUS_CDO_OVERRUN BIT(3) 845#define NI_M_CDIO_STATUS_CDO_ERROR (NI_M_CDIO_STATUS_CDO_UNDERFLOW | \ 846 NI_M_CDIO_STATUS_CDO_OVERRUN) 847#define NI_M_CDIO_STATUS_CDO_FIFO_REQ BIT(2) 848#define NI_M_CDIO_STATUS_CDO_FIFO_FULL BIT(1) 849#define NI_M_CDIO_STATUS_CDO_FIFO_EMPTY BIT(0) 850#define NI_M_CDIO_CMD_REG 0x224 851#define NI_M_CDI_CMD_SW_UPDATE BIT(20) 852#define NI_M_CDO_CMD_SW_UPDATE BIT(19) 853#define NI_M_CDO_CMD_F_E_INT_ENA_CLR BIT(17) 854#define NI_M_CDO_CMD_F_E_INT_ENA_SET BIT(16) 855#define NI_M_CDI_CMD_ERR_INT_CONFIRM BIT(15) 856#define NI_M_CDO_CMD_ERR_INT_CONFIRM BIT(14) 857#define NI_M_CDI_CMD_F_REQ_INT_ENA_CLR BIT(13) 858#define NI_M_CDI_CMD_F_REQ_INT_ENA_SET BIT(12) 859#define NI_M_CDO_CMD_F_REQ_INT_ENA_CLR BIT(11) 860#define NI_M_CDO_CMD_F_REQ_INT_ENA_SET BIT(10) 861#define NI_M_CDI_CMD_ERR_INT_ENA_CLR BIT(9) 862#define NI_M_CDI_CMD_ERR_INT_ENA_SET BIT(8) 863#define NI_M_CDO_CMD_ERR_INT_ENA_CLR BIT(7) 864#define NI_M_CDO_CMD_ERR_INT_ENA_SET BIT(6) 865#define NI_M_CDI_CMD_RESET BIT(5) 866#define NI_M_CDO_CMD_RESET BIT(4) 867#define NI_M_CDI_CMD_ARM BIT(3) 868#define NI_M_CDI_CMD_DISARM BIT(2) 869#define NI_M_CDO_CMD_ARM BIT(1) 870#define NI_M_CDO_CMD_DISARM BIT(0) 871#define NI_M_CDI_MODE_REG 0x228 872#define NI_M_CDI_MODE_DATA_LANE(x) (((x) & 0x3) << 12) 873#define NI_M_CDI_MODE_DATA_LANE_MASK NI_M_CDI_MODE_DATA_LANE(3) 874#define NI_M_CDI_MODE_DATA_LANE_0_15 NI_M_CDI_MODE_DATA_LANE(0) 875#define NI_M_CDI_MODE_DATA_LANE_16_31 NI_M_CDI_MODE_DATA_LANE(1) 876#define NI_M_CDI_MODE_DATA_LANE_0_7 NI_M_CDI_MODE_DATA_LANE(0) 877#define NI_M_CDI_MODE_DATA_LANE_8_15 NI_M_CDI_MODE_DATA_LANE(1) 878#define NI_M_CDI_MODE_DATA_LANE_16_23 NI_M_CDI_MODE_DATA_LANE(2) 879#define NI_M_CDI_MODE_DATA_LANE_24_31 NI_M_CDI_MODE_DATA_LANE(3) 880#define NI_M_CDI_MODE_FIFO_MODE BIT(11) 881#define NI_M_CDI_MODE_POLARITY BIT(10) 882#define NI_M_CDI_MODE_HALT_ON_ERROR BIT(9) 883#define NI_M_CDI_MODE_SAMPLE_SRC(x) (((x) & 0x3f) << 0) 884#define NI_M_CDI_MODE_SAMPLE_SRC_MASK NI_M_CDI_MODE_SAMPLE_SRC(0x3f) 885#define NI_M_CDO_MODE_REG 0x22c 886#define NI_M_CDO_MODE_DATA_LANE(x) (((x) & 0x3) << 12) 887#define NI_M_CDO_MODE_DATA_LANE_MASK NI_M_CDO_MODE_DATA_LANE(3) 888#define NI_M_CDO_MODE_DATA_LANE_0_15 NI_M_CDO_MODE_DATA_LANE(0) 889#define NI_M_CDO_MODE_DATA_LANE_16_31 NI_M_CDO_MODE_DATA_LANE(1) 890#define NI_M_CDO_MODE_DATA_LANE_0_7 NI_M_CDO_MODE_DATA_LANE(0) 891#define NI_M_CDO_MODE_DATA_LANE_8_15 NI_M_CDO_MODE_DATA_LANE(1) 892#define NI_M_CDO_MODE_DATA_LANE_16_23 NI_M_CDO_MODE_DATA_LANE(2) 893#define NI_M_CDO_MODE_DATA_LANE_24_31 NI_M_CDO_MODE_DATA_LANE(3) 894#define NI_M_CDO_MODE_FIFO_MODE BIT(11) 895#define NI_M_CDO_MODE_POLARITY BIT(10) 896#define NI_M_CDO_MODE_HALT_ON_ERROR BIT(9) 897#define NI_M_CDO_MODE_RETRANSMIT BIT(8) 898#define NI_M_CDO_MODE_SAMPLE_SRC(x) (((x) & 0x3f) << 0) 899#define NI_M_CDO_MODE_SAMPLE_SRC_MASK NI_M_CDO_MODE_SAMPLE_SRC(0x3f) 900#define NI_M_CDI_MASK_ENA_REG 0x230 901#define NI_M_CDO_MASK_ENA_REG 0x234 902#define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064) 903#define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x)) 904#define NI_M_AO_REF_ATTENUATION_X5 BIT(0) 905 906enum { 907 ai_gain_16 = 0, 908 ai_gain_8, 909 ai_gain_14, 910 ai_gain_4, 911 ai_gain_611x, 912 ai_gain_622x, 913 ai_gain_628x, 914 ai_gain_6143 915}; 916 917enum caldac_enum { 918 caldac_none = 0, 919 mb88341, 920 dac8800, 921 dac8043, 922 ad8522, 923 ad8804, 924 ad8842, 925 ad8804_debug 926}; 927 928enum ni_reg_type { 929 ni_reg_normal = 0x0, 930 ni_reg_611x = 0x1, 931 ni_reg_6711 = 0x2, 932 ni_reg_6713 = 0x4, 933 ni_reg_67xx_mask = 0x6, 934 ni_reg_6xxx_mask = 0x7, 935 ni_reg_622x = 0x8, 936 ni_reg_625x = 0x10, 937 ni_reg_628x = 0x18, 938 ni_reg_m_series_mask = 0x18, 939 ni_reg_6143 = 0x20 940}; 941 942struct ni_board_struct { 943 const char *name; 944 const char *alt_route_name; 945 int device_id; 946 int isapnp_id; 947 948 int n_adchan; 949 unsigned int ai_maxdata; 950 951 int ai_fifo_depth; 952 unsigned int alwaysdither:1; 953 int gainlkup; 954 int ai_speed; 955 956 int n_aochan; 957 unsigned int ao_maxdata; 958 int ao_fifo_depth; 959 const struct comedi_lrange *ao_range_table; 960 unsigned int ao_speed; 961 962 int reg_type; 963 unsigned int has_8255:1; 964 unsigned int has_32dio_chan:1; 965 unsigned int dio_speed; /* not for e-series */ 966 967 enum caldac_enum caldac[3]; 968}; 969 970#define MAX_N_CALDACS 34 971#define MAX_N_AO_CHAN 8 972#define NUM_GPCT 2 973 974#define NUM_PFI_OUTPUT_SELECT_REGS 6 975#define NUM_RTSI_SHARED_MUXS (NI_RTSI_BRD(-1) - NI_RTSI_BRD(0) + 1) 976 977#define M_SERIES_EEPROM_SIZE 1024 978 979struct ni_private { 980 unsigned short dio_output; 981 unsigned short dio_control; 982 int aimode; 983 unsigned int ai_calib_source; 984 unsigned int ai_calib_source_enabled; 985 /* protects access to windowed registers */ 986 spinlock_t window_lock; 987 /* protects interrupt/dma register access */ 988 spinlock_t soft_reg_copy_lock; 989 /* protects mite DMA channel request/release */ 990 spinlock_t mite_channel_lock; 991 992 int changain_state; 993 unsigned int changain_spec; 994 995 unsigned int caldac_maxdata_list[MAX_N_CALDACS]; 996 unsigned short caldacs[MAX_N_CALDACS]; 997 998 unsigned short ai_cmd2; 999 1000 unsigned short ao_conf[MAX_N_AO_CHAN]; 1001 unsigned short ao_mode1; 1002 unsigned short ao_mode2; 1003 unsigned short ao_mode3; 1004 unsigned short ao_cmd1; 1005 unsigned short ao_cmd2; 1006 1007 struct ni_gpct_device *counter_dev; 1008 unsigned short an_trig_etc_reg; 1009 1010 unsigned int ai_offset[512]; 1011 1012 unsigned long serial_interval_ns; 1013 unsigned char serial_hw_mode; 1014 unsigned short clock_and_fout; 1015 unsigned short clock_and_fout2; 1016 1017 unsigned short int_a_enable_reg; 1018 unsigned short int_b_enable_reg; 1019 unsigned short io_bidirection_pin_reg; 1020 unsigned short rtsi_trig_direction_reg; 1021 unsigned short rtsi_trig_a_output_reg; 1022 unsigned short rtsi_trig_b_output_reg; 1023 unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; 1024 unsigned short ai_ao_select_reg; 1025 unsigned short g0_g1_select_reg; 1026 unsigned short cdio_dma_select_reg; 1027 1028 unsigned int clock_ns; 1029 unsigned int clock_source; 1030 1031 unsigned short pwm_up_count; 1032 unsigned short pwm_down_count; 1033 1034 unsigned short ai_fifo_buffer[0x2000]; 1035 u8 eeprom_buffer[M_SERIES_EEPROM_SIZE]; 1036 1037 struct mite *mite; 1038 struct mite_channel *ai_mite_chan; 1039 struct mite_channel *ao_mite_chan; 1040 struct mite_channel *cdo_mite_chan; 1041 struct mite_ring *ai_mite_ring; 1042 struct mite_ring *ao_mite_ring; 1043 struct mite_ring *cdo_mite_ring; 1044 struct mite_ring *gpct_mite_ring[NUM_GPCT]; 1045 1046 /* ni_pcimio board type flags (based on the boardinfo reg_type) */ 1047 unsigned int is_m_series:1; 1048 unsigned int is_6xxx:1; 1049 unsigned int is_611x:1; 1050 unsigned int is_6143:1; 1051 unsigned int is_622x:1; 1052 unsigned int is_625x:1; 1053 unsigned int is_628x:1; 1054 unsigned int is_67xx:1; 1055 unsigned int is_6711:1; 1056 unsigned int is_6713:1; 1057 1058 /* 1059 * Boolean value of whether device needs to be armed. 1060 * 1061 * Currently, only NI AO devices are known to be needing arming, since 1062 * the DAC registers must be preloaded before triggering. 1063 * This variable should only be set true during a command operation 1064 * (e.g ni_ao_cmd) and should then be set false by the arming 1065 * function (e.g. ni_ao_arm). 1066 * 1067 * This variable helps to ensure that multiple DMA allocations are not 1068 * possible. 1069 */ 1070 unsigned int ao_needs_arming:1; 1071 1072 /* device signal route tables */ 1073 struct ni_route_tables routing_tables; 1074 1075 /* 1076 * Number of clients (RTSI lines) for current RTSI MUX source. 1077 * 1078 * This allows resource management of RTSI board/shared mux lines by 1079 * marking the RTSI line that is using a particular MUX. Currently, 1080 * these lines are only automatically allocated based on source of the 1081 * route requested. Furthermore, the only way that this auto-allocation 1082 * and configuration works is via the globally-named ni signal/terminal 1083 * names. 1084 */ 1085 u8 rtsi_shared_mux_usage[NUM_RTSI_SHARED_MUXS]; 1086 1087 /* 1088 * softcopy register for rtsi shared mux/board lines. 1089 * For e-series, the bit layout of this register is 1090 * (docs: mhddk/nieseries/ChipObjects/tSTC.{h,ipp}, 1091 * DAQ-STC, Jan 1999, 340934B-01): 1092 * bits 0:2 -- NI_RTSI_BRD(0) source selection 1093 * bits 3:5 -- NI_RTSI_BRD(1) source selection 1094 * bits 6:8 -- NI_RTSI_BRD(2) source selection 1095 * bits 9:11 -- NI_RTSI_BRD(3) source selection 1096 * bit 12 -- NI_RTSI_BRD(0) direction, 0:input, 1:output 1097 * bit 13 -- NI_RTSI_BRD(1) direction, 0:input, 1:output 1098 * bit 14 -- NI_RTSI_BRD(2) direction, 0:input, 1:output 1099 * bit 15 -- NI_RTSI_BRD(3) direction, 0:input, 1:output 1100 * According to DAQ-STC: 1101 * RTSI Board Interface--Configured as an input, each bidirectional 1102 * RTSI_BRD pin can drive any of the seven RTSI_TRIGGER pins. 1103 * RTSI_BRD<0..1> can also be driven by AI STOP and RTSI_BRD<2..3> 1104 * can also be driven by the AI START and SCAN_IN_PROG signals. 1105 * These pins provide a mechanism for additional board-level signals 1106 * to be sent on or received from the RTSI bus. 1107 * Couple of comments: 1108 * - Neither the DAQ-STC nor the MHDDK is clear on what the direction 1109 * of the RTSI_BRD pins actually means. There does not appear to be 1110 * any clear indication on what "output" would mean, since the point 1111 * of the RTSI_BRD lines is to always drive one of the 1112 * RTSI_TRIGGER<0..6> lines. 1113 * - The DAQ-STC also indicates that the NI_RTSI_BRD lines can be 1114 * driven by any of the RTSI_TRIGGER<0..6> lines. 1115 * But, looking at valid device routes, as visually imported from 1116 * NI-MAX, there appears to be only one family (so far) that has the 1117 * ability to route a signal from one TRIGGER_LINE to another 1118 * TRIGGER_LINE: the 653x family of DIO devices. 1119 * 1120 * For m-series, the bit layout of this register is 1121 * (docs: mhddk/nimseries/ChipObjects/tMSeries.{h,ipp}): 1122 * bits 0:3 -- NI_RTSI_BRD(0) source selection 1123 * bits 4:7 -- NI_RTSI_BRD(1) source selection 1124 * bits 8:11 -- NI_RTSI_BRD(2) source selection 1125 * bits 12:15 -- NI_RTSI_BRD(3) source selection 1126 * Note: The m-series does not have any option to change direction of 1127 * NI_RTSI_BRD muxes. Furthermore, there are no register values that 1128 * indicate the ability to have TRIGGER_LINES driving the output of 1129 * the NI_RTSI_BRD muxes. 1130 */ 1131 u16 rtsi_shared_mux_reg; 1132 1133 /* 1134 * Number of clients (RTSI lines) for current RGOUT0 path. 1135 * Stored in part of in RTSI_TRIG_DIR or RTSI_TRIGB registers 1136 */ 1137 u8 rgout0_usage; 1138}; 1139 1140static const struct comedi_lrange range_ni_E_ao_ext; 1141 1142#endif /* _COMEDI_NI_STC_H */ 1143