Searched refs:reg_mask (Results 1 - 25 of 42) sorted by path

12

/linux-master/drivers/video/fbdev/via/
H A Dhw.c968 int reg_mask; local
977 reg_mask = 0;
986 reg_mask = reg_mask | (BIT0 << j);
993 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
995 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
/linux-master/include/sound/
H A Dpcm_oss.h72 unsigned int reg_mask; member in struct:snd_pcm_oss
/linux-master/drivers/clk/samsung/
H A Dclk-pll.c80 unsigned int reg_mask)
99 if (readl_relaxed(pll->con_reg) & reg_mask)
107 val & reg_mask, 0, PLL_TIMEOUT_US);
79 samsung_pll_lock_wait(struct samsung_clk_pll *pll, unsigned int reg_mask) argument
/linux-master/drivers/clk/ux500/
H A Dclk-sysctrl.c27 u8 reg_mask[SYSCTRL_MAX_NUM_PARENTS]; member in struct:clk_sysctrl
40 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0],
53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0]))
73 clk->reg_mask[old_index]);
80 clk->reg_mask[index],
85 clk->reg_mask[old_index],
123 u8 *reg_mask,
150 clk->reg_mask[0] = reg_mask[0];
156 clk->reg_mask[
118 clk_reg_sysctrl(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u16 *reg_sel, u8 *reg_mask, u8 *reg_bits, unsigned long rate, unsigned long enable_delay_us, unsigned long flags, const struct clk_ops *clk_sysctrl_ops) argument
178 clk_reg_sysctrl_gate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, u8 reg_mask, u8 reg_bits, unsigned long enable_delay_us, unsigned long flags) argument
195 clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, u8 reg_mask, u8 reg_bits, unsigned long rate, unsigned long enable_delay_us, unsigned long flags) argument
214 clk_reg_sysctrl_set_parent(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u16 *reg_sel, u8 *reg_mask, u8 *reg_bits, unsigned long flags) argument
[all...]
H A Dclk.h72 u8 reg_mask,
81 u8 reg_mask,
92 u8 *reg_mask,
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dqat_hal.c1378 unsigned short reg_mask; local
1396 reg_mask = (unsigned short)~0x1f;
1398 reg_mask = (unsigned short)~0xf;
1400 if (reg_num & reg_mask)
/linux-master/drivers/gpio/
H A Dgpio-htc-egpio.c38 int reg_mask; member in struct:egpio_info
192 reg, (egpio->cached_values >> shift) & ei->reg_mask);
199 egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
245 if (!((egpio->is_out >> shift) & ei->reg_mask))
249 (egpio->cached_values >> shift) & ei->reg_mask,
253 & ei->reg_mask, ei, reg);
301 ei->reg_mask = (1 << pdata->reg_width) - 1;
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvi.c1060 u32 reg_mask; local
1066 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
1071 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
1090 tmp &= ~reg_mask;
/linux-master/drivers/gpu/drm/imagination/
H A Dpvr_device.h564 * @reg_mask: Mask of bits valid for comparison with @reg_value.
573 u32 reg_mask, u64 timeout_usec)
578 (value & reg_mask) == reg_value, 0, timeout_usec);
587 * @reg_mask: Mask of bits valid for comparison with @reg_value.
596 u64 reg_mask, u64 timeout_usec)
601 (value & reg_mask) == reg_value, 0, timeout_usec);
572 pvr_cr_poll_reg32(struct pvr_device *pvr_dev, u32 reg_addr, u32 reg_value, u32 reg_mask, u64 timeout_usec) argument
595 pvr_cr_poll_reg64(struct pvr_device *pvr_dev, u32 reg_addr, u64 reg_value, u64 reg_mask, u64 timeout_usec) argument
/linux-master/drivers/irqchip/
H A Dirq-mmp.c43 void __iomem *reg_mask; member in struct:icu_chip_data
86 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
87 writel_relaxed(r, data->reg_mask);
115 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
116 writel_relaxed(r, data->reg_mask);
134 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
135 writel_relaxed(r, data->reg_mask);
169 mask = readl_relaxed(data->reg_mask);
388 icu_data[i].reg_mask = mmp_icu_base + reg[2];
/linux-master/drivers/media/i2c/
H A Dmt9m111.c142 #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ macro
225 unsigned int reg_mask; member in struct:mt9m111_mode_info
258 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
267 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
277 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
939 mt9m111->current_mode->reg_mask);
/linux-master/drivers/memory/
H A Dstm32-fmc2-ebi.c215 * @reg_mask: the bit that have to be modified in the selected register
231 u32 reg_mask; member in struct:stm32_fmc2_prop
505 regmap_update_bits(ebi->regmap, reg, prop->reg_mask,
506 setup ? prop->reg_mask : 0);
934 .reg_mask = FMC2_BCR1_CCLKEN,
942 .reg_mask = FMC2_BCR_MUXEN,
955 .reg_mask = FMC2_BCR_WAITPOL,
962 .reg_mask = FMC2_BCR_WAITCFG,
970 .reg_mask = FMC2_BCR_WAITEN,
978 .reg_mask
[all...]
/linux-master/drivers/net/dsa/microchip/
H A Dksz_common.c2132 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
2237 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2251 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
H A Dksz_common.h88 u16 reg_mask; member in struct:ksz_irq
H A Dksz_ptp.c1058 ret = ksz_write16(dev, kirq->reg_mask, kirq->masked);
1135 ptpirq->reg_mask = ops->get_port_addr(p, REG_PTP_PORT_TX_INT_ENABLE__2);
/linux-master/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_init.h569 } reg_mask; /* Register mask (all valid bits) */ member in struct:__anon303
695 return bnx2x_blocks_parity_data[idx].reg_mask.e1;
697 return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
699 return bnx2x_blocks_parity_data[idx].reg_mask.e2;
701 return bnx2x_blocks_parity_data[idx].reg_mask.e3;
741 u32 reg_mask = bnx2x_parity_reg_mask(bp, i); local
743 if (reg_mask) {
746 if (reg_val & reg_mask)
750 reg_val & reg_mask);
774 u32 reg_mask local
[all...]
/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Dcommon.h582 unsigned int reg_mask; /* MII reg mask */ member in struct:mii_regs
617 u32 reg_mask; member in struct:stmmac_rx_routing
H A Ddwmac-sun8i.c1113 mac->mii.reg_mask = GENMASK(8, 4);
H A Ddwmac1000_core.c554 mac->mii.reg_mask = 0x000007C0;
H A Ddwmac100_core.c190 mac->mii.reg_mask = 0x000007C0;
H A Ddwmac4_core.c172 value &= ~route_possibilities[packet - 1].reg_mask;
174 route_possibilities[packet - 1].reg_mask;
1397 mac->mii.reg_mask = GENMASK(20, 16);
H A Ddwxgmac2_core.c171 value &= ~dwxgmac2_route_possibilities[packet - 1].reg_mask;
173 dwxgmac2_route_possibilities[packet - 1].reg_mask;
1672 mac->mii.reg_mask = GENMASK(15, 0);
1714 mac->mii.reg_mask = GENMASK(15, 0);
H A Dstmmac_mdio.c288 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
328 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
333 value &= ~priv->hw->mii.reg_mask;
334 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
387 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
428 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
435 value &= ~priv->hw->mii.reg_mask;
436 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
/linux-master/drivers/net/ethernet/ti/
H A Dcpsw_ale.c745 int untag_mask, int reg_mask, int unreg_mask)
768 reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask;
744 cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, int untag_mask, int reg_mask, int unreg_mask) argument
/linux-master/drivers/net/phy/
H A Dnxp-tja11xx.c291 u16 reg_mask, reg_val; local
304 reg_mask = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
309 reg_mask |= MII_CFG1_INTERFACE_MODE_MASK;
315 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
320 reg_mask = MII_CFG1_INTERFACE_MODE_MASK;
326 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);

Completed in 311 milliseconds

12