Searched refs:pipeline (Results 1 - 25 of 73) sorted by path

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/linux-master/arch/m68k/fpsp040/
H A Dsetox.S135 | c) To fully utilize the pipeline, p is separated into
255 | c) To fully utilize the pipeline, p is separated into
314 | d) To fully utilize the pipeline, Q is separated into
/linux-master/arch/m68k/ifpsp060/src/
H A Dfplsp.S6793 # c) To fully utilize the pipeline, p is separated into #
6921 # c) To fully utilize the pipeline, p is separated into #
6984 # d) To fully utilize the pipeline, Q is separated into #
8018 # Note 3. To fully exploit the pipeline, polynomials are usually #
H A Dfpsp.S6899 # c) To fully utilize the pipeline, p is separated into #
7027 # c) To fully utilize the pipeline, p is separated into #
7090 # d) To fully utilize the pipeline, Q is separated into #
8124 # Note 3. To fully exploit the pipeline, polynomials are usually #
/linux-master/arch/sparc/lib/
H A DM7memset.S64 * instruction in the pipeline. That avoids various pipeline delays,
188 ! get store pipeline moving
223 ! to keep the store pipeline moving.
/linux-master/drivers/gpu/drm/xen/
H A Dxen_drm_front_kms.h23 void xen_drm_front_kms_on_frame_done(struct xen_drm_front_drm_pipeline *pipeline,
/linux-master/drivers/isdn/mISDN/
H A Ddsp_dtmf.c83 /* check if pipeline exists */
84 if (dsp->pipeline.inuse) {
87 "because pipeline exists.\n",
/linux-master/drivers/net/wireless/ti/wl18xx/
H A Dacx.h277 struct wl18xx_acx_pipeline_stats pipeline; member in struct:wl18xx_acx_statistics
/linux-master/arch/arm/boot/compressed/
H A Dhead.S932 sub pc, lr, r0, lsr #32 @ properly flush pipeline
/linux-master/arch/arm/crypto/
H A Dsha1-armv4-large.S55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
/linux-master/arch/arm/mm/
H A Dproc-xsc3.S58 @ flush instruction pipeline
116 @ CAUTION: MMU turned off from this point. We count on the pipeline
H A Dproc-xscale.S71 sub pc, pc, #4 @ flush instruction pipeline
77 @ flush instruction pipeline
152 sub pc, pc, #4 @ flush pipeline
158 @ CAUTION: MMU turned off from this point. We count on the pipeline
/linux-master/arch/x86/platform/olpc/
H A Dxo1-wakeup.S35 # Control registers were modified, pipeline resync is needed
/linux-master/drivers/gpu/drm/arm/display/komeda/d71/
H A Dd71_component.c1049 struct d71_pipeline *pipe = to_d71_pipeline(c->pipeline);
1200 if (c->pipeline->dual_link) {
/linux-master/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_crtc.c69 * pipeline according to the crtc_state, but still needs to release or disable
70 * the unclaimed pipeline resources.
94 /* release unclaimed pipeline resources */
261 /* step 1: update the pipeline/component state to HW */
406 /* Once dual-link one display pipeline drives two display outputs,
606 if (kplane->layer->base.pipeline == crtc->master)
631 /* Construct an encoder for each pipeline and attach it to the remote
H A Dkomeda_pipeline.c14 /** komeda_pipeline_add - Add a pipeline to &komeda_dev */
28 DRM_ERROR("Request pipeline size too small.\n");
118 DRM_ERROR("Unknown pipeline resource ID: %d.\n", id);
158 return komeda_pipeline_get_first_component(c->pipeline, avail_inputs);
207 c->pipeline = pipe;
274 struct komeda_pipeline *pipe = c->pipeline;
341 return slave ? slave->pipeline : NULL;
H A Dkomeda_pipeline.h21 /* pipeline component IDs */
76 * component into the display pipeline.
82 /** @pipeline: the komeda pipeline this component belongs to */
83 struct komeda_pipeline *pipeline; member in struct:komeda_component
119 * pipeline.
385 * Represent a complete display pipeline and hold all functional components.
388 /** @obj: link pipeline as private obj of drm_atomic_state */
394 /** @id: pipeline id */
396 /** @avail_comps: available components mask of pipeline */
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H A Dkomeda_pipeline_state.c60 /* Assign pipeline for crtc */
73 DRM_DEBUG_ATOMIC("CRTC%d required pipeline%d is busy.\n",
78 /* pipeline only can be disabled when the it is free or unused */
80 DRM_DEBUG_ATOMIC("Disabling a busy pipeline:%d.\n", pipe->id);
104 WARN_ON(!drm_modeset_is_locked(&c->pipeline->obj.lock));
140 * The big boss (CRTC) is for pipeline assignment, since &komeda_component isn't
142 * pipeline, only pipeline can be shared between crtc, and pipeline as a whole
146 * component->pipeline t
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H A Dkomeda_plane.c23 struct komeda_pipeline *pipe = kplane->layer->base.pipeline;
197 /* for komeda, which is pipeline can be share between crtcs */
265 get_possible_crtcs(kms, c->pipeline),
311 komeda_set_crtc_plane_mask(kms, c->pipeline, plane);
H A Dkomeda_wb_connector.c26 dflow->input.component = &wb_layer->base.pipeline->compiz->base;
/linux-master/drivers/gpu/drm/ci/
H A Dlava-submit.sh38 --pipeline-info "$CI_JOB_NAME: $CI_PIPELINE_URL on $CI_COMMIT_REF_NAME ${CI_NODE_INDEX}/${CI_NODE_TOTAL}" \
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dcmd_parser.c314 #define OP_MFX(pipeline, op, sub_opa, sub_opb) \
316 (pipeline) << 11 | \
368 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
370 (pipeline) << 11 | \
/linux-master/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cmd_encoder.c129 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); local
136 mdp5_ctl_set_encoder_state(ctl, pipeline, false);
137 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
147 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); local
155 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
157 mdp5_ctl_set_encoder_state(ctl, pipeline, true);
H A Dmdp5_crtc.c95 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; local
102 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start);
127 mixer = mdp5_cstate->pipeline.mixer;
130 r_mixer = mdp5_cstate->pipeline.r_mixer;
141 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; local
159 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0);
215 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; local
588 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; local
954 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; local
1086 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; local
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H A Dmdp5_ctl.c135 static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) argument
138 struct mdp5_interface *intf = pipeline->intf;
159 if (pipeline->r_mixer)
168 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) argument
171 struct mdp5_interface *intf = pipeline->intf;
177 set_ctl_op(ctl, pipeline);
183 struct mdp5_pipeline *pipeline)
185 struct mdp5_interface *intf = pipeline->intf;
203 * For a given control operation (display pipeline), a START signal needs to be
220 * @pipeline
182 start_signal_needed(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) argument
226 mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, bool enabled) argument
250 mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, int cursor_id, bool enable) argument
349 mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, enum mdp5_pipe stage[][MAX_PIPE_STAGE], enum mdp5_pipe r_stage[][MAX_PIPE_STAGE], u32 stage_cnt, u32 ctl_blend_op_flags) argument
472 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, u32 flush_mask) argument
535 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, u32 flush_mask, bool start) argument
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H A Dmdp5_ctl.h36 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
54 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
71 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,

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