Lines Matching refs:pipeline
135 static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
138 struct mdp5_interface *intf = pipeline->intf;
159 if (pipeline->r_mixer)
168 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
171 struct mdp5_interface *intf = pipeline->intf;
177 set_ctl_op(ctl, pipeline);
183 struct mdp5_pipeline *pipeline)
185 struct mdp5_interface *intf = pipeline->intf;
203 * For a given control operation (display pipeline), a START signal needs to be
220 * @pipeline: the encoder's INTF + MIXER configuration
227 struct mdp5_pipeline *pipeline,
230 struct mdp5_interface *intf = pipeline->intf;
238 if (start_signal_needed(ctl, pipeline)) {
250 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
256 struct mdp5_hw_mixer *mixer = pipeline->mixer;
264 if (pipeline->r_mixer) {
349 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
354 struct mdp5_hw_mixer *mixer = pipeline->mixer;
355 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
472 static u32 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
482 sw_mask |= mdp_ctl_flush_mask_lm(pipeline->mixer->lm);
516 * @pipeline: the encoder's INTF + MIXER configuration
536 struct mdp5_pipeline *pipeline,
551 flush_mask |= fix_sw_flush(ctl, pipeline, flush_mask);
573 if (start_signal_needed(ctl, pipeline)) {