Searched refs:instruction (Results 1 - 25 of 123) sorted by last modified time

12345

/linux-master/arch/x86/kvm/
H A Dx86.c507 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
511 * fault we just panic; during reboot instead the instruction is ignored.
725 that instruction re-execution will regenerate lost
2111 /* Treat an INVD instruction as a NOP and just skip it. */
2130 pr_warn_once("%s instruction emulated as NOP!\n", insn);
5074 * an instruction boundary and will not trigger guest emulation of any
5178 * instruction boundary and with no events half-injected.
5389 * The API doesn't provide the instruction length for software
7599 /* used for instruction fetching */
8620 * instruction
10162 char instruction[3]; local
[all...]
/linux-master/arch/s390/kernel/
H A Dentry.S81 * The TSTMSK macro generates a test-under-mask instruction by
85 * instruction.
206 # Let the next instruction be NOP to avoid triggering a machine check
207 # and handling it in a guest as result of the instruction execution.
/linux-master/arch/mips/kernel/
H A Dscall64-o32.S38 daddiu t1, 4 # skip to next instruction
H A Dscall64-n64.S43 daddiu t1, 4 # skip to next instruction
H A Dscall64-n32.S40 daddiu t1, 4 # skip to next instruction
H A Dscall32-o32.S34 addiu t1, 4 # skip to next instruction
/linux-master/tools/objtool/
H A Dcheck.c27 struct instruction *insn;
38 struct instruction *find_insn(struct objtool_file *file,
41 struct instruction *insn;
51 struct instruction *next_insn_same_sec(struct objtool_file *file,
52 struct instruction *insn)
64 static struct instruction *next_insn_same_func(struct objtool_file *file,
65 struct instruction *insn)
67 struct instruction *next = next_insn_same_sec(file, insn);
84 static struct instruction *prev_insn_same_sec(struct objtool_file *file,
85 struct instruction *ins
[all...]
H A Dorc_gen.c62 struct instruction *insn;
/linux-master/drivers/acpi/apei/
H A Deinj-core.c243 entry->instruction == ACPI_EINJ_WRITE_REGISTER &&
248 entry->instruction == ACPI_EINJ_WRITE_REGISTER &&
306 entry->instruction <= ACPI_EINJ_WRITE_REGISTER_VALUE &&
/linux-master/tools/objtool/include/objtool/
H A Dorc.h7 int init_orc_entry(struct orc_entry *orc, struct cfi_state *cfi, struct instruction *insn);
/linux-master/tools/objtool/arch/x86/
H A Dorc.c10 int init_orc_entry(struct orc_entry *orc, struct cfi_state *cfi, struct instruction *insn)
19 * trigger unreachable instruction warnings), or
H A Dspecial.c42 struct instruction *insn,
66 * In such a case we can just crudely ignore all unreachable instruction
69 * bit. And honestly that's just not worth doing: unreachable instruction
83 * TODO: Once we have DWARF CFI and smarter instruction decoding logic,
89 struct instruction *insn)
124 * instruction.
H A Ddecode.c76 unsigned long arch_jump_destination(struct instruction *insn)
149 struct instruction *insn)
170 WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
556 WARN("ENQCMD instruction at %s:%lx", sec->name,
/linux-master/tools/objtool/arch/loongarch/
H A Dorc.c10 int init_orc_entry(struct orc_entry *orc, struct cfi_state *cfi, struct instruction *insn)
20 * trigger unreachable instruction warnings), or
H A Dspecial.c5 struct instruction *insn,
12 struct instruction *insn)
H A Ddecode.c18 unsigned long arch_jump_destination(struct instruction *insn)
79 struct instruction *insn)
100 struct instruction *insn)
118 struct instruction *insn,
177 struct instruction *insn,
221 struct instruction *insn)
238 * just treat it as a call instruction.
277 struct instruction *insn)
/linux-master/arch/arm/kernel/
H A Dtraps.c49 "undefined instruction",
97 void dump_backtrace_stm(u32 *stack, u32 instruction, const char *loglvl) argument
104 if (instruction & BIT(reg)) {
493 pr_info("%s (%d): undefined instruction: pc=%px\n",
499 arm_notify_die("Oops - undefined instruction", regs,
730 * A data abort trap was taken, but we did not handle the instruction.
801 * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8
872 * Poison the vectors page with an undefined instruction. This
873 * instruction is chosen to be undefined for both ARM and Thumb
874 * ISAs. The Thumb version is an undefined instruction wit
[all...]
/linux-master/include/linux/mlx5/
H A Dmlx5_ifc.h10897 u8 instruction[0x8]; member in struct:mlx5_ifc_mcc_reg_bits
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx10.asm231 // Caused by instruction fetch memory violation.
334 // Advance past trap instruction to prevent re-entry.
H A Dcwsr_trap_handler_gfx9.asm221 // Caused by instruction fetch memory violation.
232 // and debugger (host trap, wave start/end, trap after instruction)
324 // Advance past trap instruction to prevent re-entry.
361 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for.
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/
H A Dfw.c408 MLX5_SET(mcc_reg, in, instruction, instr);
/linux-master/arch/x86/kernel/
H A Dhead_32.S257 movl $1,%eax # Use the CPUID instruction to get CPU type
/linux-master/tools/perf/util/
H A Dheader.c2090 fprintf(fp, "# contains AUX area data (e.g. instruction trace)\n");
/linux-master/tools/testing/selftests/sgx/
H A Dtest_encl_bootstrap.S67 # Prepare EEXIT target by popping the address of the instruction after
/linux-master/drivers/net/ethernet/mellanox/mlxsw/
H A Dreg.h10536 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
10552 * Indicates the successful completion of the instruction, or the reason it
10565 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
11911 * IP (instruction pointer) that triggered the timeout.
11940 * The instruction pointer when assert was triggered.

Completed in 548 milliseconds

12345