/linux-master/arch/sh/kernel/cpu/sh2a/ |
H A D | probe.c | 43 boot_cpu_data.dcache.ways = 4; 44 boot_cpu_data.dcache.way_incr = (1 << 11); 45 boot_cpu_data.dcache.sets = 128; 46 boot_cpu_data.dcache.entry_shift = 4; 47 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; 48 boot_cpu_data.dcache.flags = 0; 51 * The icache is the same as the dcache as far as this setup is 53 * lacks the U bit that the dcache has, none of this has any bearing 56 boot_cpu_data.icache = boot_cpu_data.dcache;
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/linux-master/arch/sh/kernel/cpu/sh3/ |
H A D | probe.c | 50 boot_cpu_data.dcache.ways = 4; 51 boot_cpu_data.dcache.entry_shift = 4; 52 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; 53 boot_cpu_data.dcache.flags = 0; 60 boot_cpu_data.dcache.way_incr = (1 << 11); 61 boot_cpu_data.dcache.entry_mask = 0x7f0; 62 boot_cpu_data.dcache.sets = 128; 67 boot_cpu_data.dcache.way_incr = (1 << 12); 68 boot_cpu_data.dcache.entry_mask = 0xff0; 69 boot_cpu_data.dcache [all...] |
/linux-master/arch/sh/kernel/cpu/sh4/ |
H A D | probe.c | 42 * And again for the dcache .. 44 boot_cpu_data.dcache.way_incr = (1 << 14); 45 boot_cpu_data.dcache.entry_shift = 5; 46 boot_cpu_data.dcache.sets = 512; 47 boot_cpu_data.dcache.ways = 1; 48 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; 68 boot_cpu_data.dcache.ways = 4; 172 boot_cpu_data.dcache.ways = 2; 177 boot_cpu_data.dcache.ways = 2; 193 boot_cpu_data.dcache [all...] |
/linux-master/arch/sh/mm/ |
H A D | cache-sh2a.c | 18 * The maximum number of pages we support up to when doing ranged dcache 19 * flushing. Anything exceeding this will simply flush the dcache in its 60 nr_ways = current_cpu_data.dcache.ways; 68 end = begin + (nr_ways * current_cpu_data.dcache.way_size); 107 int nr_ways = current_cpu_data.dcache.ways;
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H A D | cache-shx3.c | 27 if (boot_cpu_data.dcache.n_aliases || boot_cpu_data.icache.n_aliases) { 31 boot_cpu_data.dcache.n_aliases = 0;
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/linux-master/fs/hfs/ |
H A D | string.c | 17 #include <linux/dcache.h>
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/linux-master/fs/ocfs2/ |
H A D | Makefile | 16 dcache.o \
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/linux-master/fs/orangefs/ |
H A D | Makefile | 9 dcache.o inode.o orangefs-sysfs.o orangefs-mod.o super.o \
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/linux-master/fs/proc/ |
H A D | util.c | 1 #include <linux/dcache.h>
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/linux-master/fs/squashfs/ |
H A D | namei.c | 46 #include <linux/dcache.h>
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/linux-master/arch/arm/boot/compressed/ |
H A D | head.S | 845 mov r0, #4 @ put dcache in WT mode 1270 dcache_line_size r1, r2 @ r1 := dcache min line size 1299 mov r2, #64*1024 @ default: 32K dcache size (*2) 1307 mov r2, r2, lsl r1 @ base dcache size *2
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/linux-master/arch/mips/include/asm/ |
H A D | cpu-features.h | 252 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 258 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 508 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz
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H A D | cpu-info.h | 76 struct cache_desc dcache; /* Primary D or combined I/D cache */ member in struct:cpuinfo_mips
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H A D | debug.h | 9 #include <linux/dcache.h>
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H A D | r4kcache.h | 244 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) 247 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, ) 251 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, ) 254 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, ) 258 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, ) 259 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, ) 277 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 280 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 283 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 304 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_ [all...] |
/linux-master/arch/mips/include/asm/mach-cavium-octeon/ |
H A D | kernel-entry-init.h | 70 # Flush dcache after config change
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/linux-master/arch/mips/kernel/ |
H A D | cacheinfo.c | 30 if (c->dcache.waysize) 87 populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA); 92 populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
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H A D | pm-cps.c | 238 unsigned line_size = cpu_info->dcache.linesz; 457 * VPE within the core will interfere with the L1 dcache. 465 /* Writeback & invalidate the L1 dcache */ 466 cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache,
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H A D | traps.c | 647 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
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/linux-master/arch/mips/loongson64/ |
H A D | smp.c | 589 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); 651 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); 735 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets),
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/linux-master/arch/mips/mm/ |
H A D | c-octeon.c | 33 * Octeon automatically flushes the dcache on tlb changes, so 117 * dcache aliases don't need to do anything here 189 c->dcache.linesz = 128; 191 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ 193 c->dcache.sets = 1; /* CN3XXX has one Dcache set */ 194 c->dcache.ways = 64; 196 c->dcache.sets * c->dcache.ways * c->dcache.linesz; 197 c->dcache [all...] |
H A D | c-r4k.c | 479 * If dcache can alias, we must blast it since mapping is changing. 1014 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1015 c->dcache.ways = 2; 1016 c->dcache.waybit= __ffs(dcache_size/2); 1028 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1029 c->dcache.ways = 2; 1030 c->dcache.waybit = 0; 1042 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1043 c->dcache.ways = 4; 1044 c->dcache [all...] |
/linux-master/arch/powerpc/kernel/ |
H A D | cacheinfo.c | 372 struct cache *dcache, *icache; local 374 pr_debug("creating L%d dcache and icache for %pOFP\n", level, 377 dcache = new_cache(CACHE_TYPE_DATA, level, node, group_id); 380 if (!dcache || !icache) 383 dcache->next_local = icache; 385 return dcache; 387 release_cache(dcache);
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/linux-master/arch/powerpc/perf/ |
H A D | generic-compat-pmu.c | 109 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 110 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
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H A D | power10-pmu.c | 133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 135 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS); 136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
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