sh: sh4: convert to SPDX identifiers

Update license to use SPDX-License-Identifier instead of verbose license
text, excepting ${LINUX}/arch/sh/kernel/cpu/sh4/softfloat.c which is not
GPL license

Link: http://lkml.kernel.org/r/87a7lkcsya.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Cc: Rich Felker <dalias@libc.org>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

sh: delete __cpuinit usage from all sh files

The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.

This removes all the arch/sh uses of the __cpuinit macros from
all C files. Currently sh does not have any __CPUINIT used in
assembly files.

[1] https://lkml.org/lkml/2013/5/20/589

Cc: Paul Mundt <lethal@linux-sh.org>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

sh: Add initial support for SH7734 CPU subtype

This implements initial support for the SH7734.
This adds support SCIF, TMU and RTC.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: sh7372 SH4AL-DSP probe support

Add probe support for the sh7372 SH4AL-DSP core.

The most common use case for this is when the system
boots from the ARM core in the sh7372 and uses the
SH core for application offload as a slave CPU.

May also be used to boot the sh7372 from the SH core.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: add PVR probing for SH7757 3rd cut

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: change PVR of SH7757 for 2nd cut

All 1st cut silicon in the wild has been replaced by the 2nd cut, so it's
safe to replace all of the 1st cut references and support.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Tidy CPU probing and fixup section annotations.

This does a detect_cpu_and_cache_system() -> cpu_probe() rename, tidies
up the unused return value, and stuffs it under __cpuinit in preparation
for CPU hotplug.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Mass ctrl_in/outX to __raw_read/writeX conversion.

The old ctrl in/out routines are non-portable and unsuitable for
cross-platform use. While drivers/sh has already been sanitized, there
is still quite a lot of code that is not. This converts the arch/sh/ bits
over, which permits us to flag the routines as deprecated whilst still
building with -Werror for the architecture code, and to ensure that
future users are not added.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Handle SH-4 FPU variants with broken CVR values.

Usually we can look to the CVR to work out whether we have an FPU or not.
Unfortunately not all parts comply with this, so just set the flag
manually for all SH-4 parts and clear it on the only SH-4 that doesn't
have one (SH4-501).

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Fix up L2 cache comment typo.

Valid sizes include 256kB, not 258kB.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: PVR detection for 2nd cut SH7786.

The mass produced cuts use an updated PVR value, add them to the list.

Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: fix CPU_SH7723/7724 numbering bug

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Add initial support for SH7757 CPU subtype

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Kill off the unhandled pvr case in SH-4 CPU probing.

This is superfluous, as the default CPU type and family are already
established by the initial cpuinfo definition. Given that we are still
able to probe for the CPU family even if we are not able to detect the
subtype, it's preferable to let the probing code fill out what it can and
leave the rest.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Track the CPU family in sh_cpuinfo.

This adds a family member to struct sh_cpuinfo, which allows us to fall
back more on the probe routines to work out what sort of subtype we are
running on. This will be used by the CPU cache initialization code in
order to first do family-level initialization, followed by subtype-level
optimizations.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Tidy up SH-4A boot_cpu_data.flags probing.

This tidies up the boot_cpu_data.flags probing on SH-4A. All of them have
a few things in common, which we can blindly set, rather than having each
subtype have to set the same flags. We can also make assumptions about
cache ways and the validity of PTEA, so this also kills off CPU_HAS_PTEA
as a config option. There was also a bug in the FPU probing, which is now
tidied up.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Tidy up the optional L2 probing, wire it up for SH7786.

This tidies up the L2 probing, as it may or may not be implemented on a
CPU, regardless of whether it is supported. This converts the cvr
validity checks from BUG_ON()'s to simply clearing the CPU_HAS_L2_CACHE
flag and moving on with life.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: SH7724 has an L2 cache.

Add the CPU_HAS_L2_CACHE flag to SH7724.

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Add support for SH7724 (SH-Mobile R2R) CPU subtype.

This implements initial support for the SH-Mobile R2R CPU.
Based on Rev 0.11 of the initial SH7724 hardware manual.

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Kill off broken direct-mapped cache mode.

Forcing direct-mapped worked on certain older 2-way set associative
parts, but was always error prone on 4-way parts. As these are the
norm these days, there is not much point in continuing to support this
mode. Most of the folks that used direct-mapped mode generally just
wanted writethrough caching in the first place..

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.

This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
that implement the PTAEX register and respective functionality. Presently
only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).

The main change is in how the PTE is written out when loading the entry
in to the TLB, as well as in how the TLB entry is selectively flushed.

While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
arrays for extra bits, extended ASID mode splits out the address arrays.
While we don't use the memory-mapped data array access, the address
array accesses are necessary for selective TLB flushes, so these are
implemented newly and replace the generic SH-4 implementation.

With this, TLB flushes in switch_mm() are almost non-existent on newer
parts.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Add support for SH7786 CPU subtype.

This adds preliminary support for the SH7786 CPU subtype.

While this is a dual-core CPU, only UP is supported for now. L2 cache
support is likewise not yet implemented.

More information on this particular CPU subtype is available at:

http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Record the major cut revision for probed SH-4A parts.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Stub in silicon cut in CPU info.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: add probe support for new sh7723 cut

This patch adds support for sh7723 silicon with a prr value of 0x51.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Fix up L2 cache probe.

SH7723 is the first hard silicon to implement the L2, and unsurprisingly,
does the precise inverse of what the specification alleges. XOR the
URAM/L2 size bits to get back in line with the existing parsing logic.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Fix up SH-4A part probe.

The SH-4A series probe we were relying on doesn't work any more on the
newer parts, bump this up to use CVR.CHIP instead so we have consistent
behaviour across all of the parts, which is what this should have been
testing in the first place.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Add support for SH7723 CPU subtype.

This adds basic support for the SH7723 MobileR2 CPU.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: add support for sh7366 processor

This patch adds sh7366 cpu supports. Just the most basic things like interrupt
controller, clocks and serial port are included at this point.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: add probe support for new sh7722 cut

This patch adds support for sh7722 devices with prr value 0xa1.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Add support for SH7763 CPU subtype.

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Kill off the remaining ST40 cruft.

The ST40 stuff in-tree hasn't built for some time, and hasn't been
updated for over 3 years. ST maintains their own out-of-tree changes
and rebases occasionally, and that's ultimately where all of the ST40
users go anyways.

In order for the ST40 code to be brought up to date most of the stuff
removed in this changeset would have to be rewritten anyways, so there's
very little benefit in keeping the remnants around either.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Use boot_cpu_data for CPU probe.

This moves off of smp_processor_id() and only sets the probe
information for the boot CPU directly. This will be copied out
for the secondaries, so there's no reason to do this each time.

This also allows for some header tidying.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Disable L2 reporting for present URAM only parts.

The probing logic works for both URAM and L2, with no way to
distinguish between the two. Disable the probing for now and
let the CPU subtypes that have this in a real L2 configuration
explicitly say so.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: remove support for sh73180 and solution engine 73180

This patch removes old dead code:
- kill off sh73180 cpu support
- get rid of broken solution engine 73180 board support

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Preliminary support for the SH-X3 CPU.

This adds basic support for UP SH-X3.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: trivial build cleanups.

Several errors were spotted during building for custom config (SMP
included). Although SMP still does not compile (no ipi and
__smp_call_function) and does not work, this looks a bit cleaner.
Some other errors obtained via gcc-4.1.0 build.

Signed-off-by: Evgeniy Polyakov <johnpol@2ka.mipt.ru>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Add SH7785 Highlander board support (R7785RP).

This adds preliminary support for the SH7785-based Highlander board.
Some of the Highlander support code is reordered so that most of it
can be reused directly.

This also plugs in missing SH7785 checks in the places that need it,
as this is the first board to support the CPU.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Fix SH-3 cache entry_mask and way_size calculation.

The code for performing the calculation was only in the SH-4 probe
path, move it out to the common path so the other parts get this
right too.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Fixup cpu_data references for the non-boot CPUs.

There are a lot of bogus cpu_data-> references that only end up working
for the boot CPU, convert these to current_cpu_data to fixup SMP.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Lazy dcache writeback optimizations.

This converts the lazy dcache handling to the model described in
Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks
used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a
bonus, this slightly cuts down on the cache flushing frequency.

With that and the PTEA handling out of the way, the update_mmu_cache()
implementations can be consolidated, and we no longer have to worry
about which configuration the cache is in for the SH7705 case.

And finally, explicitly disable the lazy writeback on SMP (SH-4A).

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: SH-MobileR SH7722 CPU support.

This adds CPU support for the SH7722.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: TLB miss fast-path optimizations.

Handle simple TLB miss faults which can be resolved completely
from the page table in assembler.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: More intelligent entry_mask/way_size calculation.

Figure out the cache desc entry_mask at runtime, and remove
hard-coded assumption about the cacheline size.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Support for L2 cache on newer SH-4A CPUs.

This implements preliminary support for the L2 caches found
on newer SH-4A CPUs.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: CPU flags in AT_HWCAP in ELF auxvt.

Encode processor flags in AT_HWCAP in the ELF auxiliary vector.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Add support for SH7706/SH7710/SH7343 CPUs.

This adds support for the aforementioned CPU subtypes, and cleans
up some build issues encountered as a result.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Add flag for MMU PTEA capability.

Add CPU_HAS_PTEA, refactor some of the cpu flag settings.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Support for SH7770/SH7780 CPU subtypes.

Merge support for SH7770 and SH7780 SH-4A subtypes.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Refactor PRR masking to catch newer SH7760 cuts.

Newer SH7760 cuts have a range of acceptable PRR values..

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: Optimized cache handling for SH-4/SH-4A caches.

This reworks some of the SH-4 cache handling code to more easily
accomodate newer-style caches (particularly for the > direct-mapped
case), as well as optimizing some of the old code.

Signed-off-by: Richard Curnow <richard.curnow@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Linux-2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!