Searched refs:cur_state (Results 1 - 25 of 98) sorted by last modified time

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/linux-master/drivers/infiniband/sw/rxe/
H A Drxe_qp.c581 enum ib_qp_state cur_state; local
584 cur_state = (mask & IB_QP_CUR_STATE) ?
587 attr->qp_state : cur_state;
589 if (!ib_modify_qp_is_ok(cur_state, new_state, qp_type(qp), mask))
592 if (mask & IB_QP_STATE && cur_state == IB_QPS_SQD) {
/linux-master/drivers/infiniband/hw/mlx5/
H A Dqp.c4103 enum ib_qp_state cur_state,
4189 cur_state == IB_QPS_RESET &&
4298 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
4301 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4316 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
4322 mlx5_cur = to_mlx5_state(cur_state);
4340 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4451 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, argument
4459 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4462 } else if (cur_state
4101 __mlx5_ib_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, enum ib_qp_state cur_state, enum ib_qp_state new_state, const struct mlx5_ib_modify_qp *ucmd, struct mlx5_ib_modify_qp_resp *resp, struct ib_udata *udata) argument
4496 enum ib_qp_state cur_state, new_state; local
4661 enum ib_qp_state cur_state, new_state; local
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/linux-master/drivers/infiniband/hw/hns/
H A Dhns_roce_qp.c1393 enum ib_qp_state cur_state, new_state; local
1401 cur_state = hr_qp->state;
1402 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1418 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1428 if (cur_state == new_state && cur_state == IB_QPS_RESET)
1431 ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state,
H A Dhns_roce_hw_v2.c4993 static bool check_qp_state(enum ib_qp_state cur_state, argument
5015 return sm[cur_state][new_state];
5021 enum ib_qp_state cur_state,
5030 if (!check_qp_state(cur_state, new_state)) {
5035 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
5038 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
5040 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
5043 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
5244 int attr_mask, enum ib_qp_state cur_state,
5267 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5018 hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, enum ib_qp_state cur_state, enum ib_qp_state new_state, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask, struct ib_udata *udata) argument
5242 hns_roce_v2_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, enum ib_qp_state cur_state, enum ib_qp_state new_state, struct ib_udata *udata) argument
[all...]
H A Dhns_roce_device.h942 int attr_mask, enum ib_qp_state cur_state,
/linux-master/drivers/infiniband/hw/efa/
H A Defa_verbs.c877 static bool efa_modify_srd_qp_is_ok(enum ib_qp_state cur_state, argument
884 cur_state != IB_QPS_RTR && cur_state != IB_QPS_RTS &&
885 cur_state != IB_QPS_SQD && cur_state != IB_QPS_SQE)
888 if (!srd_qp_state_table[cur_state][next_state].valid)
891 req_param = srd_qp_state_table[cur_state][next_state].req_param;
892 opt_param = srd_qp_state_table[cur_state][next_state].opt_param;
905 enum ib_qp_state cur_state,
923 err = !efa_modify_srd_qp_is_ok(cur_state, new_stat
903 efa_modify_qp_validate(struct efa_dev *dev, struct efa_qp *qp, struct ib_qp_attr *qp_attr, int qp_attr_mask, enum ib_qp_state cur_state, enum ib_qp_state new_state) argument
953 enum ib_qp_state cur_state; local
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/linux-master/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_execbuf.c1628 SVGA3dTextureState *cur_state = (SVGA3dTextureState *) local
1642 for (; cur_state < last_state; ++cur_state) {
1643 if (likely(cur_state->name != SVGA3D_TS_BIND_TEXTURE))
1646 if (cur_state->stage >= SVGA3D_NUM_TEXTURE_UNITS) {
1648 (unsigned int) cur_state->stage);
1655 &cur_state->value, &res);
1670 binding.texture_stage = cur_state->stage;
/linux-master/drivers/video/fbdev/savage/
H A Dsavagefb_driver.c2413 int cur_state = par->pm_state; local
2423 if (cur_state == PM_EVENT_FREEZE)
/linux-master/drivers/gpu/drm/i915/display/
H A Dvlv_dsi_pll.c595 bool cur_state; local
598 cur_state = vlv_cck_read(i915, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN;
601 I915_STATE_WARN(i915, cur_state != state,
603 str_on_off(state), str_on_off(cur_state));
H A Dintel_dpll_mgr.c176 bool cur_state; local
183 cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state);
184 I915_STATE_WARN(i915, cur_state != state,
187 str_on_off(cur_state));
H A Dintel_dpll.c2313 bool cur_state; local
2315 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
2316 I915_STATE_WARN(dev_priv, cur_state != state,
2318 str_on_off(state), str_on_off(cur_state));
H A Dintel_display.c316 bool cur_state; local
328 cur_state = !!(val & TRANSCONF_ENABLE);
332 cur_state = false;
335 I915_STATE_WARN(dev_priv, cur_state != state,
338 str_on_off(cur_state));
345 bool cur_state; local
347 cur_state = plane->get_hw_state(plane, &pipe);
349 I915_STATE_WARN(i915, cur_state != state,
352 str_on_off(cur_state));
/linux-master/drivers/gpu/drm/
H A Ddrm_bridge.c900 struct drm_bridge_state *cur_state; local
906 cur_state = drm_atomic_get_new_bridge_state(crtc_state->state,
929 if (cur_state) {
930 cur_state->input_bus_cfg.format = MEDIA_BUS_FMT_FIXED;
931 cur_state->output_bus_cfg.format = out_bus_fmt;
941 if (WARN_ON(!cur_state))
945 cur_state,
956 cur_state->input_bus_cfg.format = in_bus_fmts[0];
957 cur_state->output_bus_cfg.format = out_bus_fmt;
971 cur_state
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/linux-master/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c2003 adev->vcn.cur_state = AMD_PG_STATE_GATE;
2004 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_baco.c76 enum BACO_STATE cur_state; local
79 vega20_baco_get_state(hwmgr, &cur_state);
81 if (cur_state == state)
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c268 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
1656 if (state == adev->vcn.cur_state)
1665 adev->vcn.cur_state = state;
H A Dvcn_v5_0_0.c1215 if (state == adev->vcn.cur_state)
1224 adev->vcn.cur_state = state;
H A Dvcn_v4_0_3.c274 if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
1544 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1548 if (state == adev->vcn.cur_state)
1557 adev->vcn.cur_state = state;
H A Dvcn_v3_0.c391 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
2133 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
2137 if (state == adev->vcn.cur_state)
2146 adev->vcn.cur_state = state;
H A Dvcn_v4_0.c319 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
2003 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
2007 if (state == adev->vcn.cur_state)
2016 adev->vcn.cur_state = state;
H A Dvcn_v2_5.c355 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
1792 if(state == adev->vcn.cur_state)
1801 adev->vcn.cur_state = state;
H A Dvcn_v2_0.c275 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
1771 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1775 if (state == adev->vcn.cur_state)
1784 adev->vcn.cur_state = state;
H A Dvcn_v1_0.c241 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
1775 if (state == adev->vcn.cur_state)
1784 adev->vcn.cur_state = state;
H A Djpeg_v4_0_5.c233 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
692 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE;
696 if (state == adev->jpeg.cur_state)
705 adev->jpeg.cur_state = state;
H A Djpeg_v5_0_0.c166 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
457 if (state == adev->jpeg.cur_state)
466 adev->jpeg.cur_state = state;

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