/linux-master/arch/arm/mach-omap2/ |
H A D | sram242x.S | 86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks 180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks 296 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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H A D | sram243x.S | 86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks 180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks 296 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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/linux-master/arch/arm64/boot/dts/sprd/ |
H A D | sharkl64.dtsi | 30 clocks = <&clk26mhz>; 38 clocks = <&clk26mhz>; 46 clocks = <&clk26mhz>; 54 clocks = <&clk26mhz>;
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/linux-master/include/trace/events/ |
H A D | fsi_master_gpio.h | 54 TP_PROTO(const struct fsi_master_gpio *master, int clocks), 55 TP_ARGS(master, clocks), 58 __field(int, clocks) 62 __entry->clocks = clocks; 65 __entry->master_idx, __entry->clocks
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/linux-master/arch/arm/mach-omap1/ |
H A D | sram.S | 43 mov r4, #0x0700 @ let the clocks settle
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/linux-master/arch/powerpc/platforms/52xx/ |
H A D | mpc52xx_gpt.c | 387 u64 clocks; local 399 /* Determine the number of clocks in the requested period. 64 bit 403 clocks = period * (u64)gpt->ipb_freq; 404 do_div(clocks, 1000000000); /* Scale it down to ns range */ 407 if (clocks > 0xffffffff) 410 /* Calculate the prescaler and count values from the clocks value. 411 * 'clocks' is the number of clock ticks in the period. The timer 413 * calculated by integer dividing the clocks by 0x10000 (shifting 414 * down 16 bits) to obtain the smallest possible divisor for clocks 422 prescale = (clocks >> 1 [all...] |
/linux-master/arch/x86/kernel/apic/ |
H A D | apic.c | 266 * 'clocks' APIC bus clock. During calibration we actually call 274 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) argument 317 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 609 * In this functions we calibrate APIC bus clocks to the external timer.
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/linux-master/drivers/ata/ |
H A D | pata_atp867x.c | 142 unsigned char clocks = clk; local 149 clocks++; 151 switch (clocks) { 153 clocks = 1; 162 clocks = 7; /* 12 clk */ 166 clocks = 0; 171 return clocks << ATP867X_IO_PIOSPD_ACTIVE_SHIFT; 177 unsigned char clocks = clk; local 179 switch (clocks) { 181 clocks [all...] |
H A D | pata_hpt366.c | 122 struct hpt_clock *clocks = ap->host->private_data; local 124 while (clocks->xfer_mode) { 125 if (clocks->xfer_mode == speed) 126 return clocks->timing; 127 clocks++;
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H A D | pata_hpt37x.c | 36 struct hpt_clock const *clocks[4]; member in struct:hpt_chip 210 struct hpt_clock *clocks = ap->host->private_data; local 212 while (clocks->xfer_speed) { 213 if (clocks->xfer_speed == speed) 214 return clocks->timing; 215 clocks++; 940 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { 989 private_data = (void *)chip_table->clocks[clock_slot]; 993 * about lack of UDMA133 support on lower clocks
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H A D | pata_hpt3x2n.c | 61 /* 66MHz DPLL clocks */ 90 * that matches the speed provided. For the moment the clocks table 97 struct hpt_clock *clocks = hpt3x2n_clocks; local 99 while (clocks->xfer_speed) { 100 if (clocks->xfer_speed == speed) 101 return clocks->timing; 102 clocks++;
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/linux-master/drivers/bus/ |
H A D | ti-sysc.c | 103 * @clocks: clocks used by the interconnect target module 104 * @clock_roles: clock role names for the found clocks 105 * @nr_clocks: number of clocks used by the interconnect target module 135 struct clk **clocks; member in struct:sysc 396 if (!ddata->clocks[i]) { 408 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 409 if (IS_ERR(ddata->clocks[index])) { 411 name, PTR_ERR(ddata->clocks[index])); 413 return PTR_ERR(ddata->clocks[inde [all...] |
/linux-master/drivers/clk/bcm/ |
H A D | clk-bcm21664.c | 17 .clocks = CLOCKS("ref_crystal"), 35 .clocks = CLOCKS("bbl_32k", 59 .clocks = CLOCKS("ref_crystal", 71 .clocks = CLOCKS("ref_crystal", 83 .clocks = CLOCKS("ref_crystal", 95 .clocks = CLOCKS("ref_crystal", 106 .clocks = CLOCKS("ref_32k"), /* Verify */ 111 .clocks = CLOCKS("ref_32k"), /* Verify */ 116 .clocks = CLOCKS("ref_32k"), /* Verify */ 121 .clocks [all...] |
H A D | clk-bcm281xx.c | 19 .clocks = CLOCKS("ref_crystal"), 35 .clocks = CLOCKS("bbl_32k", 44 .clocks = CLOCKS("ref_crystal", 53 .clocks = CLOCKS("var_312m", 77 .clocks = CLOCKS("ref_crystal", 96 .clocks = CLOCKS("ref_crystal", 108 .clocks = CLOCKS("ref_crystal", 120 .clocks = CLOCKS("ref_crystal", 132 .clocks = CLOCKS("ref_crystal", 144 .clocks [all...] |
H A D | clk-kona-setup.c | 502 * placeholders for non-supported clocks. Keep track of the 527 static u32 *parent_process(const char *clocks[], argument 541 if (!clocks) 548 for (clock = clocks; *clock; clock++) 551 orig_count = (u32)(clock - clocks); 554 /* If all clocks are unsupported, we treat it as no clock */ 588 if (clocks[i] != BAD_CLK_NAME) { 589 parent_names[j] = clocks[i]; 601 clk_sel_setup(const char **clocks, struct bcm_clk_sel *sel, argument 611 * by the parent clock's position in the "clocks" lis [all...] |
H A D | clk-kona.h | 77 * CCU policy control for clocks. Clocks can be enabled or disabled 104 * Enabling or disabling clocks with this type of gate is 105 * managed automatically by the hardware. Such clocks can be 107 * of auto-gated clocks can be read from the gate status bit. 202 /* Gate hysteresis for clocks */ 312 * Clocks may have multiple "parent" clocks. If there is more than 314 * clocks is currently in use. The selected clock is indicated in a 317 * available parent clocks. Occasionally the reset value of a 321 * We register all known parent clocks with the common clock code 391 const char *clocks[]; /* mus member in struct:peri_clk_data [all...] |
/linux-master/drivers/clk/ |
H A D | clkdev.c | 24 static LIST_HEAD(clocks); 48 list_for_each_entry(p, &clocks, node) { 124 list_add_tail(&cl->node, &clocks); 141 list_add_tail(&cl->node, &clocks);
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/linux-master/drivers/clk/hisilicon/ |
H A D | clk.h | 142 struct clk **clocks = data->clk_data.clks; \ 146 if (clocks[id]) \ 147 clk_unregister_##type(clocks[id]); \
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/linux-master/drivers/clk/ingenic/ |
H A D | cgu.c | 329 * Operations for all non-PLL clocks 667 cgu->clocks.clks[idx] = clk; 712 parent = cgu->clocks.clks[clk_info->parents[i]]; 723 parent = cgu->clocks.clks[clk_info->parents[0]]; 778 cgu->clocks.clks[idx] = clk; 803 cgu->clocks.clk_num = num_clocks; 820 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *), 822 if (!cgu->clocks.clks) { 827 for (i = 0; i < cgu->clocks [all...] |
H A D | cgu.h | 96 * @bypass_mask: mask of parent clocks for which the divider does not apply 194 * @clock_info: an array containing information about implemented clocks 195 * @clocks: used to provide clocks to DT, allows lookup of struct clk* 203 struct clk_onecell_data clocks; member in struct:ingenic_cgu 224 * @clock_info: an array of clock information structures describing the clocks 237 * ingenic_cgu_register_clocks() - Registers the clocks 240 * Register the clocks described by the CGU with the common clock framework.
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H A D | tcu.c | 3 * JZ47xx SoCs TCU clocks driver 55 struct clk_hw_onecell_data *clocks; member in struct:ingenic_tcu 271 struct clk_hw_onecell_data *clocks) 296 clocks->hws[idx] = &tcu_clk->hw; 382 tcu->clocks = kzalloc(struct_size(tcu->clocks, hws, TCU_CLK_COUNT), 384 if (!tcu->clocks) { 389 tcu->clocks->num = TCU_CLK_COUNT; 394 tcu->clocks); 402 * We set EXT as the default parent clock for all the TCU clocks 268 ingenic_tcu_register_clock(struct ingenic_tcu *tcu, unsigned int idx, enum tcu_clk_parent parent, const struct ingenic_tcu_clk_info *info, struct clk_hw_onecell_data *clocks) argument [all...] |
/linux-master/drivers/clk/keystone/ |
H A D | sci-clk.c | 26 * @ops: Pointer to the SCI ops to be used by the clocks 28 * @clocks: Clocks array for this device 29 * @num_clocks: Total number of clocks for this provider 35 struct sci_clk **clocks; member in struct:sci_clk_provider 47 * @node: Link for handling clocks probed via DT 204 * @parent_rate: rate of the clock parent, not used for TI SCI clocks 282 * executed, or recursively from itself when parsing parent clocks. 302 * From kernel point of view, we only care about a clocks parents, 390 clk = bsearch(&key, provider->clocks, provider->num_clocks, 405 ret = _sci_clk_build(p, p->clocks[ [all...] |
/linux-master/drivers/clk/renesas/ |
H A D | Makefile | 34 obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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H A D | r9a06g032-clocks.c | 111 * @ffc: substructure for fixed-factor clocks 629 * These are not hardware clocks, but are needed to handle the special 699 static void clk_rdesc_set(struct r9a06g032_priv *clocks, argument 702 u32 __iomem *reg = clocks->reg + (rb.reg * 4); 713 static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb) argument 715 u32 __iomem *reg = clocks->reg + (rb.reg * 4); 728 struct r9a06g032_priv *clocks; member in struct:r9a06g032_clk_gate 770 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++, 815 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, argument 822 spin_lock_irqsave(&clocks 877 r9a06g032_register_gate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) argument 920 struct r9a06g032_priv *clocks; member in struct:r9a06g032_clk_div 1048 r9a06g032_register_div(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) argument 1101 struct r9a06g032_priv *clocks; member in struct:r9a06g032_clk_bitsel 1133 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) argument 1171 struct r9a06g032_priv *clocks; member in struct:r9a06g032_clk_dualgate 1223 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc, struct regbit sel) argument 1273 r9a06g032_init_h2mode(struct r9a06g032_priv *clocks) argument 1299 struct r9a06g032_priv *clocks; local [all...] |
/linux-master/drivers/clk/rockchip/ |
H A D | clk.c | 616 void rockchip_clk_protect_critical(const char *const clocks[], argument 621 /* Protect the clocks that needs to stay on */ 623 struct clk *clk = __clk_lookup(clocks[i]);
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