Searched refs:base_reg (Results 1 - 25 of 56) sorted by path

123

/linux-master/arch/sparc/include/asm/
H A Dwinmacro.h38 #define LOAD_PT_INS(base_reg) \
39 ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
40 ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
41 ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
42 ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
44 #define LOAD_PT_GLOBALS(base_reg) \
45 ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
46 ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
47 ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
48 ldd [%base_reg
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/linux-master/drivers/media/dvb-frontends/
H A Ddibx000_common.c82 while (((status = dibx000_read_word(mst, mst->base_reg + 2)) & 0x0100) == 0 && --i > 0)
105 dibx000_read_word(mst, mst->base_reg + 2);
112 dibx000_write_word(mst, mst->base_reg, data);
129 dibx000_write_word(mst, mst->base_reg+1, da);
161 dibx000_write_word(mst, mst->base_reg+1, da);
169 da = dibx000_read_word(mst, mst->base_reg);
188 return dibx000_write_word(mst, mst->base_reg + 3, (u16)(60000 / speed));
204 return dibx000_write_word(mst, mst->base_reg + 4, intf);
277 tx[0] = (((mst->base_reg + 1) >> 8) & 0xff);
278 tx[1] = ((mst->base_reg
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H A Ddibx000_common.h31 u16 base_reg; member in struct:dibx000_i2c_master
/linux-master/arch/arm/mach-omap1/
H A Dirq.c58 unsigned long base_reg; member in struct:omap_irq_bank
116 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
117 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
120 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
121 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
128 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
129 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
130 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
131 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
208 irq_banks[i].va = ioremap(irq_banks[i].base_reg,
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/linux-master/arch/mips/kernel/
H A Dmips-cm.c203 u32 base_reg; local
209 base_reg = read_gcr_l2_only_sync_base();
210 if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN)
211 return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE;
243 u32 base_reg; local
263 base_reg = read_gcr_base();
264 if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) {
/linux-master/arch/powerpc/perf/
H A Dimc-pmu.c161 /* Add the base_reg value to the "reg" */
226 u32 handle, base_reg; local
257 of_property_read_u32(node, "reg", &base_reg);
269 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
/linux-master/arch/x86/kvm/
H A Demulate.c1170 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) argument
1172 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1180 int index_reg, base_reg, scale; local
1186 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1190 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1272 base_reg |= sib & 7;
1275 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1278 modrm_ea += reg_read(ctxt, base_reg);
1279 adjust_modrm_seg(ctxt, base_reg);
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/linux-master/arch/x86/kvm/vmx/
H A Dnested.c5006 int base_reg = (vmx_instruction_info >> 23) & 0xf; local
5022 off += kvm_register_read(vcpu, base_reg);
/linux-master/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c394 u64 base_reg; local
403 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
413 WREG32(base_reg + 0xE80, 0x80004);
414 WREG32(base_reg + 0xD64, 7);
415 WREG32(base_reg + 0xD60, 0);
416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
417 WREG32(base_reg + 0xD60, 1);
418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
419 WREG32(base_reg
472 u64 base_reg; local
701 u64 base_reg; local
721 u64 base_reg; local
782 u64 base_reg; local
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/linux-master/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_coresight.c1955 const u64 base_reg)
1959 WREG32(base_reg + mmCORESIGHT_UNLOCK_REGISTER_OFFSET, CORESIGHT_UNLOCK);
1961 rc = gaudi2_coresight_timeout(hdev, base_reg + mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET,
1967 base_reg);
1975 u64 base_reg; local
1985 base_reg = debug_stm_regs[params->reg_idx];
1990 if (!base_reg)
1997 read_reg = RREG32(base_reg + mmSTM_STMDMAIDR_OFFSET);
2001 rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2011 WREG32(base_reg
1954 gaudi2_unlock_coresight_unit(struct hl_device *hdev, const u64 base_reg) argument
2062 u64 base_reg; local
2302 u64 base_reg; local
2342 u64 base_reg; local
2443 u64 base_reg; local
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/linux-master/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c232 u64 base_reg; local
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
251 WREG32(base_reg + 0xE80, 0x80004);
252 WREG32(base_reg + 0xD64, 7);
253 WREG32(base_reg + 0xD60, 0);
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask));
256 WREG32(base_reg + 0xD60, 1);
257 WREG32(base_reg
305 u64 base_reg; local
487 u64 base_reg; local
507 u64 base_reg; local
578 u64 base_reg; local
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/linux-master/drivers/base/regmap/
H A Dinternal.h26 unsigned int base_reg; member in struct:regmap_debugfs_off_cache
H A Dregcache-rbtree.c27 unsigned int base_reg; member in struct:regcache_rbtree_node
44 *base = rbnode->base_reg;
45 *top = rbnode->base_reg + ((rbnode->blklen - 1) * map->reg_stride);
68 unsigned int base_reg, top_reg; local
72 regcache_rbtree_get_base_top_reg(map, rbnode, &base_reg,
74 if (reg >= base_reg && reg <= top_reg)
81 regcache_rbtree_get_base_top_reg(map, rbnode, &base_reg,
83 if (reg >= base_reg && reg <= top_reg) {
88 } else if (reg < base_reg) {
102 unsigned int base_reg; local
262 regcache_rbtree_insert_to_block(struct regmap *map, struct regcache_rbtree_node *rbnode, unsigned int base_reg, unsigned int top_reg, unsigned int reg, unsigned int value) argument
387 unsigned int base_reg, top_reg; local
471 unsigned int base_reg, top_reg; local
516 unsigned int base_reg, top_reg; local
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H A Dregmap-debugfs.c140 c->base_reg = i;
170 return c->base_reg + (reg_offset * map->reg_stride);
205 if (reg < c->base_reg) {
206 ret = c->base_reg;
403 c->base_reg, c->max_reg);
/linux-master/drivers/bus/
H A Duniphier-system-bus.c118 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; local
121 is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE);
136 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; local
171 writel(val, base_reg + UNIPHIER_SBC_STRIDE * i);
/linux-master/drivers/clk/
H A Dclk-en7523.c46 u32 base_reg; member in struct:en_clk_desc
84 .base_reg = REG_GSW_CLK_DIV_SEL,
97 .base_reg = REG_EMI_CLK_DIV_SEL,
110 .base_reg = REG_BUS_CLK_DIV_SEL,
123 .base_reg = REG_SPI_CLK_FREQ_SEL,
138 .base_reg = REG_SPI_CLK_DIV_SEL,
150 .base_reg = REG_NPU_CLK_DIV_SEL,
163 .base_reg = REG_CRYPTO_CLKSRC,
179 val = readl(base + desc->base_reg);
197 reg = desc->div_reg ? desc->div_reg : desc->base_reg;
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/linux-master/drivers/clk/tegra/
H A Dclk-pll.c231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
306 lock_addr += pll->params->base_reg;
2082 val = readl_relaxed(clk_base + pll_params->base_reg);
2660 val = readl_relaxed(clk_base + pll_params->base_reg);
H A Dclk-tegra114.c184 .base_reg = PLLC_BASE,
235 .base_reg = PLLC2_BASE,
257 .base_reg = PLLC3_BASE,
306 .base_reg = PLLM_BASE,
346 .base_reg = PLLP_BASE,
376 .base_reg = PLLA_BASE,
412 .base_reg = PLLD_BASE,
430 .base_reg = PLLD2_BASE,
472 .base_reg = PLLU_BASE,
501 .base_reg
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H A Dclk-tegra124.c188 .base_reg = PLLX_BASE,
222 .base_reg = PLLC_BASE,
276 .base_reg = PLLC2_BASE,
298 .base_reg = PLLC3_BASE,
357 .base_reg = PLLC4_BASE,
420 .base_reg = PLLM_BASE,
477 .base_reg = PLLE_BASE,
516 .base_reg = PLLRE_BASE,
553 .base_reg = PLLP_BASE,
582 .base_reg
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H A Dclk-tegra20.c284 .base_reg = PLLC_BASE,
300 .base_reg = PLLM_BASE,
316 .base_reg = PLLP_BASE,
334 .base_reg = PLLA_BASE,
350 .base_reg = PLLD_BASE,
372 .base_reg = PLLU_BASE,
389 .base_reg = PLLX_BASE,
407 .base_reg = PLLE_BASE,
H A Dclk-tegra210.c785 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
834 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
871 writel_relaxed(val, clk_base + plla->params->base_reg);
890 if (readl_relaxed(clk_base + plld->params->base_reg) &
940 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
991 plldss->params->base_reg);
1006 writel_relaxed(val, clk_base + plldss->params->base_reg);
1059 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
1103 writel_relaxed(val, clk_base + pllre->params->base_reg);
1188 if (readl_relaxed(clk_base + pllx->params->base_reg)
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H A Dclk-tegra30.c359 .base_reg = PLLC_BASE,
388 .base_reg = PLLM_BASE,
409 .base_reg = PLLP_BASE,
427 .base_reg = PLLA_BASE,
444 .base_reg = PLLD_BASE,
461 .base_reg = PLLD2_BASE,
478 .base_reg = PLLU_BASE,
496 .base_reg = PLLX_BASE,
515 .base_reg = PLLE_BASE,
H A Dclk.h223 * @base_reg: PLL base reg offset
308 u32 base_reg; member in struct:tegra_clk_pll_params
/linux-master/drivers/clk/visconti/
H A Dpll.c309 list->base_reg,
H A Dpll.h52 unsigned long base_reg; member in struct:visconti_pll_info

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