Searched refs:acr (Results 1 - 25 of 58) sorted by path

123

/linux-master/arch/powerpc/include/asm/
H A Dmpc52xx_psc.h91 /* PSC acr bits */
177 u8 acr; member in union:mpc52xx_psc::__anon10
180 #define mpc52xx_psc_acr ipcr_acr.acr
324 u8 acr; /* PSC + 0x1c */ member in struct:mpc5125_psc::__anon16
/linux-master/drivers/ipack/devices/
H A Dscc2698.h70 u8 d4, acr; /* Auxiliary control register of block */ member in struct:scc2698_block::__anon346
/linux-master/arch/arm/kernel/
H A Dhead-nommu.S223 .macro setup_region bar, acr, sr, side = PMSAv7_DATA_SIDE, unused
225 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
234 .macro setup_region bar, acr, sr, unused, base
235 lsl \acr, \acr, #16
236 orr \acr, \acr, \sr
238 str \acr, [\base, #PMSAv7_RASR]
/linux-master/arch/arm/mach-omap2/
H A Domap-secure.c192 u32 acr; local
195 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
196 acr &= ~clear_bits;
197 acr |= set_bits;
202 1, acr, 0, 0, 0);
H A Domap-smp.c77 u32 acr, revidr; local
85 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
94 if ((acr & acr_mask) == acr_mask)
97 acr |= acr_mask;
98 omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
123 u32 acr, acr_mask; local
125 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
133 if ((acr & acr_mask) == acr_mask)
136 acr |= acr_mask;
137 omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
[all...]
/linux-master/arch/arm/mm/
H A Dcache-l2x0.c625 u32 acr = get_auxcr(); local
627 pr_debug("Cortex-A9 ACR=0x%08x\n", acr);
629 if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO))
632 if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3)))
/linux-master/drivers/atm/
H A Diphase.c1834 vc->acr = cellrate_to_float(iadev->LineRate);
1836 vc->acr = cellrate_to_float(vcc->qos.txtp.pcr);
1838 vcc->qos.txtp.max_pcr,vc->acr);)
H A Diphase.h254 u_short acr; member in struct:main_vc
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v10_0.c1486 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); local
1492 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1495 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1499 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1502 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1506 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1509 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
H A Ddce_v11_0.c1535 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); local
1541 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1544 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1548 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1551 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1555 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1558 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
H A Ddce_v6_0.c1431 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); local
1443 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1446 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1450 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1453 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1457 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1460 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
H A Ddce_v8_0.c1467 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); local
1472 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1473 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1475 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1476 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1478 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1479 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dlayout.h22 NVKM_LAYOUT_ONCE(NVKM_SUBDEV_ACR , struct nvkm_acr , acr)
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dbase.c2011 .acr = { 0x00000001, gm200_acr_new },
2046 .acr = { 0x00000001, gm200_acr_new },
2081 .acr = { 0x00000001, gm200_acr_new },
2116 .acr = { 0x00000001, gm20b_acr_new },
2141 .acr = { 0x00000001, gm200_acr_new },
2174 .acr = { 0x00000001, gp102_acr_new },
2208 .acr = { 0x00000001, gp102_acr_new },
2242 .acr = { 0x00000001, gp102_acr_new },
2276 .acr = { 0x00000001, gp102_acr_new },
2310 .acr
[all...]
H A Dpriv.h6 #include <subdev/acr.h>
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dga102.c27 #include <subdev/acr.h>
H A Dgf100.c31 #include <subdev/acr.h>
H A Dgm200.c28 #include <subdev/acr.h>
46 gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
49 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
52 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
53 flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr);
57 gm200_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, argument
73 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
H A Dgm20b.c26 #include <subdev/acr.h>
34 gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
39 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
46 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
48 flcn_bl_dmem_desc_dump(&acr->subdev, &hdr);
52 gm20b_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, argument
70 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
87 if (!device->acr) {
H A Dgp108.c24 #include <subdev/acr.h>
29 gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
32 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
35 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
36 flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
40 gp108_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, argument
56 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
H A Dgp10b.c26 #include <subdev/acr.h>
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
H A Dga102.c23 #include <subdev/acr.h>
181 NVKM_ACR_LSF_SEC2, "sec2/", ver, fwif->acr);
H A Dgp102.c25 #include <subdev/acr.h>
78 gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
81 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
85 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
86 loader_config_v1_dump(&acr->subdev, &hdr);
90 gp102_sec2_acr_bld_write(struct nvkm_acr *acr, u32 bld, argument
107 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
241 gp102_sec2_acr_bld_patch_1(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
244 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
247 nvkm_wobj(acr
252 gp102_sec2_acr_bld_write_1(struct nvkm_acr *acr, u32 bld, struct nvkm_acr_lsfw *lsfw) argument
[all...]
H A Dgp108.c23 #include <subdev/acr.h>
H A Dpriv.h26 const struct nvkm_acr_lsf_func *acr; member in struct:nvkm_sec2_fwif

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