| /u-boot/arch/m68k/include/asm/ |
| H A D | ptrace.h | 23 ulong a2; member in struct:pt_regs
|
| /u-boot/arch/mips/include/asm/ |
| H A D | regdef.h | 25 #define a2 $6 macro
68 #define a2 $6 macro
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| /u-boot/arch/riscv/include/asm/ |
| H A D | ptrace.h | 25 unsigned long a2; member in struct:pt_regs
|
| /u-boot/arch/xtensa/lib/ |
| H A D | misc.S | 24 ___invalidate_icache_page a2 a3
39 ___invalidate_dcache_page a2 a3
54 ___flush_invalidate_dcache_page a2 a3
69 ___flush_dcache_page a2 a3
84 ___invalidate_icache_range a2 a3 a4
99 ___flush_invalidate_dcache_range a2 a3 a4
114 ___flush_dcache_range a2 a3 a4
129 ___invalidate_dcache_range a2 a3 a4
143 ___invalidate_icache_all a2 a3
158 ___flush_invalidate_dcache_all a2 a
[all...] |
| /u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | cpu.c | 1372 debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2);
1374 gd->bd->bi_dram[i].size = res.a2;
|
| /u-boot/arch/arm/lib/ |
| H A D | asm-offsets.c | 95 DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
100 DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS, offsetof(struct arm_smccc_1_2_regs, a2));
|
| H A D | setjmp.S | 28 mov a1, a2
|
| /u-boot/arch/m68k/cpu/mcf523x/ |
| H A D | start.S | 111 move.l #(DCACHE_STATUS), %a2 /* icache */
113 move.l %d0, (%a2)
171 move.l #__init_end, %a2
177 cmp.l %a1,%a2
184 move.l #(__rel_dyn_end), %a2
210 cmp.l %a1, %a2
|
| /u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | start.S | 140 move.l #(CFG_SYS_INIT_RAM_ADDR), %a2
142 move.l (%a0)+, (%a2)+
190 move.l #(DCACHE_STATUS), %a2 /* icache */
192 move.l %d0, (%a2)
250 move.l #__init_end, %a2
255 cmp.l %a1,%a2
262 move.l #(__rel_dyn_end), %a2
288 cmp.l %a1, %a2
|
| /u-boot/arch/m68k/cpu/mcf530x/ |
| H A D | start.S | 120 move.l #(DCACHE_STATUS), %a2 /* dcache */
122 move.l %d0, (%a2)
175 move.l #__init_end, %a2
180 cmp.l %a1,%a2
187 move.l #(__rel_dyn_end), %a2
213 cmp.l %a1, %a2
|
| /u-boot/arch/m68k/cpu/mcf532x/ |
| H A D | start.S | 126 move.l #(DCACHE_STATUS), %a2 /* icache */
128 move.l %d0, (%a2)
186 move.l #__init_end, %a2
192 cmp.l %a1,%a2
199 move.l #(__rel_dyn_end), %a2
225 cmp.l %a1, %a2
|
| /u-boot/arch/m68k/cpu/mcf5445x/ |
| H A D | start.S | 142 move.l #(DCACHE_STATUS), %a2 /* dcache */
144 move.l %d0, (%a2)
189 * a2 - dtfr
197 move.l #0xEC09404F, %a2
199 move.b #0x80, (%a2)
211 move.l #0xFC05C034, %a2 /* dtfr */
282 move.l %d2, (%a2)
300 move.l #CONFIG_TEXT_BASE, %a2 /* dst */
304 move.l (%a1)+, (%a2)+
321 move.l #(ICACHE_STATUS), %a2 /* icach
[all...] |
| /u-boot/arch/m68k/lib/ |
| H A D | traps.c | 32 fp->a0, fp->a1, fp->a2, fp->a3);
|
| /u-boot/arch/mips/mach-ath79/qca956x/ |
| H A D | qca956x-ddr-tap.S | 28 li a2, 0x08000000 /* Setting the RST_RESET_RTC_RESET */
29 or a1, a1, a2
33 xor a2, a2, a3
34 and a1, a1, a2
42 li a2, 0x2
46 and a1, a2, a1
47 bne a1, a2, _poll_for_RTC_ON
|
| /u-boot/arch/mips/mach-mtmips/mt7621/spl/ |
| H A D | launch_ll.S | 127 move a2, zero
148 li a2, CONFIG_SYS_DCACHE_SIZE
175 PTR_ADDU t1, t0, a2
220 /* a2 = current TC No. */
221 move a2, zero
232 ins t0, a2, 0, 8
237 beqz a2, _next_vpe
245 slt t1, a1, a2
251 ins t0, a2, VPECONF0_XTC_SHIFT, 8
254 move t1, a2
[all...] |
| H A D | start.S | 170 la a2, __image_copy_end
171 sub a2, a2, a1
|
| /u-boot/arch/mips/mach-mtmips/mt7628/ |
| H A D | lowlevel_init.S | 100 li a2, 0x1ffff800 /* Mask of DTagLo[PTagLo] */
104 and t0, a0, a2
|
| /u-boot/arch/mips/mach-octeon/ |
| H A D | lowlevel_init.S | 72 ld a2, 16(t0)
76 sd a2, 16(t1)
127 ld a2, 0x18(t9)
|
| /u-boot/arch/riscv/cpu/ |
| H A D | mtrap.S | 66 csrr a2, MODE_PREFIX(tval)
|
| H A D | start.S | 257 mv a2, s0
290 mv s4, a2 /* save addr of destination */
392 mv a2, s3
438 /* a2: new gd */
446 mv gp, a2
|
| /u-boot/arch/riscv/lib/ |
| H A D | interrupts.c | 47 regs->a1, regs->a2, regs->a3);
|
| H A D | memcpy.S | 22 add t0, a0, a2
33 bltu a2, a3, .Lbyte_copy_tail
38 addi a2, a0, SZREG-1
39 andi a2, a2, ~(SZREG-1)
40 beq a0, a2, 2f
46 bne a0, a2, 1b
61 REG_L a2, 0(a1)
72 REG_S a2, 0(a0)
83 REG_L a2, 1
[all...] |
| H A D | memmove.S | 12 * If a0 >= a1, t0 gives their distance, if t0 >= a2 then we can
15 * so a *unsigned* comparison will always have t0 >= a2.
20 bltu t0, a2, 1f
31 add a0, a0, a2
32 add a1, a1, a2
43 bltu a2, a3, .Lbyte_copy_tail
48 andi a2, a0, ~(SZREG-1)
49 beq a0, a2, 2f
55 bne a0, a2, 1b
116 srl a2, a
[all...] |
| H A D | memset.S | 16 sltiu a3, a2, 16
32 sub a2, a2, a4 /* Update count */
47 andi a4, a2, ~(SZREG-1)
101 andi a2, a2, SZREG-1 /* Update count */
105 beqz a2, 6f
106 add a3, t0, a2
|
| H A D | sbi.c | 23 register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
31 : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
|