1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 *
6 * Copyright 2010-2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 */
9
10#include <asm-offsets.h>
11#include <config.h>
12#include <asm/cache.h>
13
14#define _START	_start
15#define _FAULT	_fault
16
17#define SAVE_ALL						\
18	move.w	#0x2700,%sr;		/* disable intrs */	\
19	subl	#60,%sp;		/* space for 15 regs */ \
20	moveml	%d0-%d7/%a0-%a6,%sp@;
21
22#define RESTORE_ALL						\
23	moveml	%sp@,%d0-%d7/%a0-%a6;				\
24	addl	#60,%sp;		/* space for 15 regs */ \
25	rte;
26
27#if defined(CONFIG_SERIAL_BOOT)
28#define ASM_DRAMINIT	(asm_dram_init - CONFIG_TEXT_BASE + \
29	CFG_SYS_INIT_RAM_ADDR)
30#define ASM_DRAMINIT_N	(asm_dram_init - CONFIG_TEXT_BASE)
31#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_TEXT_BASE + \
32	CFG_SYS_INIT_RAM_ADDR)
33#endif
34
35.text
36
37/*
38 * Vector table. This is used for initial platform startup.
39 * These vectors are to catch any un-intended traps.
40 */
41_vectors:
42#if defined(CONFIG_SERIAL_BOOT)
43
44INITSP:	.long	0			/* Initial SP	*/
45#ifdef CONFIG_CF_SBF
46INITPC:	.long	ASM_DRAMINIT		/* Initial PC	*/
47#endif
48#ifdef CONFIG_SYS_NAND_BOOT
49INITPC:	.long	ASM_DRAMINIT_N		/* Initial PC	*/
50#endif
51
52#else
53
54INITSP:	.long	0			/* Initial SP	*/
55INITPC:	.long	_START			/* Initial PC	*/
56
57#endif
58
59vector02_0F:
60.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
61.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
62
63/* Reserved */
64vector10_17:
65.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66
67vector18_1F:
68.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69
70#if !defined(CONFIG_SERIAL_BOOT)
71
72/* TRAP #0 - #15 */
73vector20_2F:
74.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76
77/* Reserved	*/
78vector30_3F:
79.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81
82vector64_127:
83.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91
92vector128_191:
93.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101
102vector192_255:
103.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
106.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111#endif
112
113#if defined(CONFIG_SERIAL_BOOT)
114	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
115asm_sbf_img_hdr:
116	.long	0x00000000		/* checksum, not yet implemented */
117	.long	0x00040000		/* image length */
118	.long	CONFIG_TEXT_BASE	/* image to be relocated at */
119
120asm_dram_init:
121	move.w	#0x2700,%sr		/* Mask off Interrupt */
122
123#ifdef CONFIG_SYS_NAND_BOOT
124	/* for assembly stack */
125	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
126	movec	%d0, %RAMBAR1
127
128	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
129	clr.l	%sp@-
130#endif
131
132#ifdef CONFIG_CF_SBF
133	move.l	#CFG_SYS_INIT_RAM_ADDR, %d0
134	movec	%d0, %VBR
135
136	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
137	movec	%d0, %RAMBAR1
138
139	/* initialize general use internal ram */
140	move.l	#0, %d0
141	move.l	#(ICACHE_STATUS), %a1	/* icache */
142	move.l	#(DCACHE_STATUS), %a2	/* dcache */
143	move.l	%d0, (%a1)
144	move.l	%d0, (%a2)
145
146	/* invalidate and disable cache */
147	move.l	#(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
148	movec	%d0, %CACR		/* Invalidate cache */
149	move.l	#0, %d0
150	movec	%d0, %ACR0
151	movec	%d0, %ACR1
152	movec	%d0, %ACR2
153	movec	%d0, %ACR3
154
155	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
156	clr.l	%sp@-
157
158#ifdef CFG_SYS_CS0_BASE
159	/* Must disable global address */
160	move.l	#0xFC008000, %a1
161	move.l	#(CFG_SYS_CS0_BASE), (%a1)
162	move.l	#0xFC008008, %a1
163	move.l	#(CFG_SYS_CS0_CTRL), (%a1)
164	move.l	#0xFC008004, %a1
165	move.l	#(CFG_SYS_CS0_MASK), (%a1)
166#endif
167#endif /* CONFIG_CF_SBF */
168
169#ifdef CONFIG_MCF5441x
170	/* TC: enable all peripherals,
171	in the future only enable certain peripherals */
172	move.l	#0xFC04002D, %a1
173
174#if defined(CONFIG_CF_SBF)
175	move.b	#23, (%a1)		/* dspi */
176#endif
177#endif	/* CONFIG_MCF5441x */
178
179	/* mandatory board level ddr-sdram init,
180	 * for both 5441x and 5445x
181	 */
182	bsr	sbf_dram_init
183
184#ifdef CONFIG_CF_SBF
185	/*
186	 * DSPI Initialization
187	 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
188	 * a1 - dspi status
189	 * a2 - dtfr
190	 * a3 - drfr
191	 * a4 - Dst addr
192	 */
193	/* Enable pins for DSPI mode - chip-selects are enabled later */
194asm_dspi_init:
195#ifdef CONFIG_MCF5441x
196	move.l	#0xEC09404E, %a1
197	move.l	#0xEC09404F, %a2
198	move.b	#0xFF, (%a1)
199	move.b	#0x80, (%a2)
200#endif
201
202	/* Configure DSPI module */
203	move.l	#0xFC05C000, %a0
204	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
205
206	move.l	#0xFC05C00C, %a0
207#ifdef CONFIG_MCF5441x
208	move.l	#0x3E000016, (%a0)
209#endif
210
211	move.l	#0xFC05C034, %a2	/* dtfr */
212	move.l	#0xFC05C03B, %a3	/* drfr */
213
214	move.l	#(ASM_SBF_IMG_HDR + 4), %a1
215	move.l	(%a1)+, %d5
216	move.l	(%a1), %a4
217
218	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0
219	move.l	#(CFG_SYS_SBFHDR_SIZE), %d4
220
221	move.l	#0xFC05C02C, %a1	/* dspi status */
222
223	/* Issue commands and address */
224	move.l	#0x8002000B, %d2	/* Fast Read Cmd */
225	jsr	asm_dspi_wr_status
226	jsr	asm_dspi_rd_status
227
228	move.l	#0x80020000, %d2	/* Address byte 2 */
229	jsr	asm_dspi_wr_status
230	jsr	asm_dspi_rd_status
231
232	move.l	#0x80020000, %d2	/* Address byte 1 */
233	jsr	asm_dspi_wr_status
234	jsr	asm_dspi_rd_status
235
236	move.l	#0x80020000, %d2	/* Address byte 0 */
237	jsr	asm_dspi_wr_status
238	jsr	asm_dspi_rd_status
239
240	move.l	#0x80020000, %d2	/* Dummy Wr and Rd */
241	jsr	asm_dspi_wr_status
242	jsr	asm_dspi_rd_status
243
244	/* Transfer serial boot header to sram */
245asm_dspi_rd_loop1:
246	move.l	#0x80020000, %d2
247	jsr	asm_dspi_wr_status
248	jsr	asm_dspi_rd_status
249
250	move.b	%d1, (%a0)		/* read, copy to dst */
251
252	add.l	#1, %a0			/* inc dst by 1 */
253	sub.l	#1, %d4			/* dec cnt by 1 */
254	bne	asm_dspi_rd_loop1
255
256	/* Transfer u-boot from serial flash to memory */
257asm_dspi_rd_loop2:
258	move.l	#0x80020000, %d2
259	jsr	asm_dspi_wr_status
260	jsr	asm_dspi_rd_status
261
262	move.b	%d1, (%a4)		/* read, copy to dst */
263
264	add.l	#1, %a4			/* inc dst by 1 */
265	sub.l	#1, %d5			/* dec cnt by 1 */
266	bne	asm_dspi_rd_loop2
267
268	move.l	#0x00020000, %d2	/* Terminate */
269	jsr	asm_dspi_wr_status
270	jsr	asm_dspi_rd_status
271
272	/* jump to memory and execute */
273	move.l	#(CONFIG_TEXT_BASE + 0x400), %a0
274	jmp	(%a0)
275
276asm_dspi_wr_status:
277	move.l	(%a1), %d0		/* status */
278	and.l	#0x0000F000, %d0
279	cmp.l	#0x00003000, %d0
280	bgt	asm_dspi_wr_status
281
282	move.l	%d2, (%a2)
283	rts
284
285asm_dspi_rd_status:
286	move.l	(%a1), %d0		/* status */
287	and.l	#0x000000F0, %d0
288	lsr.l	#4, %d0
289	cmp.l	#0, %d0
290	beq	asm_dspi_rd_status
291
292	move.b	(%a3), %d1
293	rts
294#endif /* CONFIG_CF_SBF */
295
296#ifdef CONFIG_SYS_NAND_BOOT
297	/* copy 4 boot pages to dram as soon as possible */
298	/* each page is 996 bytes (1056 total with 60 ECC bytes */
299	move.l  #0x00000000, %a1	/* src */
300	move.l	#CONFIG_TEXT_BASE, %a2		/* dst */
301	move.l	#0x3E0, %d0		/* sz in long */
302
303asm_boot_nand_copy:
304	move.l	(%a1)+, (%a2)+
305	subq.l	#1, %d0
306	bne	asm_boot_nand_copy
307
308	/* jump to memory and execute */
309	move.l	#(asm_nand_init), %a0
310	jmp	(%a0)
311
312asm_nand_init:
313	/* exit nand boot-mode */
314	move.l	#0xFC0FFF30, %a1
315	or.l	#0x00000040, %d1
316	move.l	%d1, (%a1)
317
318	/* initialize general use internal ram */
319	move.l	#0, %d0
320	move.l	#(CACR_STATUS), %a1	/* CACR */
321	move.l	#(ICACHE_STATUS), %a2	/* icache */
322	move.l	#(DCACHE_STATUS), %a3	/* dcache */
323	move.l	%d0, (%a1)
324	move.l	%d0, (%a2)
325	move.l	%d0, (%a3)
326
327	/* invalidate and disable cache */
328	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
329	movec	%d0, %CACR		/* Invalidate cache */
330	move.l	#0, %d0
331	movec	%d0, %ACR0
332	movec	%d0, %ACR1
333	movec	%d0, %ACR2
334	movec	%d0, %ACR3
335
336#ifdef CFG_SYS_CS0_BASE
337	/* Must disable global address */
338	move.l	#0xFC008000, %a1
339	move.l	#(CFG_SYS_CS0_BASE), (%a1)
340	move.l	#0xFC008008, %a1
341	move.l	#(CFG_SYS_CS0_CTRL), (%a1)
342	move.l	#0xFC008004, %a1
343	move.l	#(CFG_SYS_CS0_MASK), (%a1)
344#endif
345
346	/* NAND port configuration */
347	move.l	#0xEC094048, %a1
348	move.b	#0xFD, (%a1)+
349	move.b	#0x5F, (%a1)+
350	move.b	#0x04, (%a1)+
351
352	/* reset nand */
353	move.l  #0xFC0FFF38, %a1	/* isr */
354	move.l  #0x000e0000, (%a1)
355	move.l	#0xFC0FFF08, %a2
356	move.l	#0x00000000, (%a2)+	/* car */
357	move.l	#0x11000000, (%a2)+	/* rar */
358	move.l	#0x00000000, (%a2)+	/* rpt */
359	move.l	#0x00000000, (%a2)+	/* rai */
360	move.l  #0xFC0FFF2c, %a2	/* cfg */
361	move.l  #0x00000000, (%a2)+	/* secsz */
362	move.l  #0x000e0681, (%a2)+
363	move.l  #0xFC0FFF04, %a2	/* cmd2 */
364	move.l  #0xFF404001, (%a2)
365	move.l  #0x000e0000, (%a1)
366
367	move.l	#0x2000, %d1
368	bsr	asm_delay
369
370	/* setup nand */
371	move.l  #0xFC0FFF00, %a1
372	move.l  #0x30700000, (%a1)+	/* cmd1 */
373	move.l  #0x007EF000, (%a1)+	/* cmd2 */
374
375	move.l  #0xFC0FFF2C, %a1
376	move.l  #0x00000841, (%a1)+	/* secsz */
377	move.l  #0x000e0681, (%a1)+	/* cfg */
378
379	move.l	#100, %d4		/* 100 pages ~200KB */
380	move.l	#4, %d2			/* start at 4 */
381	move.l  #0xFC0FFF04, %a0	/* cmd2 */
382	move.l  #0xFC0FFF0C, %a1	/* rar */
383	move.l	#(CONFIG_TEXT_BASE + 0xF80), %a2
384
385asm_nand_read:
386	move.l	#0x11000000, %d0	/* rar */
387	or.l	%d2, %d0
388	move.l	%d0, (%a1)
389	add.l	#1, %d2
390
391	move.l	(%a0), %d0		/* cmd2 */
392	or.l	#1, %d0
393	move.l	%d0, (%a0)
394
395	move.l	#0x200, %d1
396	bsr	asm_delay
397
398asm_nand_chk_status:
399	move.l  #0xFC0FFF38, %a4	/* isr */
400	move.l	(%a4), %d0
401	and.l	#0x40000000, %d0
402	tst.l	%d0
403	beq	asm_nand_chk_status
404
405	move.l  #0xFC0FFF38, %a4	/* isr */
406	move.l	(%a4), %d0
407	or.l	#0x000E0000, %d0
408	move.l	%d0, (%a4)
409
410	move.l	#0x200, %d3
411	move.l	#0xFC0FC000, %a3	/* buf 1 */
412asm_nand_copy:
413	move.l	(%a3)+, (%a2)+
414	subq.l	#1, %d3
415	bgt	asm_nand_copy
416
417	subq.l	#1, %d4
418	bgt	asm_nand_read
419
420	/* jump to memory and execute */
421	move.l	#(CONFIG_TEXT_BASE + 0x400), %a0
422	jmp	(%a0)
423
424#endif			/* CONFIG_SYS_NAND_BOOT */
425
426.globl asm_delay
427asm_delay:
428	nop
429	subq.l	#1, %d1
430	bne	asm_delay
431	rts
432#endif			/* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
433
434.text
435	. = 0x400
436.globl _start
437_start:
438#if !defined(CONFIG_SERIAL_BOOT)
439	nop
440	nop
441	move.w	#0x2700,%sr		/* Mask off Interrupt */
442
443	/* Set vector base register at the beginning of the Flash */
444	move.l	#CFG_SYS_FLASH_BASE, %d0
445	movec	%d0, %VBR
446
447	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
448	movec	%d0, %RAMBAR1
449
450	/* initialize general use internal ram */
451	move.l	#0, %d0
452	move.l	#(ICACHE_STATUS), %a1	/* icache */
453	move.l	#(DCACHE_STATUS), %a2	/* dcache */
454	move.l	%d0, (%a1)
455	move.l	%d0, (%a2)
456
457	/* invalidate and disable cache */
458	move.l	#(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
459	movec	%d0, %CACR		/* Invalidate cache */
460	move.l	#0, %d0
461	movec	%d0, %ACR0
462	movec	%d0, %ACR1
463	movec	%d0, %ACR2
464	movec	%d0, %ACR3
465#else
466	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
467	movec	%d0, %RAMBAR1
468#endif
469
470	/* put relocation table address to a5 */
471	move.l	#__got_start, %a5
472
473	/* setup stack initially on top of internal static ram  */
474	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
475
476	/*
477	 * if configured, malloc_f arena will be reserved first,
478	 * then (and always) gd struct space will be reserved
479	 */
480	move.l	%sp, -(%sp)
481	move.l	#board_init_f_alloc_reserve, %a1
482	jsr	(%a1)
483
484	/* update stack and frame-pointers */
485	move.l	%d0, %sp
486	move.l	%sp, %fp
487
488	/* initialize reserved area */
489	move.l	%d0, -(%sp)
490	move.l	#board_init_f_init_reserve, %a1
491	jsr	(%a1)
492
493	/* run low-level CPU init code (from flash) */
494	move.l	#cpu_init_f, %a1
495	jsr	(%a1)
496
497	/* run low-level board init code (from flash) */
498	clr.l   %sp@-
499	move.l	#board_init_f, %a1
500	jsr	(%a1)
501
502	/* board_init_f() does not return */
503
504/******************************************************************************/
505
506/*
507 * void relocate_code(addr_sp, gd, addr_moni)
508 *
509 * This "function" does not return, instead it continues in RAM
510 * after relocating the monitor code.
511 *
512 * r3 = dest
513 * r4 = src
514 * r5 = length in bytes
515 * r6 = cachelinesize
516 */
517.globl relocate_code
518relocate_code:
519	link.w	%a6,#0
520	move.l	8(%a6), %sp		/* set new stack pointer */
521
522	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
523	move.l	16(%a6), %a0		/* Save copy of Destination Address */
524
525	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
526	move.l	#__init_end, %a2
527	move.l	%a0, %a3
528
529	/* copy the code to RAM */
5301:
531	move.l	(%a1)+, (%a3)+
532	cmp.l	%a1,%a2
533	bgt.s	1b
534
535#define R_68K_32	1
536#define R_68K_RELATIVE	22
537
538	move.l #(__rel_dyn_start), %a1
539	move.l #(__rel_dyn_end), %a2
540
541fixloop:
542	move.l	(%a1)+, %d1	/* Elf32_Rela r_offset */
543	move.l	(%a1)+, %d2	/* Elf32_Rela r_info */
544	move.l	(%a1)+, %d3	/* Elf32_Rela r_addend */
545
546	andi.l	#0xff, %d2
547	cmp.l	#R_68K_32, %d2
548	beq.s	fixup
549	cmp.l	#R_68K_RELATIVE, %d2
550	beq.s	fixup
551
552	bra	fixnext
553
554fixup:
555	/* relative fix: store addend plus offset at dest location */
556	move.l	%a0, %a3
557	add.l	%d1, %a3
558	sub.l   #CONFIG_SYS_MONITOR_BASE, %a3
559	move.l	(%a3), %d4
560	add.l	%a0, %d4
561	sub.l   #CONFIG_SYS_MONITOR_BASE, %d4
562	move.l	%d4, (%a3)
563
564fixnext:
565	cmp.l	%a1, %a2
566	bge.s	fixloop
567
568/*
569 * We are done. Do not return, instead branch to second part of board
570 * initialization, now running from RAM.
571 */
572	move.l	%a0, %a1
573	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
574	jmp	(%a1)
575
576in_ram:
577
578clear_bss:
579	/*
580	 * Now clear BSS segment
581	 */
582	move.l	#(_sbss), %a1
583	move.l	#(_ebss), %d1
5846:
585	clr.l	(%a1)+
586	cmp.l	%a1,%d1
587	bgt.s	6b
588
589	/*
590	 * fix got table in RAM
591	 */
592	move.l	#(__got_start), %a5	/* fix got pointer register a5 */
593
594	/* calculate relative jump to board_init_r in ram */
595	move.l	#(board_init_r), %a1
596
597	/* set parameters for board_init_r */
598	move.l	%a0,-(%sp)		/* dest_addr */
599	move.l	%d0,-(%sp)		/* gd */
600	jsr	(%a1)
601
602/******************************************************************************/
603
604/* exception code */
605.globl _fault
606_fault:
607	bra	_fault
608
609.globl _exc_handler
610_exc_handler:
611	SAVE_ALL
612	movel	%sp,%sp@-
613	bsr	exc_handler
614	addql	#4,%sp
615	RESTORE_ALL
616
617.globl _int_handler
618_int_handler:
619	SAVE_ALL
620	movel	%sp,%sp@-
621	bsr	int_handler
622	addql	#4,%sp
623	RESTORE_ALL
624
625/******************************************************************************/
626
627.align 4
628